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perf vendor events intel: Add uncore event list for Alderlake
Add JSON uncore events for Alderlake to perf. Based on JSON list v1.06: https://download.01.org/perfmon/ADL/ Signed-off-by: Zhengjun Xing <zhengjun.xing@linux.intel.com> Acked-by: Ian Rogers <irogers@google.com> Cc: Adrian Hunter <adrian.hunter@intel.com> Cc: Alexander Shishkin <alexander.shishkin@intel.com> Cc: Andi Kleen <ak@linux.intel.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: Kan Liang <kan.liang@linux.intel.com> Cc: Peter Zijlstra <peterz@infradead.org> Link: http://lore.kernel.org/lkml/20220224162350.1975130-1-zhengjun.xing@linux.intel.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
This commit is contained in:
Zhengjun Xing
Arnaldo Carvalho de Melo
parent
f9900dd005
commit
2c0fd42c1c
2 changed files with 262 additions and 0 deletions
222
tools/perf/pmu-events/arch/x86/alderlake/uncore-memory.json
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222
tools/perf/pmu-events/arch/x86/alderlake/uncore-memory.json
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[
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{
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"BriefDescription": "Number of clocks",
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"Counter": "0,1,2,3,4",
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"CounterType": "PGMABLE",
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"EventCode": "0x01",
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"EventName": "UNC_M_CLOCKTICKS",
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"PerPkg": "1",
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"Unit": "iMC"
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},
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{
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"BriefDescription": "Incoming VC0 read request",
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"Counter": "0,1,2,3,4",
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"CounterType": "PGMABLE",
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"EventCode": "0x02",
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"EventName": "UNC_M_VC0_REQUESTS_RD",
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"PerPkg": "1",
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"Unit": "iMC"
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},
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{
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"BriefDescription": "Incoming VC0 write request",
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"Counter": "0,1,2,3,4",
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"CounterType": "PGMABLE",
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"EventCode": "0x03",
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"EventName": "UNC_M_VC0_REQUESTS_WR",
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"PerPkg": "1",
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"Unit": "iMC"
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},
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{
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"BriefDescription": "Incoming VC1 read request",
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"Counter": "0,1,2,3,4",
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"CounterType": "PGMABLE",
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"EventCode": "0x04",
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"EventName": "UNC_M_VC1_REQUESTS_RD",
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"PerPkg": "1",
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"Unit": "iMC"
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},
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{
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"BriefDescription": "Incoming VC1 write request",
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"Counter": "0,1,2,3,4",
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"CounterType": "PGMABLE",
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"EventCode": "0x05",
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"EventName": "UNC_M_VC1_REQUESTS_WR",
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"PerPkg": "1",
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"Unit": "iMC"
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},
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{
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"BriefDescription": "Incoming read prefetch request from IA",
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"Counter": "0,1,2,3,4",
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"CounterType": "PGMABLE",
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"EventCode": "0x0A",
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"EventName": "UNC_M_PREFETCH_RD",
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"PerPkg": "1",
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"Unit": "iMC"
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},
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{
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"BriefDescription": "Any Rank at Hot state",
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"Counter": "0,1,2,3,4",
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"CounterType": "PGMABLE",
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"EventCode": "0x19",
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"EventName": "UNC_M_DRAM_THERMAL_HOT",
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"PerPkg": "1",
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"Unit": "iMC"
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},
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{
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"BriefDescription": "Any Rank at Warm state",
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"Counter": "0,1,2,3,4",
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"CounterType": "PGMABLE",
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"EventCode": "0x1A",
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"EventName": "UNC_M_DRAM_THERMAL_WARM",
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"PerPkg": "1",
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"Unit": "iMC"
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},
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{
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"BriefDescription": "incoming read request page status is Page Hit",
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"Counter": "0,1,2,3,4",
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"CounterType": "PGMABLE",
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"EventCode": "0x1C",
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"EventName": "UNC_M_DRAM_PAGE_HIT_RD",
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"PerPkg": "1",
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"Unit": "iMC"
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},
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{
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"BriefDescription": "incoming read request page status is Page Empty",
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"Counter": "0,1,2,3,4",
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"CounterType": "PGMABLE",
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"EventCode": "0x1D",
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"EventName": "UNC_M_DRAM_PAGE_EMPTY_RD",
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"PerPkg": "1",
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"Unit": "iMC"
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},
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{
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"BriefDescription": "incoming read request page status is Page Miss",
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"Counter": "0,1,2,3,4",
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"CounterType": "PGMABLE",
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"EventCode": "0x1E",
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"EventName": "UNC_M_DRAM_PAGE_MISS_RD",
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"PerPkg": "1",
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"Unit": "iMC"
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},
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{
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"BriefDescription": "incoming write request page status is Page Hit",
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"Counter": "0,1,2,3,4",
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"CounterType": "PGMABLE",
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"EventCode": "0x1F",
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"EventName": "UNC_M_DRAM_PAGE_HIT_WR",
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"PerPkg": "1",
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"Unit": "iMC"
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},
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{
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"BriefDescription": "incoming write request page status is Page Empty",
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"Counter": "0,1,2,3,4",
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"CounterType": "PGMABLE",
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"EventCode": "0x20",
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"EventName": "UNC_M_DRAM_PAGE_EMPTY_WR",
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"PerPkg": "1",
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"Unit": "iMC"
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},
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{
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"BriefDescription": "incoming write request page status is Page Miss",
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"Counter": "0,1,2,3,4",
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"CounterType": "PGMABLE",
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"EventCode": "0x21",
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"EventName": "UNC_M_DRAM_PAGE_MISS_WR",
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"PerPkg": "1",
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"Unit": "iMC"
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},
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{
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"BriefDescription": "Read CAS command sent to DRAM",
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"Counter": "0,1,2,3,4",
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"CounterType": "PGMABLE",
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"EventCode": "0x22",
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"EventName": "UNC_M_CAS_COUNT_RD",
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"PerPkg": "1",
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"Unit": "iMC"
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},
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{
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"BriefDescription": "Write CAS command sent to DRAM",
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"Counter": "0,1,2,3,4",
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"CounterType": "PGMABLE",
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"EventCode": "0x23",
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"EventName": "UNC_M_CAS_COUNT_WR",
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"PerPkg": "1",
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"Unit": "iMC"
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},
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{
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"BriefDescription": "ACT command for a read request sent to DRAM",
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"Counter": "0,1,2,3,4",
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"CounterType": "PGMABLE",
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"EventCode": "0x24",
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"EventName": "UNC_M_ACT_COUNT_RD",
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"PerPkg": "1",
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"Unit": "iMC"
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},
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{
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"BriefDescription": "ACT command for a write request sent to DRAM",
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"Counter": "0,1,2,3,4",
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"CounterType": "PGMABLE",
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"EventCode": "0x25",
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"EventName": "UNC_M_ACT_COUNT_WR",
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"PerPkg": "1",
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"Unit": "iMC"
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},
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{
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"BriefDescription": "ACT command sent to DRAM",
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"Counter": "0,1,2,3,4",
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"CounterType": "PGMABLE",
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"EventCode": "0x26",
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"EventName": "UNC_M_ACT_COUNT_TOTAL",
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"PerPkg": "1",
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"Unit": "iMC"
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},
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{
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"BriefDescription": "PRE command sent to DRAM for a read/write request",
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"Counter": "0,1,2,3,4",
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"CounterType": "PGMABLE",
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"EventCode": "0x27",
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"EventName": "UNC_M_PRE_COUNT_PAGE_MISS",
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"PerPkg": "1",
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"Unit": "iMC"
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},
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{
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"BriefDescription": "PRE command sent to DRAM due to page table idle timer expiration",
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"Counter": "0,1,2,3,4",
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"CounterType": "PGMABLE",
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"EventCode": "0x28",
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"EventName": "UNC_M_PRE_COUNT_IDLE",
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"PerPkg": "1",
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"Unit": "iMC"
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},
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{
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"BriefDescription": "Counts every 64B read request entering the Memory Controller 0 to DRAM (sum of all channels)",
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"CounterType": "FREERUN",
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"EventName": "UNC_MC0_RDCAS_COUNT_FREERUN",
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"PerPkg": "1",
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"Unit": "iMC"
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},
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{
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"BriefDescription": "Counts every 64B read request entering the Memory Controller 1 to DRAM (sum of all channels)",
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"Counter": "3",
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"CounterType": "FREERUN",
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"EventName": "UNC_MC1_RDCAS_COUNT_FREERUN",
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"PerPkg": "1",
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"Unit": "iMC"
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},
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{
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"BriefDescription": "Counts every 64B write request entering the Memory Controller 0 to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM",
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"Counter": "1",
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"CounterType": "FREERUN",
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"EventName": "UNC_MC0_WRCAS_COUNT_FREERUN",
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"PerPkg": "1",
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"Unit": "iMC"
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},
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{
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"BriefDescription": "Counts every 64B write request entering the Memory Controller 1 to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM",
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"Counter": "4",
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"CounterType": "FREERUN",
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"EventName": "UNC_MC1_WRCAS_COUNT_FREERUN",
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"PerPkg": "1",
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"Unit": "iMC"
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}
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]
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40
tools/perf/pmu-events/arch/x86/alderlake/uncore-other.json
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tools/perf/pmu-events/arch/x86/alderlake/uncore-other.json
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[
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{
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"BriefDescription": "This 48-bit fixed counter counts the UCLK cycles",
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"Counter": "Fixed",
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"CounterType": "PGMABLE",
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"EventCode": "0xff",
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"EventName": "UNC_CLOCK.SOCKET",
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"PerPkg": "1",
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"Unit": "CLOCK"
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},
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{
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"BriefDescription": "Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLC",
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"Counter": "0,1",
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"CounterType": "PGMABLE",
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"EventCode": "0x81",
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"EventName": "UNC_ARB_TRK_REQUESTS.ALL",
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"PerPkg": "1",
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"UMask": "0x01",
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"Unit": "ARB"
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},
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{
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"BriefDescription": "Number of requests allocated in Coherency Tracker",
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"Counter": "0,1",
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"CounterType": "PGMABLE",
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"EventCode": "0x84",
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"EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL",
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"PerPkg": "1",
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"UMask": "0x01",
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"Unit": "ARB"
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},
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{
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"BriefDescription": "Each cycle counts number of all outgoing valid entries in ReqTrk. Such entry is defined as valid from its allocation in ReqTrk till deallocation. Accounts for Coherent and non-coherent traffic",
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"CounterType": "PGMABLE",
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"EventCode": "0x80",
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"EventName": "UNC_ARB_TRK_OCCUPANCY.ALL",
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"PerPkg": "1",
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"UMask": "0x01",
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"Unit": "ARB"
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}
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]
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