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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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Samsung DTS ARM64 changes for v6.0
1. Add binding headers for several Exynos850 and ExynosAutov9 clocks. 2. ExynosAutov9: Add FSYS clock controller nodes. 3. ExynosAutov9: Document serial compatible (used in DTS). 4. Exynos850: Add Audio, IS, MFC clock controllers. Add IOMMU nodes. -----BEGIN PGP SIGNATURE----- iQJEBAABCgAuFiEE3dJiKD0RGyM7briowTdm5oaLg9cFAmMbVoEQHGtyemtAa2Vy bmVsLm9yZwAKCRDBN2bmhouD1+oyD/wIScAnh7VVTa1OXhHx3PRMxij3bHA8bka8 B+eTXuHDgomjyjOOysb8APouBAX9nVsi2HFTLOvL9cKLfOZ8mIJutQj70EEfRrg2 sdVrDgDkJjFkDDNbYyxoLWN/GE1GlambxyTX2BKqJa3GoOg7tcMmXFpy3Lik0XKP nxZdIi63aEZc96rqtoLBn4Ni7kWllNNKnGZabrxK4cs3jTHO0Ay+ZGp57exXwEgf JdTPaVCw8uB2jjStZESwnldsBZxzJFpwUG+R3cLOejXq8xHuvxpJgD8rvBWS7A8u 2zOA/qONL1J+B/3pLtlWJAAOXL9MPlxAxWzYOdcaV+vm8XCDhA1aDlJPP+STpcFy 5zBwm44rqEelgYqPS0CwtCigC0tCmsekMANnRUeCSAmzjRYq18dLF8S36AUPR6UK sAtrJwgaGwg6xgsIX4ZqpGKEwNnv6FhViXHGp6Dq3Gw/Czin4Q8sHhRBIhFkUn19 g4nerk+vzsILke4ZgVT0Hab6Yplrlestc7nxnkAAsPQMwSK9g29HionzNGgxW91m 7MupJq9KcDGOY3UvSID/L4Bh7XJm/oIqskQX/UGvVACkuprpPs9zlGoO0vwfsQKA 4HL27Bwvfb1msTFvpOVK4uU00S1sCBd7cnsvS1KoJaxOxSjlLlMwI+ZEUcl+PC5e vtkE60ZhfA== =bRQO -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmMfTh0ACgkQmmx57+YA GNkRqxAAlhirqrhRyy2MKuHiI0jJPqXCjbI8CWq1Snb9/aWjkn2Jvg7GChbRnpaS bUBMRlwo5ejMJA53zyhx7UMBLzfhrPdAVWZ81sy+EsLMcXRFQ1yXAuocHCMM8Sry ttNrof8gi94QOHdkJOqWOF8+/s96bfATms583UlCw5nQR7FX9PeE72zT49YAP5zG gUrTmLhZ16fDQDnrAcUJXEbDcSkXO7xsxy1fun0LmykS6bvHK4M5nWsNcYz0JJYm L+lQeM/xe3cyIsaqGRkiH+tu1YxCePNSIq2BcfMi+s0dYX0UKnfLAcsxrfVF434/ pfD/YlXdSnm9QhSowwTe9iDNObuXkxmYuTKJqS0kSmm0Ayc7KrAhZylF7POgYkwG KOWis+31f8vinpMKYmLbWKwmo8EgXTdIuANwwX5VyH42GtESpmxnSp6wQO5/i8S3 TPiG/R4sq5e23qpCez5CBU7ImnDObHCYflW0HLWi1YAUS1oRgVeXXWC+Zt0yzXyS IAnz3vwSQqnIbXyzVIQOl9rV+UYLzFixk+3QnXn3RfTEVzJzlKkXp3Jr5ntarW3M apqxOwJh7k9QZsawEjNtBNlWgasmD1ThDw7+rp3idbjBJGXppy/mKHBoD3PrzyWw AVG3L8SjNrHHxFvKqzDkmVF72tGee+t/vZHzoVLVuPjddkSf4Eo= =xnEY -----END PGP SIGNATURE----- Merge tag 'samsung-dt64-6.1' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/dt Samsung DTS ARM64 changes for v6.0 1. Add binding headers for several Exynos850 and ExynosAutov9 clocks. 2. ExynosAutov9: Add FSYS clock controller nodes. 3. ExynosAutov9: Document serial compatible (used in DTS). 4. Exynos850: Add Audio, IS, MFC clock controllers. Add IOMMU nodes. * tag 'samsung-dt64-6.1' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: dt-bindings: serial: samsung: add exynosautov9-uart compatible arm64: dts: exynos: Add SysMMU nodes for Exynos850 arm64: dts: exynos: Add CMU_AUD, CMU_IS and CMU_MFCMSCL for Exynos850 arm64: dts: exynosautov9: add fsys0/1 clock DT nodes dt-bindings: clock: exynos850: Add Exynos850 CMU_MFCMSCL dt-bindings: clock: exynos850: Add Exynos850 CMU_IS dt-bindings: clock: exynos850: Add Exynos850 CMU_AUD dt-bindings: clock: exynosautov9: add schema for cmu_fsys0/1 dt-bindings: clock: exynosautov9: add fsys1 clock definitions dt-bindings: clock: exynosautov9: add fys0 clock definitions dt-bindings: clock: exynosautov9: correct clock numbering of peric0/c1 Link: https://lore.kernel.org/r/20220909150849.820523-2-krzysztof.kozlowski@linaro.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
2c12f88cef
7 changed files with 459 additions and 30 deletions
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@ -33,10 +33,13 @@ properties:
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enum:
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- samsung,exynos850-cmu-top
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- samsung,exynos850-cmu-apm
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- samsung,exynos850-cmu-aud
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- samsung,exynos850-cmu-cmgp
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- samsung,exynos850-cmu-core
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- samsung,exynos850-cmu-dpu
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- samsung,exynos850-cmu-hsi
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- samsung,exynos850-cmu-is
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- samsung,exynos850-cmu-mfcmscl
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- samsung,exynos850-cmu-peri
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clocks:
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@ -88,6 +91,24 @@ allOf:
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- const: oscclk
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- const: dout_clkcmu_apm_bus
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos850-cmu-aud
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then:
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properties:
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clocks:
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items:
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- description: External reference clock (26 MHz)
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- description: AUD clock (from CMU_TOP)
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clock-names:
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items:
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- const: oscclk
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- const: dout_aud
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- if:
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properties:
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compatible:
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@ -172,6 +193,54 @@ allOf:
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- const: dout_hsi_mmc_card
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- const: dout_hsi_usb20drd
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos850-cmu-is
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then:
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properties:
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clocks:
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items:
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- description: External reference clock (26 MHz)
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- description: CMU_IS bus clock (from CMU_TOP)
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- description: Image Texture Processing core clock (from CMU_TOP)
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- description: Visual Recognition Accelerator clock (from CMU_TOP)
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- description: Geometric Distortion Correction clock (from CMU_TOP)
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clock-names:
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items:
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- const: oscclk
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- const: dout_is_bus
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- const: dout_is_itp
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- const: dout_is_vra
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- const: dout_is_gdc
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos850-cmu-mfcmscl
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then:
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properties:
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clocks:
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items:
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- description: External reference clock (26 MHz)
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- description: Multi-Format Codec clock (from CMU_TOP)
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- description: Memory to Memory Scaler clock (from CMU_TOP)
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- description: Multi-Channel Scaler clock (from CMU_TOP)
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- description: JPEG codec clock (from CMU_TOP)
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clock-names:
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items:
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- const: oscclk
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- const: dout_mfcmscl_mfc
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- const: dout_mfcmscl_m2m
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- const: dout_mfcmscl_mcsc
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- const: dout_mfcmscl_jpeg
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- if:
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properties:
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compatible:
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@ -35,6 +35,8 @@ properties:
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- samsung,exynosautov9-cmu-top
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- samsung,exynosautov9-cmu-busmc
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- samsung,exynosautov9-cmu-core
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- samsung,exynosautov9-cmu-fsys0
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- samsung,exynosautov9-cmu-fsys1
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- samsung,exynosautov9-cmu-fsys2
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- samsung,exynosautov9-cmu-peric0
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- samsung,exynosautov9-cmu-peric1
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@ -107,6 +109,48 @@ allOf:
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- const: oscclk
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- const: dout_clkcmu_core_bus
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynosautov9-cmu-fsys0
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then:
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properties:
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clocks:
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items:
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- description: External reference clock (26 MHz)
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- description: CMU_FSYS0 bus clock (from CMU_TOP)
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- description: CMU_FSYS0 pcie clock (from CMU_TOP)
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clock-names:
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items:
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- const: oscclk
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- const: dout_clkcmu_fsys0_bus
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- const: dout_clkcmu_fsys0_pcie
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynosautov9-cmu-fsys1
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then:
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properties:
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clocks:
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items:
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- description: External reference clock (26 MHz)
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- description: CMU_FSYS1 bus clock (from CMU_TOP)
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- description: CMU_FSYS1 mmc card clock (from CMU_TOP)
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- description: CMU_FSYS1 usb clock (from CMU_TOP)
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clock-names:
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items:
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- const: oscclk
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- const: dout_clkcmu_fsys1_bus
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- const: dout_clkcmu_fsys1_mmc_card
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- const: dout_clkcmu_fsys1_usbdrd
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- if:
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properties:
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compatible:
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@ -17,7 +17,10 @@ description: |+
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properties:
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compatible:
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items:
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oneOf:
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- items:
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- const: samsung,exynosautov9-uart
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- const: samsung,exynos850-uart
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- enum:
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- apple,s5l-uart
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- axis,artpec8-uart
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@ -286,6 +286,21 @@ cmu_top: clock-controller@120e0000 {
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clock-names = "oscclk";
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};
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cmu_mfcmscl: clock-controller@12c00000 {
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compatible = "samsung,exynos850-cmu-mfcmscl";
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reg = <0x12c00000 0x8000>;
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#clock-cells = <1>;
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clocks = <&oscclk>,
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<&cmu_top CLK_DOUT_MFCMSCL_MFC>,
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<&cmu_top CLK_DOUT_MFCMSCL_M2M>,
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<&cmu_top CLK_DOUT_MFCMSCL_MCSC>,
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<&cmu_top CLK_DOUT_MFCMSCL_JPEG>;
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clock-names = "oscclk", "dout_mfcmscl_mfc",
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"dout_mfcmscl_m2m", "dout_mfcmscl_mcsc",
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"dout_mfcmscl_jpeg";
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};
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cmu_dpu: clock-controller@13000000 {
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compatible = "samsung,exynos850-cmu-dpu";
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reg = <0x13000000 0x8000>;
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@ -308,6 +323,29 @@ cmu_hsi: clock-controller@13400000 {
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"dout_hsi_mmc_card", "dout_hsi_usb20drd";
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};
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cmu_is: clock-controller@14500000 {
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compatible = "samsung,exynos850-cmu-is";
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reg = <0x14500000 0x8000>;
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#clock-cells = <1>;
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clocks = <&oscclk>,
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<&cmu_top CLK_DOUT_IS_BUS>,
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<&cmu_top CLK_DOUT_IS_ITP>,
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<&cmu_top CLK_DOUT_IS_VRA>,
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<&cmu_top CLK_DOUT_IS_GDC>;
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clock-names = "oscclk", "dout_is_bus", "dout_is_itp",
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"dout_is_vra", "dout_is_gdc";
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};
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cmu_aud: clock-controller@14a00000 {
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compatible = "samsung,exynos850-cmu-aud";
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reg = <0x14a00000 0x8000>;
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#clock-cells = <1>;
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clocks = <&oscclk>, <&cmu_top CLK_DOUT_AUD>;
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clock-names = "oscclk", "dout_aud";
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};
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pinctrl_alive: pinctrl@11850000 {
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compatible = "samsung,exynos850-pinctrl";
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reg = <0x11850000 0x1000>;
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@ -465,6 +503,51 @@ i2c_6: i2c@13890000 {
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status = "disabled";
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};
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sysmmu_mfcmscl: sysmmu@12c50000 {
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compatible = "samsung,exynos-sysmmu";
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reg = <0x12c50000 0x9000>;
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interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "sysmmu";
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clocks = <&cmu_mfcmscl CLK_GOUT_MFCMSCL_SYSMMU_CLK>;
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#iommu-cells = <0>;
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};
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sysmmu_dpu: sysmmu@130c0000 {
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compatible = "samsung,exynos-sysmmu";
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reg = <0x130c0000 0x9000>;
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interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "sysmmu";
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clocks = <&cmu_dpu CLK_GOUT_DPU_SMMU_CLK>;
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#iommu-cells = <0>;
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};
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sysmmu_is0: sysmmu@14550000 {
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compatible = "samsung,exynos-sysmmu";
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reg = <0x14550000 0x9000>;
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interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "sysmmu";
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clocks = <&cmu_is CLK_GOUT_IS_SYSMMU_IS0_CLK>;
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#iommu-cells = <0>;
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};
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sysmmu_is1: sysmmu@14570000 {
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compatible = "samsung,exynos-sysmmu";
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reg = <0x14570000 0x9000>;
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interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "sysmmu";
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clocks = <&cmu_is CLK_GOUT_IS_SYSMMU_IS1_CLK>;
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#iommu-cells = <0>;
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};
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sysmmu_aud: sysmmu@14850000 {
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compatible = "samsung,exynos-sysmmu";
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reg = <0x14850000 0x9000>;
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interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "sysmmu";
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clocks = <&cmu_aud CLK_GOUT_AUD_SYSMMU_CLK>;
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#iommu-cells = <0>;
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};
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sysreg_peri: syscon@10020000 {
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compatible = "samsung,exynos850-sysreg", "syscon";
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reg = <0x10020000 0x10000>;
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@ -207,6 +207,34 @@ cmu_peric1: clock-controller@10800000 {
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"dout_clkcmu_peric1_ip";
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};
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cmu_fsys1: clock-controller@17040000 {
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compatible = "samsung,exynosautov9-cmu-fsys1";
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reg = <0x17040000 0x8000>;
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#clock-cells = <1>;
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clocks = <&xtcxo>,
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<&cmu_top DOUT_CLKCMU_FSYS1_BUS>,
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<&cmu_top GOUT_CLKCMU_FSYS1_MMC_CARD>,
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<&cmu_top DOUT_CLKCMU_FSYS1_USBDRD>;
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clock-names = "oscclk",
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"dout_clkcmu_fsys1_bus",
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"gout_clkcmu_fsys1_mmc_card",
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"dout_clkcmu_fsys1_usbdrd";
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};
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cmu_fsys0: clock-controller@17700000 {
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compatible = "samsung,exynosautov9-cmu-fsys0";
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reg = <0x17700000 0x8000>;
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#clock-cells = <1>;
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clocks = <&xtcxo>,
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<&cmu_top DOUT_CLKCMU_FSYS0_BUS>,
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<&cmu_top DOUT_CLKCMU_FSYS0_PCIE>;
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clock-names = "oscclk",
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"dout_clkcmu_fsys0_bus",
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"dout_clkcmu_fsys0_pcie";
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};
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cmu_fsys2: clock-controller@17c00000 {
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compatible = "samsung,exynosautov9-cmu-fsys2";
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reg = <0x17c00000 0x8000>;
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@ -58,7 +58,34 @@
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#define CLK_MOUT_CLKCMU_APM_BUS 46
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#define CLK_DOUT_CLKCMU_APM_BUS 47
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#define CLK_GOUT_CLKCMU_APM_BUS 48
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#define TOP_NR_CLK 49
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#define CLK_MOUT_AUD 49
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#define CLK_GOUT_AUD 50
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#define CLK_DOUT_AUD 51
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#define CLK_MOUT_IS_BUS 52
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#define CLK_MOUT_IS_ITP 53
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#define CLK_MOUT_IS_VRA 54
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#define CLK_MOUT_IS_GDC 55
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#define CLK_GOUT_IS_BUS 56
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#define CLK_GOUT_IS_ITP 57
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#define CLK_GOUT_IS_VRA 58
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#define CLK_GOUT_IS_GDC 59
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#define CLK_DOUT_IS_BUS 60
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#define CLK_DOUT_IS_ITP 61
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#define CLK_DOUT_IS_VRA 62
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#define CLK_DOUT_IS_GDC 63
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#define CLK_MOUT_MFCMSCL_MFC 64
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#define CLK_MOUT_MFCMSCL_M2M 65
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#define CLK_MOUT_MFCMSCL_MCSC 66
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#define CLK_MOUT_MFCMSCL_JPEG 67
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#define CLK_GOUT_MFCMSCL_MFC 68
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#define CLK_GOUT_MFCMSCL_M2M 69
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#define CLK_GOUT_MFCMSCL_MCSC 70
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#define CLK_GOUT_MFCMSCL_JPEG 71
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#define CLK_DOUT_MFCMSCL_MFC 72
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#define CLK_DOUT_MFCMSCL_M2M 73
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#define CLK_DOUT_MFCMSCL_MCSC 74
|
||||
#define CLK_DOUT_MFCMSCL_JPEG 75
|
||||
#define TOP_NR_CLK 76
|
||||
|
||||
/* CMU_APM */
|
||||
#define CLK_RCO_I3C_PMIC 1
|
||||
|
|
@ -87,6 +114,69 @@
|
|||
#define CLK_GOUT_SYSREG_APM_PCLK 24
|
||||
#define APM_NR_CLK 25
|
||||
|
||||
/* CMU_AUD */
|
||||
#define CLK_DOUT_AUD_AUDIF 1
|
||||
#define CLK_DOUT_AUD_BUSD 2
|
||||
#define CLK_DOUT_AUD_BUSP 3
|
||||
#define CLK_DOUT_AUD_CNT 4
|
||||
#define CLK_DOUT_AUD_CPU 5
|
||||
#define CLK_DOUT_AUD_CPU_ACLK 6
|
||||
#define CLK_DOUT_AUD_CPU_PCLKDBG 7
|
||||
#define CLK_DOUT_AUD_FM 8
|
||||
#define CLK_DOUT_AUD_FM_SPDY 9
|
||||
#define CLK_DOUT_AUD_MCLK 10
|
||||
#define CLK_DOUT_AUD_UAIF0 11
|
||||
#define CLK_DOUT_AUD_UAIF1 12
|
||||
#define CLK_DOUT_AUD_UAIF2 13
|
||||
#define CLK_DOUT_AUD_UAIF3 14
|
||||
#define CLK_DOUT_AUD_UAIF4 15
|
||||
#define CLK_DOUT_AUD_UAIF5 16
|
||||
#define CLK_DOUT_AUD_UAIF6 17
|
||||
#define CLK_FOUT_AUD_PLL 18
|
||||
#define CLK_GOUT_AUD_ABOX_ACLK 19
|
||||
#define CLK_GOUT_AUD_ASB_CCLK 20
|
||||
#define CLK_GOUT_AUD_CA32_CCLK 21
|
||||
#define CLK_GOUT_AUD_CNT_BCLK 22
|
||||
#define CLK_GOUT_AUD_CODEC_MCLK 23
|
||||
#define CLK_GOUT_AUD_DAP_CCLK 24
|
||||
#define CLK_GOUT_AUD_GPIO_PCLK 25
|
||||
#define CLK_GOUT_AUD_PPMU_ACLK 26
|
||||
#define CLK_GOUT_AUD_PPMU_PCLK 27
|
||||
#define CLK_GOUT_AUD_SPDY_BCLK 28
|
||||
#define CLK_GOUT_AUD_SYSMMU_CLK 29
|
||||
#define CLK_GOUT_AUD_SYSREG_PCLK 30
|
||||
#define CLK_GOUT_AUD_TZPC_PCLK 31
|
||||
#define CLK_GOUT_AUD_UAIF0_BCLK 32
|
||||
#define CLK_GOUT_AUD_UAIF1_BCLK 33
|
||||
#define CLK_GOUT_AUD_UAIF2_BCLK 34
|
||||
#define CLK_GOUT_AUD_UAIF3_BCLK 35
|
||||
#define CLK_GOUT_AUD_UAIF4_BCLK 36
|
||||
#define CLK_GOUT_AUD_UAIF5_BCLK 37
|
||||
#define CLK_GOUT_AUD_UAIF6_BCLK 38
|
||||
#define CLK_GOUT_AUD_WDT_PCLK 39
|
||||
#define CLK_MOUT_AUD_CPU 40
|
||||
#define CLK_MOUT_AUD_CPU_HCH 41
|
||||
#define CLK_MOUT_AUD_CPU_USER 42
|
||||
#define CLK_MOUT_AUD_FM 43
|
||||
#define CLK_MOUT_AUD_PLL 44
|
||||
#define CLK_MOUT_AUD_TICK_USB_USER 45
|
||||
#define CLK_MOUT_AUD_UAIF0 46
|
||||
#define CLK_MOUT_AUD_UAIF1 47
|
||||
#define CLK_MOUT_AUD_UAIF2 48
|
||||
#define CLK_MOUT_AUD_UAIF3 49
|
||||
#define CLK_MOUT_AUD_UAIF4 50
|
||||
#define CLK_MOUT_AUD_UAIF5 51
|
||||
#define CLK_MOUT_AUD_UAIF6 52
|
||||
#define IOCLK_AUDIOCDCLK0 53
|
||||
#define IOCLK_AUDIOCDCLK1 54
|
||||
#define IOCLK_AUDIOCDCLK2 55
|
||||
#define IOCLK_AUDIOCDCLK3 56
|
||||
#define IOCLK_AUDIOCDCLK4 57
|
||||
#define IOCLK_AUDIOCDCLK5 58
|
||||
#define IOCLK_AUDIOCDCLK6 59
|
||||
#define TICK_USB 60
|
||||
#define AUD_NR_CLK 61
|
||||
|
||||
/* CMU_CMGP */
|
||||
#define CLK_RCO_CMGP 1
|
||||
#define CLK_MOUT_CMGP_ADC 2
|
||||
|
|
@ -121,6 +211,50 @@
|
|||
#define CLK_GOUT_SYSREG_HSI_PCLK 13
|
||||
#define HSI_NR_CLK 14
|
||||
|
||||
/* CMU_IS */
|
||||
#define CLK_MOUT_IS_BUS_USER 1
|
||||
#define CLK_MOUT_IS_ITP_USER 2
|
||||
#define CLK_MOUT_IS_VRA_USER 3
|
||||
#define CLK_MOUT_IS_GDC_USER 4
|
||||
#define CLK_DOUT_IS_BUSP 5
|
||||
#define CLK_GOUT_IS_CMU_IS_PCLK 6
|
||||
#define CLK_GOUT_IS_CSIS0_ACLK 7
|
||||
#define CLK_GOUT_IS_CSIS1_ACLK 8
|
||||
#define CLK_GOUT_IS_CSIS2_ACLK 9
|
||||
#define CLK_GOUT_IS_TZPC_PCLK 10
|
||||
#define CLK_GOUT_IS_CSIS_DMA_CLK 11
|
||||
#define CLK_GOUT_IS_GDC_CLK 12
|
||||
#define CLK_GOUT_IS_IPP_CLK 13
|
||||
#define CLK_GOUT_IS_ITP_CLK 14
|
||||
#define CLK_GOUT_IS_MCSC_CLK 15
|
||||
#define CLK_GOUT_IS_VRA_CLK 16
|
||||
#define CLK_GOUT_IS_PPMU_IS0_ACLK 17
|
||||
#define CLK_GOUT_IS_PPMU_IS0_PCLK 18
|
||||
#define CLK_GOUT_IS_PPMU_IS1_ACLK 19
|
||||
#define CLK_GOUT_IS_PPMU_IS1_PCLK 20
|
||||
#define CLK_GOUT_IS_SYSMMU_IS0_CLK 21
|
||||
#define CLK_GOUT_IS_SYSMMU_IS1_CLK 22
|
||||
#define CLK_GOUT_IS_SYSREG_PCLK 23
|
||||
#define IS_NR_CLK 24
|
||||
|
||||
/* CMU_MFCMSCL */
|
||||
#define CLK_MOUT_MFCMSCL_MFC_USER 1
|
||||
#define CLK_MOUT_MFCMSCL_M2M_USER 2
|
||||
#define CLK_MOUT_MFCMSCL_MCSC_USER 3
|
||||
#define CLK_MOUT_MFCMSCL_JPEG_USER 4
|
||||
#define CLK_DOUT_MFCMSCL_BUSP 5
|
||||
#define CLK_GOUT_MFCMSCL_CMU_MFCMSCL_PCLK 6
|
||||
#define CLK_GOUT_MFCMSCL_TZPC_PCLK 7
|
||||
#define CLK_GOUT_MFCMSCL_JPEG_ACLK 8
|
||||
#define CLK_GOUT_MFCMSCL_M2M_ACLK 9
|
||||
#define CLK_GOUT_MFCMSCL_MCSC_CLK 10
|
||||
#define CLK_GOUT_MFCMSCL_MFC_ACLK 11
|
||||
#define CLK_GOUT_MFCMSCL_PPMU_ACLK 12
|
||||
#define CLK_GOUT_MFCMSCL_PPMU_PCLK 13
|
||||
#define CLK_GOUT_MFCMSCL_SYSMMU_CLK 14
|
||||
#define CLK_GOUT_MFCMSCL_SYSREG_PCLK 15
|
||||
#define MFCMSCL_NR_CLK 16
|
||||
|
||||
/* CMU_PERI */
|
||||
#define CLK_MOUT_PERI_BUS_USER 1
|
||||
#define CLK_MOUT_PERI_UART_USER 2
|
||||
|
|
|
|||
|
|
@ -185,6 +185,74 @@
|
|||
|
||||
#define CORE_NR_CLK 6
|
||||
|
||||
/* CMU_FSYS0 */
|
||||
#define CLK_MOUT_FSYS0_BUS_USER 1
|
||||
#define CLK_MOUT_FSYS0_PCIE_USER 2
|
||||
#define CLK_GOUT_FSYS0_BUS_PCLK 3
|
||||
|
||||
#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X1_REFCLK 4
|
||||
#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_REFCLK 5
|
||||
#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X1_DBI_ACLK 6
|
||||
#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X1_MSTR_ACLK 7
|
||||
#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X1_SLV_ACLK 8
|
||||
#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_DBI_ACLK 9
|
||||
#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_MSTR_ACLK 10
|
||||
#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_SLV_ACLK 11
|
||||
#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_PIPE_CLK 12
|
||||
#define CLK_GOUT_FSYS0_PCIE_GEN3A_2L0_CLK 13
|
||||
#define CLK_GOUT_FSYS0_PCIE_GEN3B_2L0_CLK 14
|
||||
|
||||
#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_REFCLK 15
|
||||
#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_REFCLK 16
|
||||
#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_DBI_ACLK 17
|
||||
#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_MSTR_ACLK 18
|
||||
#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_SLV_ACLK 19
|
||||
#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_DBI_ACLK 20
|
||||
#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_MSTR_ACLK 21
|
||||
#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_SLV_ACLK 22
|
||||
#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_PIPE_CLK 23
|
||||
#define CLK_GOUT_FSYS0_PCIE_GEN3A_2L1_CLK 24
|
||||
#define CLK_GOUT_FSYS0_PCIE_GEN3B_2L1_CLK 25
|
||||
|
||||
#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_REFCLK 26
|
||||
#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_REFCLK 27
|
||||
#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_DBI_ACLK 28
|
||||
#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_MSTR_ACLK 29
|
||||
#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_SLV_ACLK 30
|
||||
#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_DBI_ACLK 31
|
||||
#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_MSTR_ACLK 32
|
||||
#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_SLV_ACLK 33
|
||||
#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_PIPE_CLK 34
|
||||
#define CLK_GOUT_FSYS0_PCIE_GEN3A_4L_CLK 35
|
||||
#define CLK_GOUT_FSYS0_PCIE_GEN3B_4L_CLK 36
|
||||
|
||||
#define FSYS0_NR_CLK 37
|
||||
|
||||
/* CMU_FSYS1 */
|
||||
#define FOUT_MMC_PLL 1
|
||||
|
||||
#define CLK_MOUT_FSYS1_BUS_USER 2
|
||||
#define CLK_MOUT_FSYS1_MMC_PLL 3
|
||||
#define CLK_MOUT_FSYS1_MMC_CARD_USER 4
|
||||
#define CLK_MOUT_FSYS1_USBDRD_USER 5
|
||||
#define CLK_MOUT_FSYS1_MMC_CARD 6
|
||||
|
||||
#define CLK_DOUT_FSYS1_MMC_CARD 7
|
||||
|
||||
#define CLK_GOUT_FSYS1_PCLK 8
|
||||
#define CLK_GOUT_FSYS1_MMC_CARD_SDCLKIN 9
|
||||
#define CLK_GOUT_FSYS1_MMC_CARD_ACLK 10
|
||||
#define CLK_GOUT_FSYS1_USB20DRD_0_REFCLK 11
|
||||
#define CLK_GOUT_FSYS1_USB20DRD_1_REFCLK 12
|
||||
#define CLK_GOUT_FSYS1_USB30DRD_0_REFCLK 13
|
||||
#define CLK_GOUT_FSYS1_USB30DRD_1_REFCLK 14
|
||||
#define CLK_GOUT_FSYS1_USB20_0_ACLK 15
|
||||
#define CLK_GOUT_FSYS1_USB20_1_ACLK 16
|
||||
#define CLK_GOUT_FSYS1_USB30_0_ACLK 17
|
||||
#define CLK_GOUT_FSYS1_USB30_1_ACLK 18
|
||||
|
||||
#define FSYS1_NR_CLK 19
|
||||
|
||||
/* CMU_FSYS2 */
|
||||
#define CLK_MOUT_FSYS2_BUS_USER 1
|
||||
#define CLK_MOUT_FSYS2_UFS_EMBD_USER 2
|
||||
|
|
@ -226,21 +294,21 @@
|
|||
#define CLK_GOUT_PERIC0_IPCLK_8 28
|
||||
#define CLK_GOUT_PERIC0_IPCLK_9 29
|
||||
#define CLK_GOUT_PERIC0_IPCLK_10 30
|
||||
#define CLK_GOUT_PERIC0_IPCLK_11 30
|
||||
#define CLK_GOUT_PERIC0_PCLK_0 31
|
||||
#define CLK_GOUT_PERIC0_PCLK_1 32
|
||||
#define CLK_GOUT_PERIC0_PCLK_2 33
|
||||
#define CLK_GOUT_PERIC0_PCLK_3 34
|
||||
#define CLK_GOUT_PERIC0_PCLK_4 35
|
||||
#define CLK_GOUT_PERIC0_PCLK_5 36
|
||||
#define CLK_GOUT_PERIC0_PCLK_6 37
|
||||
#define CLK_GOUT_PERIC0_PCLK_7 38
|
||||
#define CLK_GOUT_PERIC0_PCLK_8 39
|
||||
#define CLK_GOUT_PERIC0_PCLK_9 40
|
||||
#define CLK_GOUT_PERIC0_PCLK_10 41
|
||||
#define CLK_GOUT_PERIC0_PCLK_11 42
|
||||
#define CLK_GOUT_PERIC0_IPCLK_11 31
|
||||
#define CLK_GOUT_PERIC0_PCLK_0 32
|
||||
#define CLK_GOUT_PERIC0_PCLK_1 33
|
||||
#define CLK_GOUT_PERIC0_PCLK_2 34
|
||||
#define CLK_GOUT_PERIC0_PCLK_3 35
|
||||
#define CLK_GOUT_PERIC0_PCLK_4 36
|
||||
#define CLK_GOUT_PERIC0_PCLK_5 37
|
||||
#define CLK_GOUT_PERIC0_PCLK_6 38
|
||||
#define CLK_GOUT_PERIC0_PCLK_7 39
|
||||
#define CLK_GOUT_PERIC0_PCLK_8 40
|
||||
#define CLK_GOUT_PERIC0_PCLK_9 41
|
||||
#define CLK_GOUT_PERIC0_PCLK_10 42
|
||||
#define CLK_GOUT_PERIC0_PCLK_11 43
|
||||
|
||||
#define PERIC0_NR_CLK 43
|
||||
#define PERIC0_NR_CLK 44
|
||||
|
||||
/* CMU_PERIC1 */
|
||||
#define CLK_MOUT_PERIC1_BUS_USER 1
|
||||
|
|
@ -272,21 +340,21 @@
|
|||
#define CLK_GOUT_PERIC1_IPCLK_8 28
|
||||
#define CLK_GOUT_PERIC1_IPCLK_9 29
|
||||
#define CLK_GOUT_PERIC1_IPCLK_10 30
|
||||
#define CLK_GOUT_PERIC1_IPCLK_11 30
|
||||
#define CLK_GOUT_PERIC1_PCLK_0 31
|
||||
#define CLK_GOUT_PERIC1_PCLK_1 32
|
||||
#define CLK_GOUT_PERIC1_PCLK_2 33
|
||||
#define CLK_GOUT_PERIC1_PCLK_3 34
|
||||
#define CLK_GOUT_PERIC1_PCLK_4 35
|
||||
#define CLK_GOUT_PERIC1_PCLK_5 36
|
||||
#define CLK_GOUT_PERIC1_PCLK_6 37
|
||||
#define CLK_GOUT_PERIC1_PCLK_7 38
|
||||
#define CLK_GOUT_PERIC1_PCLK_8 39
|
||||
#define CLK_GOUT_PERIC1_PCLK_9 40
|
||||
#define CLK_GOUT_PERIC1_PCLK_10 41
|
||||
#define CLK_GOUT_PERIC1_PCLK_11 42
|
||||
#define CLK_GOUT_PERIC1_IPCLK_11 31
|
||||
#define CLK_GOUT_PERIC1_PCLK_0 32
|
||||
#define CLK_GOUT_PERIC1_PCLK_1 33
|
||||
#define CLK_GOUT_PERIC1_PCLK_2 34
|
||||
#define CLK_GOUT_PERIC1_PCLK_3 35
|
||||
#define CLK_GOUT_PERIC1_PCLK_4 36
|
||||
#define CLK_GOUT_PERIC1_PCLK_5 37
|
||||
#define CLK_GOUT_PERIC1_PCLK_6 38
|
||||
#define CLK_GOUT_PERIC1_PCLK_7 39
|
||||
#define CLK_GOUT_PERIC1_PCLK_8 40
|
||||
#define CLK_GOUT_PERIC1_PCLK_9 41
|
||||
#define CLK_GOUT_PERIC1_PCLK_10 42
|
||||
#define CLK_GOUT_PERIC1_PCLK_11 43
|
||||
|
||||
#define PERIC1_NR_CLK 43
|
||||
#define PERIC1_NR_CLK 44
|
||||
|
||||
/* CMU_PERIS */
|
||||
#define CLK_MOUT_PERIS_BUS_USER 1
|
||||
|
|
|
|||
Loading…
Reference in a new issue