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clk: sunxi: A31: Fix wrong AHB gate number
[ Upstream commitee0b27a3a4
] According to the manual the gate clock for MMC3 is at bit 11, and NAND1 is controlled by bit 12. Fix the gate bit definitions in the clock driver. Fixes:c6e6c96d8f
("clk: sunxi-ng: Add A31/A31s clocks") Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
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1 changed files with 2 additions and 2 deletions
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@ -252,9 +252,9 @@ static SUNXI_CCU_GATE(ahb1_mmc1_clk, "ahb1-mmc1", "ahb1",
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static SUNXI_CCU_GATE(ahb1_mmc2_clk, "ahb1-mmc2", "ahb1",
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0x060, BIT(10), 0);
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static SUNXI_CCU_GATE(ahb1_mmc3_clk, "ahb1-mmc3", "ahb1",
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0x060, BIT(12), 0);
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0x060, BIT(11), 0);
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static SUNXI_CCU_GATE(ahb1_nand1_clk, "ahb1-nand1", "ahb1",
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0x060, BIT(13), 0);
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0x060, BIT(12), 0);
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static SUNXI_CCU_GATE(ahb1_nand0_clk, "ahb1-nand0", "ahb1",
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0x060, BIT(13), 0);
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static SUNXI_CCU_GATE(ahb1_sdram_clk, "ahb1-sdram", "ahb1",
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