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clk: rockchip: associate SCLK_MAC_PLL and disable reparenting on rk3036
The emac needs constant and very specific rate but the possible PLL-sources are very limited, so we expect the PLL source to be set manually on per board and don't want it to get changed in an automatic way later. So add the necessary clock-id and disable reparenting on set_rate calls. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Heiko Stuebner <heiko@sntech.de> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: linux-clk@vger.kernel.org Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -343,7 +343,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {
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RK2928_CLKSEL_CON(16), 0, 2, MFLAGS, 2, 5, DFLAGS,
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RK2928_CLKGATE_CON(10), 5, GFLAGS),
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COMPOSITE_NOGATE(0, "mac_pll_src", mux_pll_src_3plls_p, 0,
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COMPOSITE_NOGATE(SCLK_MACPLL, "mac_pll_src", mux_pll_src_3plls_p, CLK_SET_RATE_NO_REPARENT,
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RK2928_CLKSEL_CON(21), 0, 2, MFLAGS, 9, 5, DFLAGS),
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MUX(SCLK_MACREF, "mac_clk_ref", mux_mac_p, CLK_SET_RATE_PARENT,
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RK2928_CLKSEL_CON(21), 3, 1, MFLAGS),
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