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drm/i195: Extract cnl_ddi_{enable,disable}_clock()
Extract the DDI clock routing for CNL into the new vfuncs. v2: s/dev_priv/i915/ (Lucas) Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210205214634.19341-6-ville.syrjala@linux.intel.com
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2c7b1d340f
1 changed files with 42 additions and 20 deletions
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@ -1853,7 +1853,6 @@ void intel_ddi_clk_select(struct intel_encoder *encoder,
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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enum port port = encoder->port;
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enum phy phy = intel_port_to_phy(dev_priv, port);
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u32 val;
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const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
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if (drm_WARN_ON(&dev_priv->drm, !pll))
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@ -1872,21 +1871,6 @@ void intel_ddi_clk_select(struct intel_encoder *encoder,
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*/
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intel_de_write(dev_priv, DDI_CLK_SEL(port),
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DDI_CLK_SEL_MG);
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} else if (IS_CANNONLAKE(dev_priv)) {
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/* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
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val = intel_de_read(dev_priv, DPCLKA_CFGCR0);
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val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
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val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
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intel_de_write(dev_priv, DPCLKA_CFGCR0, val);
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/*
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* Configure DPCLKA_CFGCR0 to turn on the clock for the DDI.
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* This step and the step before must be done with separate
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* register writes.
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*/
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val = intel_de_read(dev_priv, DPCLKA_CFGCR0);
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val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
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intel_de_write(dev_priv, DPCLKA_CFGCR0, val);
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}
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mutex_unlock(&dev_priv->dpll.lock);
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@ -1903,12 +1887,47 @@ static void intel_ddi_clk_disable(struct intel_encoder *encoder)
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(IS_JSL_EHL(dev_priv) && port >= PORT_C))
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intel_de_write(dev_priv, DDI_CLK_SEL(port),
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DDI_CLK_SEL_NONE);
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} else if (IS_CANNONLAKE(dev_priv)) {
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intel_de_write(dev_priv, DPCLKA_CFGCR0,
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intel_de_read(dev_priv, DPCLKA_CFGCR0) | DPCLKA_CFGCR0_DDI_CLK_OFF(port));
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}
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}
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static void cnl_ddi_enable_clock(struct intel_encoder *encoder,
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const struct intel_crtc_state *crtc_state)
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{
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struct drm_i915_private *i915 = to_i915(encoder->base.dev);
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const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
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enum port port = encoder->port;
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u32 val;
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if (drm_WARN_ON(&i915->drm, !pll))
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return;
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mutex_lock(&i915->dpll.lock);
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val = intel_de_read(i915, DPCLKA_CFGCR0);
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val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
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val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
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intel_de_write(i915, DPCLKA_CFGCR0, val);
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/*
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* "This step and the step before must be
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* done with separate register writes."
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*/
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val = intel_de_read(i915, DPCLKA_CFGCR0);
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val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
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intel_de_write(i915, DPCLKA_CFGCR0, val);
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mutex_unlock(&i915->dpll.lock);
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}
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static void cnl_ddi_disable_clock(struct intel_encoder *encoder)
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{
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struct drm_i915_private *i915 = to_i915(encoder->base.dev);
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enum port port = encoder->port;
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intel_de_write(i915, DPCLKA_CFGCR0,
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intel_de_read(i915, DPCLKA_CFGCR0) | DPCLKA_CFGCR0_DDI_CLK_OFF(port));
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}
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static void skl_ddi_enable_clock(struct intel_encoder *encoder,
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const struct intel_crtc_state *crtc_state)
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{
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@ -4118,7 +4137,10 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
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encoder->cloneable = 0;
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encoder->pipe_mask = ~0;
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if (IS_GEN9_BC(dev_priv)) {
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if (IS_CANNONLAKE(dev_priv)) {
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encoder->enable_clock = cnl_ddi_enable_clock;
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encoder->disable_clock = cnl_ddi_disable_clock;
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} else if (IS_GEN9_BC(dev_priv)) {
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encoder->enable_clock = skl_ddi_enable_clock;
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encoder->disable_clock = skl_ddi_disable_clock;
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} else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
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