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drm/amdgpu/gfx10: update CGTS_TCC_DISABLE and CGTS_USER_TCC_DISABLE register offsets for VGH
For Vangogh: The offset of the CGTS_TCC_DISABLE is 0x5006 by calculation. The offset of the CGTS_USER_TCC_DISABLE is 0x5007 by calculation. Signed-off-by: chen gong <curry.gong@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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1 changed files with 16 additions and 2 deletions
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@ -98,6 +98,10 @@
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#define mmGCR_GENERAL_CNTL_Sienna_Cichlid 0x1580
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#define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX 0
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#define mmCGTS_TCC_DISABLE_Vangogh 0x5006
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#define mmCGTS_TCC_DISABLE_Vangogh_BASE_IDX 1
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#define mmCGTS_USER_TCC_DISABLE_Vangogh 0x5007
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#define mmCGTS_USER_TCC_DISABLE_Vangogh_BASE_IDX 1
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#define mmGOLDEN_TSC_COUNT_UPPER_Vangogh 0x0025
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#define mmGOLDEN_TSC_COUNT_UPPER_Vangogh_BASE_IDX 1
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#define mmGOLDEN_TSC_COUNT_LOWER_Vangogh 0x0026
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@ -4933,8 +4937,18 @@ static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
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static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev)
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{
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/* TCCs are global (not instanced). */
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uint32_t tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) |
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RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE);
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uint32_t tcc_disable;
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switch (adev->asic_type) {
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case CHIP_VANGOGH:
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tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE_Vangogh) |
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RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE_Vangogh);
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break;
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default:
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tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) |
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RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE);
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break;
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}
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adev->gfx.config.tcc_disabled_mask =
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REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) |
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