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e1000: add mmiowb() for IA64 to sync tail writes
IA64 SMP systems were seeing TX issues with multiple cpu's attempting to write tail registers unordered. This mmiowb() fixes the issue. Signed-off-by: Auke Kok <auke-jan.h.kok@intel.com> Signed-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com>
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@ -2867,6 +2867,9 @@ e1000_tx_queue(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
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tx_ring->next_to_use = i;
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writel(i, adapter->hw.hw_addr + tx_ring->tdt);
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/* we need this if more than one processor can write to our tail
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* at a time, it syncronizes IO on IA64/Altix systems */
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mmiowb();
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}
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/**
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