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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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drm/i915: Embedded struct drm_crtc_state in intel_crtc_state
And get rid of the duplicate mode structures. This patch was generated with the following semantic patch: @@ @@ struct intel_crtc_state { +struct drm_crtc_state base; + ... -struct drm_display_mode requested_mode; -struct drm_display_mode adjusted_mode; ... } @@ struct intel_crtc_state *state; @@ -state->adjusted_mode +state->base.adjusted_mode @@ struct intel_crtc_state *state; @@ -state->requested_mode +state->base.mode @@ struct intel_crtc_state state; @@ -state.adjusted_mode +state.base.adjusted_mode @@ struct intel_crtc_state state; @@ -state.requested_mode +state.base.mode @@ struct drm_crtc *crtc; @@ -to_intel_crtc(crtc)->config.adjusted_mode +to_intel_crtc(crtc)->config.base.adjusted_mode @@ identifier member; expression E; @@ -PIPE_CONF_CHECK_FLAGS(adjusted_mode.member, E); +PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.member, E); @@ identifier member; @@ -PIPE_CONF_CHECK_I(adjusted_mode.member); +PIPE_CONF_CHECK_I(base.adjusted_mode.member); @@ identifier member; @@ -PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.member); +PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.member); v2: Completely generate the patch with cocci. (Ander) Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
parent
5cec258b4f
commit
2d112de7db
20 changed files with 157 additions and 164 deletions
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@ -593,7 +593,7 @@ static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
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struct intel_crtc *intel_crtc =
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struct intel_crtc *intel_crtc =
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to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
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to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
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const struct drm_display_mode *mode =
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const struct drm_display_mode *mode =
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&intel_crtc->config.adjusted_mode;
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&intel_crtc->config.base.adjusted_mode;
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htotal = mode->crtc_htotal;
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htotal = mode->crtc_htotal;
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hsync_start = mode->crtc_hsync_start;
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hsync_start = mode->crtc_hsync_start;
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@ -664,7 +664,7 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
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{
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{
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struct drm_device *dev = crtc->base.dev;
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struct drm_device *dev = crtc->base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct drm_i915_private *dev_priv = dev->dev_private;
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const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
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const struct drm_display_mode *mode = &crtc->config.base.adjusted_mode;
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enum pipe pipe = crtc->pipe;
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enum pipe pipe = crtc->pipe;
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int position, vtotal;
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int position, vtotal;
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@ -691,7 +691,7 @@ static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
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struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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const struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
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const struct drm_display_mode *mode = &intel_crtc->config.base.adjusted_mode;
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int position;
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int position;
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int vbl_start, vbl_end, hsync_start, htotal, vtotal;
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int vbl_start, vbl_end, hsync_start, htotal, vtotal;
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bool in_vbl = true;
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bool in_vbl = true;
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@ -849,7 +849,7 @@ static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
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return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
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return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
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vblank_time, flags,
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vblank_time, flags,
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crtc,
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crtc,
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&to_intel_crtc(crtc)->config.adjusted_mode);
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&to_intel_crtc(crtc)->config.base.adjusted_mode);
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}
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}
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static bool intel_hpd_irq_event(struct drm_device *dev,
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static bool intel_hpd_irq_event(struct drm_device *dev,
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@ -400,7 +400,7 @@ void intel_audio_codec_enable(struct intel_encoder *intel_encoder)
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{
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{
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struct drm_encoder *encoder = &intel_encoder->base;
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struct drm_encoder *encoder = &intel_encoder->base;
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struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
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struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
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struct drm_display_mode *mode = &crtc->config.adjusted_mode;
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struct drm_display_mode *mode = &crtc->config.base.adjusted_mode;
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struct drm_connector *connector;
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struct drm_connector *connector;
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struct drm_device *dev = encoder->dev;
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struct drm_device *dev = encoder->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct drm_i915_private *dev_priv = dev->dev_private;
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@ -115,14 +115,14 @@ static void intel_crt_get_config(struct intel_encoder *encoder,
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struct drm_device *dev = encoder->base.dev;
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struct drm_device *dev = encoder->base.dev;
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int dotclock;
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int dotclock;
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pipe_config->adjusted_mode.flags |= intel_crt_get_flags(encoder);
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pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder);
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dotclock = pipe_config->port_clock;
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dotclock = pipe_config->port_clock;
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if (HAS_PCH_SPLIT(dev))
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if (HAS_PCH_SPLIT(dev))
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ironlake_check_encoder_dotclock(pipe_config, dotclock);
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ironlake_check_encoder_dotclock(pipe_config, dotclock);
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pipe_config->adjusted_mode.crtc_clock = dotclock;
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pipe_config->base.adjusted_mode.crtc_clock = dotclock;
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}
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}
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static void hsw_crt_get_config(struct intel_encoder *encoder,
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static void hsw_crt_get_config(struct intel_encoder *encoder,
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@ -130,11 +130,11 @@ static void hsw_crt_get_config(struct intel_encoder *encoder,
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{
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{
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intel_ddi_get_config(encoder, pipe_config);
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intel_ddi_get_config(encoder, pipe_config);
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pipe_config->adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC |
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pipe_config->base.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC |
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DRM_MODE_FLAG_NHSYNC |
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DRM_MODE_FLAG_NHSYNC |
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DRM_MODE_FLAG_PVSYNC |
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DRM_MODE_FLAG_PVSYNC |
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DRM_MODE_FLAG_NVSYNC);
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DRM_MODE_FLAG_NVSYNC);
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pipe_config->adjusted_mode.flags |= intel_crt_get_flags(encoder);
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pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder);
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}
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}
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static void hsw_crt_pre_enable(struct intel_encoder *encoder)
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static void hsw_crt_pre_enable(struct intel_encoder *encoder)
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@ -157,7 +157,7 @@ static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode)
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crt *crt = intel_encoder_to_crt(encoder);
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struct intel_crt *crt = intel_encoder_to_crt(encoder);
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struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
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struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
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struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
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struct drm_display_mode *adjusted_mode = &crtc->config.base.adjusted_mode;
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u32 adpa;
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u32 adpa;
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if (INTEL_INFO(dev)->gen >= 5)
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if (INTEL_INFO(dev)->gen >= 5)
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@ -768,11 +768,11 @@ static void skl_ddi_clock_get(struct intel_encoder *encoder,
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pipe_config->port_clock = link_clock;
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pipe_config->port_clock = link_clock;
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if (pipe_config->has_dp_encoder)
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if (pipe_config->has_dp_encoder)
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pipe_config->adjusted_mode.crtc_clock =
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pipe_config->base.adjusted_mode.crtc_clock =
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intel_dotclock_calculate(pipe_config->port_clock,
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intel_dotclock_calculate(pipe_config->port_clock,
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&pipe_config->dp_m_n);
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&pipe_config->dp_m_n);
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else
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else
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pipe_config->adjusted_mode.crtc_clock = pipe_config->port_clock;
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pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
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}
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}
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static void hsw_ddi_clock_get(struct intel_encoder *encoder,
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static void hsw_ddi_clock_get(struct intel_encoder *encoder,
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@ -820,15 +820,15 @@ static void hsw_ddi_clock_get(struct intel_encoder *encoder,
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pipe_config->port_clock = link_clock * 2;
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pipe_config->port_clock = link_clock * 2;
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if (pipe_config->has_pch_encoder)
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if (pipe_config->has_pch_encoder)
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pipe_config->adjusted_mode.crtc_clock =
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pipe_config->base.adjusted_mode.crtc_clock =
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intel_dotclock_calculate(pipe_config->port_clock,
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intel_dotclock_calculate(pipe_config->port_clock,
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&pipe_config->fdi_m_n);
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&pipe_config->fdi_m_n);
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else if (pipe_config->has_dp_encoder)
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else if (pipe_config->has_dp_encoder)
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pipe_config->adjusted_mode.crtc_clock =
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pipe_config->base.adjusted_mode.crtc_clock =
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intel_dotclock_calculate(pipe_config->port_clock,
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intel_dotclock_calculate(pipe_config->port_clock,
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&pipe_config->dp_m_n);
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&pipe_config->dp_m_n);
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else
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else
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pipe_config->adjusted_mode.crtc_clock = pipe_config->port_clock;
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pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
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}
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}
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void intel_ddi_clock_get(struct intel_encoder *encoder,
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void intel_ddi_clock_get(struct intel_encoder *encoder,
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@ -1261,9 +1261,9 @@ void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
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BUG();
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BUG();
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}
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}
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if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
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if (intel_crtc->config.base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
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temp |= TRANS_DDI_PVSYNC;
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temp |= TRANS_DDI_PVSYNC;
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if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
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if (intel_crtc->config.base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
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temp |= TRANS_DDI_PHSYNC;
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temp |= TRANS_DDI_PHSYNC;
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if (cpu_transcoder == TRANSCODER_EDP) {
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if (cpu_transcoder == TRANSCODER_EDP) {
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@ -1533,7 +1533,7 @@ static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
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intel_hdmi->set_infoframes(encoder,
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intel_hdmi->set_infoframes(encoder,
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crtc->config.has_hdmi_sink,
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crtc->config.has_hdmi_sink,
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&crtc->config.adjusted_mode);
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&crtc->config.base.adjusted_mode);
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}
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}
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}
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}
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@ -2045,7 +2045,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
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else
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else
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flags |= DRM_MODE_FLAG_NVSYNC;
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flags |= DRM_MODE_FLAG_NVSYNC;
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pipe_config->adjusted_mode.flags |= flags;
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pipe_config->base.adjusted_mode.flags |= flags;
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switch (temp & TRANS_DDI_BPC_MASK) {
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switch (temp & TRANS_DDI_BPC_MASK) {
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case TRANS_DDI_BPC_6:
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case TRANS_DDI_BPC_6:
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@ -897,7 +897,7 @@ bool intel_crtc_active(struct drm_crtc *crtc)
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* properly reconstruct framebuffers.
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* properly reconstruct framebuffers.
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*/
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*/
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return intel_crtc->active && crtc->primary->fb &&
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return intel_crtc->active && crtc->primary->fb &&
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intel_crtc->config.adjusted_mode.crtc_clock;
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intel_crtc->config.base.adjusted_mode.crtc_clock;
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}
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}
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enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
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enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
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@ -2941,7 +2941,7 @@ static void intel_update_pipe_size(struct intel_crtc *crtc)
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* then update the pipesrc and pfit state, even on the flip path.
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* then update the pipesrc and pfit state, even on the flip path.
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*/
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*/
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adjusted_mode = &crtc->config.adjusted_mode;
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adjusted_mode = &crtc->config.base.adjusted_mode;
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I915_WRITE(PIPESRC(crtc->pipe),
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I915_WRITE(PIPESRC(crtc->pipe),
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((adjusted_mode->crtc_hdisplay - 1) << 16) |
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((adjusted_mode->crtc_hdisplay - 1) << 16) |
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@ -3577,7 +3577,7 @@ static void lpt_program_iclkip(struct drm_crtc *crtc)
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{
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{
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struct drm_device *dev = crtc->dev;
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struct drm_device *dev = crtc->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct drm_i915_private *dev_priv = dev->dev_private;
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int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
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int clock = to_intel_crtc(crtc)->config.base.adjusted_mode.crtc_clock;
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u32 divsel, phaseinc, auxdiv, phasedir = 0;
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u32 divsel, phaseinc, auxdiv, phasedir = 0;
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u32 temp;
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u32 temp;
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@ -4908,7 +4908,7 @@ static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
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for_each_intel_crtc(dev, intel_crtc) {
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for_each_intel_crtc(dev, intel_crtc) {
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if (intel_crtc->new_enabled)
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if (intel_crtc->new_enabled)
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max_pixclk = max(max_pixclk,
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max_pixclk = max(max_pixclk,
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intel_crtc->new_config->adjusted_mode.crtc_clock);
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intel_crtc->new_config->base.adjusted_mode.crtc_clock);
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}
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}
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return max_pixclk;
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return max_pixclk;
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@ -5429,7 +5429,7 @@ static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
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struct intel_crtc_state *pipe_config)
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struct intel_crtc_state *pipe_config)
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{
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{
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struct drm_device *dev = intel_crtc->base.dev;
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struct drm_device *dev = intel_crtc->base.dev;
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struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
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struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
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int lane, link_bw, fdi_dotclock;
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int lane, link_bw, fdi_dotclock;
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bool setup_ok, needs_recompute = false;
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bool setup_ok, needs_recompute = false;
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@ -5484,7 +5484,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
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{
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{
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struct drm_device *dev = crtc->base.dev;
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struct drm_device *dev = crtc->base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
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struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
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/* FIXME should check pixel clock limits on all platforms */
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/* FIXME should check pixel clock limits on all platforms */
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if (INTEL_INFO(dev)->gen < 4) {
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if (INTEL_INFO(dev)->gen < 4) {
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@ -6206,7 +6206,7 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
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enum pipe pipe = intel_crtc->pipe;
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enum pipe pipe = intel_crtc->pipe;
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enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
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enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
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struct drm_display_mode *adjusted_mode =
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struct drm_display_mode *adjusted_mode =
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&intel_crtc->config.adjusted_mode;
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&intel_crtc->config.base.adjusted_mode;
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uint32_t crtc_vtotal, crtc_vblank_end;
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uint32_t crtc_vtotal, crtc_vblank_end;
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int vsyncshift = 0;
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int vsyncshift = 0;
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@ -6277,56 +6277,56 @@ static void intel_get_pipe_timings(struct intel_crtc *crtc,
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uint32_t tmp;
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uint32_t tmp;
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tmp = I915_READ(HTOTAL(cpu_transcoder));
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tmp = I915_READ(HTOTAL(cpu_transcoder));
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pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
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pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
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pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
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pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
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tmp = I915_READ(HBLANK(cpu_transcoder));
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tmp = I915_READ(HBLANK(cpu_transcoder));
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pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
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pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
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pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
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pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
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tmp = I915_READ(HSYNC(cpu_transcoder));
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tmp = I915_READ(HSYNC(cpu_transcoder));
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pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
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pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
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pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
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pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
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tmp = I915_READ(VTOTAL(cpu_transcoder));
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tmp = I915_READ(VTOTAL(cpu_transcoder));
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pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
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pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
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pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
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pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
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tmp = I915_READ(VBLANK(cpu_transcoder));
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tmp = I915_READ(VBLANK(cpu_transcoder));
|
||||||
pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
|
pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
|
||||||
pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
|
pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
|
||||||
tmp = I915_READ(VSYNC(cpu_transcoder));
|
tmp = I915_READ(VSYNC(cpu_transcoder));
|
||||||
pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
|
pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
|
||||||
pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
|
pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
|
||||||
|
|
||||||
if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
|
if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
|
||||||
pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
|
pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
|
||||||
pipe_config->adjusted_mode.crtc_vtotal += 1;
|
pipe_config->base.adjusted_mode.crtc_vtotal += 1;
|
||||||
pipe_config->adjusted_mode.crtc_vblank_end += 1;
|
pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
|
||||||
}
|
}
|
||||||
|
|
||||||
tmp = I915_READ(PIPESRC(crtc->pipe));
|
tmp = I915_READ(PIPESRC(crtc->pipe));
|
||||||
pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
|
pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
|
||||||
pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
|
pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
|
||||||
|
|
||||||
pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
|
pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
|
||||||
pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
|
pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
|
||||||
}
|
}
|
||||||
|
|
||||||
void intel_mode_from_pipe_config(struct drm_display_mode *mode,
|
void intel_mode_from_pipe_config(struct drm_display_mode *mode,
|
||||||
struct intel_crtc_state *pipe_config)
|
struct intel_crtc_state *pipe_config)
|
||||||
{
|
{
|
||||||
mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
|
mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
|
||||||
mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
|
mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
|
||||||
mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
|
mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
|
||||||
mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
|
mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
|
||||||
|
|
||||||
mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
|
mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
|
||||||
mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
|
mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
|
||||||
mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
|
mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
|
||||||
mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
|
mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
|
||||||
|
|
||||||
mode->flags = pipe_config->adjusted_mode.flags;
|
mode->flags = pipe_config->base.adjusted_mode.flags;
|
||||||
|
|
||||||
mode->clock = pipe_config->adjusted_mode.crtc_clock;
|
mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
|
||||||
mode->flags |= pipe_config->adjusted_mode.flags;
|
mode->flags |= pipe_config->base.adjusted_mode.flags;
|
||||||
}
|
}
|
||||||
|
|
||||||
static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
|
static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
|
||||||
|
@ -6376,7 +6376,7 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
|
if (intel_crtc->config.base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
|
||||||
if (INTEL_INFO(dev)->gen < 4 ||
|
if (INTEL_INFO(dev)->gen < 4 ||
|
||||||
intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
|
intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
|
||||||
pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
|
pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
|
||||||
|
@ -7133,7 +7133,7 @@ static void ironlake_set_pipeconf(struct drm_crtc *crtc)
|
||||||
if (intel_crtc->config.dither)
|
if (intel_crtc->config.dither)
|
||||||
val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
|
val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
|
||||||
|
|
||||||
if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
|
if (intel_crtc->config.base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
|
||||||
val |= PIPECONF_INTERLACED_ILK;
|
val |= PIPECONF_INTERLACED_ILK;
|
||||||
else
|
else
|
||||||
val |= PIPECONF_PROGRESSIVE;
|
val |= PIPECONF_PROGRESSIVE;
|
||||||
|
@ -7223,7 +7223,7 @@ static void haswell_set_pipeconf(struct drm_crtc *crtc)
|
||||||
if (IS_HASWELL(dev) && intel_crtc->config.dither)
|
if (IS_HASWELL(dev) && intel_crtc->config.dither)
|
||||||
val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
|
val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
|
||||||
|
|
||||||
if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
|
if (intel_crtc->config.base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
|
||||||
val |= PIPECONF_INTERLACED_ILK;
|
val |= PIPECONF_INTERLACED_ILK;
|
||||||
else
|
else
|
||||||
val |= PIPECONF_PROGRESSIVE;
|
val |= PIPECONF_PROGRESSIVE;
|
||||||
|
@ -8789,7 +8789,7 @@ static void ironlake_pch_clock_get(struct intel_crtc *crtc,
|
||||||
* agree once we know their relationship in the encoder's
|
* agree once we know their relationship in the encoder's
|
||||||
* get_config() function.
|
* get_config() function.
|
||||||
*/
|
*/
|
||||||
pipe_config->adjusted_mode.crtc_clock =
|
pipe_config->base.adjusted_mode.crtc_clock =
|
||||||
intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
|
intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
|
||||||
&pipe_config->fdi_m_n);
|
&pipe_config->fdi_m_n);
|
||||||
}
|
}
|
||||||
|
@ -9981,10 +9981,10 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc,
|
||||||
pipe_config->has_infoframe);
|
pipe_config->has_infoframe);
|
||||||
|
|
||||||
DRM_DEBUG_KMS("requested mode:\n");
|
DRM_DEBUG_KMS("requested mode:\n");
|
||||||
drm_mode_debug_printmodeline(&pipe_config->requested_mode);
|
drm_mode_debug_printmodeline(&pipe_config->base.mode);
|
||||||
DRM_DEBUG_KMS("adjusted mode:\n");
|
DRM_DEBUG_KMS("adjusted mode:\n");
|
||||||
drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
|
drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
|
||||||
intel_dump_crtc_timings(&pipe_config->adjusted_mode);
|
intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
|
||||||
DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
|
DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
|
||||||
DRM_DEBUG_KMS("pipe src size: %dx%d\n",
|
DRM_DEBUG_KMS("pipe src size: %dx%d\n",
|
||||||
pipe_config->pipe_src_w, pipe_config->pipe_src_h);
|
pipe_config->pipe_src_w, pipe_config->pipe_src_h);
|
||||||
|
@ -10108,8 +10108,8 @@ intel_modeset_pipe_config(struct drm_crtc *crtc,
|
||||||
if (!pipe_config)
|
if (!pipe_config)
|
||||||
return ERR_PTR(-ENOMEM);
|
return ERR_PTR(-ENOMEM);
|
||||||
|
|
||||||
drm_mode_copy(&pipe_config->adjusted_mode, mode);
|
drm_mode_copy(&pipe_config->base.adjusted_mode, mode);
|
||||||
drm_mode_copy(&pipe_config->requested_mode, mode);
|
drm_mode_copy(&pipe_config->base.mode, mode);
|
||||||
|
|
||||||
pipe_config->cpu_transcoder =
|
pipe_config->cpu_transcoder =
|
||||||
(enum transcoder) to_intel_crtc(crtc)->pipe;
|
(enum transcoder) to_intel_crtc(crtc)->pipe;
|
||||||
|
@ -10120,13 +10120,13 @@ intel_modeset_pipe_config(struct drm_crtc *crtc,
|
||||||
* positive or negative polarity is requested, treat this as meaning
|
* positive or negative polarity is requested, treat this as meaning
|
||||||
* negative polarity.
|
* negative polarity.
|
||||||
*/
|
*/
|
||||||
if (!(pipe_config->adjusted_mode.flags &
|
if (!(pipe_config->base.adjusted_mode.flags &
|
||||||
(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
|
(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
|
||||||
pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
|
pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
|
||||||
|
|
||||||
if (!(pipe_config->adjusted_mode.flags &
|
if (!(pipe_config->base.adjusted_mode.flags &
|
||||||
(DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
|
(DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
|
||||||
pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
|
pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
|
||||||
|
|
||||||
/* Compute a starting value for pipe_config->pipe_bpp taking the source
|
/* Compute a starting value for pipe_config->pipe_bpp taking the source
|
||||||
* plane pixel format and any sink constraints into account. Returns the
|
* plane pixel format and any sink constraints into account. Returns the
|
||||||
|
@ -10145,7 +10145,7 @@ intel_modeset_pipe_config(struct drm_crtc *crtc,
|
||||||
* computation to clearly distinguish it from the adjusted mode, which
|
* computation to clearly distinguish it from the adjusted mode, which
|
||||||
* can be changed by the connectors in the below retry loop.
|
* can be changed by the connectors in the below retry loop.
|
||||||
*/
|
*/
|
||||||
drm_crtc_get_hv_timing(&pipe_config->requested_mode,
|
drm_crtc_get_hv_timing(&pipe_config->base.mode,
|
||||||
&pipe_config->pipe_src_w,
|
&pipe_config->pipe_src_w,
|
||||||
&pipe_config->pipe_src_h);
|
&pipe_config->pipe_src_h);
|
||||||
|
|
||||||
|
@ -10155,7 +10155,8 @@ intel_modeset_pipe_config(struct drm_crtc *crtc,
|
||||||
pipe_config->pixel_multiplier = 1;
|
pipe_config->pixel_multiplier = 1;
|
||||||
|
|
||||||
/* Fill in default crtc timings, allow encoders to overwrite them. */
|
/* Fill in default crtc timings, allow encoders to overwrite them. */
|
||||||
drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
|
drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
|
||||||
|
CRTC_STEREO_DOUBLE);
|
||||||
|
|
||||||
/* Pass our mode to the connectors and the CRTC to give them a chance to
|
/* Pass our mode to the connectors and the CRTC to give them a chance to
|
||||||
* adjust it according to limitations or connector properties, and also
|
* adjust it according to limitations or connector properties, and also
|
||||||
|
@ -10175,7 +10176,7 @@ intel_modeset_pipe_config(struct drm_crtc *crtc,
|
||||||
/* Set default port clock if not overwritten by the encoder. Needs to be
|
/* Set default port clock if not overwritten by the encoder. Needs to be
|
||||||
* done afterwards in case the encoder adjusts the mode. */
|
* done afterwards in case the encoder adjusts the mode. */
|
||||||
if (!pipe_config->port_clock)
|
if (!pipe_config->port_clock)
|
||||||
pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
|
pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
|
||||||
* pipe_config->pixel_multiplier;
|
* pipe_config->pixel_multiplier;
|
||||||
|
|
||||||
ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
|
ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
|
||||||
|
@ -10476,19 +10477,19 @@ intel_pipe_config_compare(struct drm_device *dev,
|
||||||
PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
|
PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
|
||||||
}
|
}
|
||||||
|
|
||||||
PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
|
PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
|
||||||
PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
|
PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
|
||||||
PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
|
PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
|
||||||
PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
|
PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
|
||||||
PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
|
PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
|
||||||
PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
|
PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
|
||||||
|
|
||||||
PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
|
PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
|
||||||
PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
|
PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
|
||||||
PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
|
PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
|
||||||
PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
|
PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
|
||||||
PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
|
PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
|
||||||
PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
|
PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
|
||||||
|
|
||||||
PIPE_CONF_CHECK_I(pixel_multiplier);
|
PIPE_CONF_CHECK_I(pixel_multiplier);
|
||||||
PIPE_CONF_CHECK_I(has_hdmi_sink);
|
PIPE_CONF_CHECK_I(has_hdmi_sink);
|
||||||
|
@ -10499,17 +10500,17 @@ intel_pipe_config_compare(struct drm_device *dev,
|
||||||
|
|
||||||
PIPE_CONF_CHECK_I(has_audio);
|
PIPE_CONF_CHECK_I(has_audio);
|
||||||
|
|
||||||
PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
|
PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
|
||||||
DRM_MODE_FLAG_INTERLACE);
|
DRM_MODE_FLAG_INTERLACE);
|
||||||
|
|
||||||
if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
|
if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
|
||||||
PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
|
PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
|
||||||
DRM_MODE_FLAG_PHSYNC);
|
DRM_MODE_FLAG_PHSYNC);
|
||||||
PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
|
PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
|
||||||
DRM_MODE_FLAG_NHSYNC);
|
DRM_MODE_FLAG_NHSYNC);
|
||||||
PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
|
PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
|
||||||
DRM_MODE_FLAG_PVSYNC);
|
DRM_MODE_FLAG_PVSYNC);
|
||||||
PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
|
PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
|
||||||
DRM_MODE_FLAG_NVSYNC);
|
DRM_MODE_FLAG_NVSYNC);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -10559,7 +10560,7 @@ intel_pipe_config_compare(struct drm_device *dev,
|
||||||
if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
|
if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
|
||||||
PIPE_CONF_CHECK_I(pipe_bpp);
|
PIPE_CONF_CHECK_I(pipe_bpp);
|
||||||
|
|
||||||
PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
|
PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
|
||||||
PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
|
PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
|
||||||
|
|
||||||
#undef PIPE_CONF_CHECK_X
|
#undef PIPE_CONF_CHECK_X
|
||||||
|
@ -10835,9 +10836,9 @@ void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
|
||||||
* FDI already provided one idea for the dotclock.
|
* FDI already provided one idea for the dotclock.
|
||||||
* Yell if the encoder disagrees.
|
* Yell if the encoder disagrees.
|
||||||
*/
|
*/
|
||||||
WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
|
WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
|
||||||
"FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
|
"FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
|
||||||
pipe_config->adjusted_mode.crtc_clock, dotclock);
|
pipe_config->base.adjusted_mode.crtc_clock, dotclock);
|
||||||
}
|
}
|
||||||
|
|
||||||
static void update_scanline_offset(struct intel_crtc *crtc)
|
static void update_scanline_offset(struct intel_crtc *crtc)
|
||||||
|
@ -10863,7 +10864,7 @@ static void update_scanline_offset(struct intel_crtc *crtc)
|
||||||
* one to the value.
|
* one to the value.
|
||||||
*/
|
*/
|
||||||
if (IS_GEN2(dev)) {
|
if (IS_GEN2(dev)) {
|
||||||
const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
|
const struct drm_display_mode *mode = &crtc->config.base.adjusted_mode;
|
||||||
int vtotal;
|
int vtotal;
|
||||||
|
|
||||||
vtotal = mode->crtc_vtotal;
|
vtotal = mode->crtc_vtotal;
|
||||||
|
@ -10992,7 +10993,7 @@ static int __intel_set_mode(struct drm_crtc *crtc,
|
||||||
* timestamping. They are derived from true hwmode.
|
* timestamping. They are derived from true hwmode.
|
||||||
*/
|
*/
|
||||||
drm_calc_timestamping_constants(crtc,
|
drm_calc_timestamping_constants(crtc,
|
||||||
&pipe_config->adjusted_mode);
|
&pipe_config->base.adjusted_mode);
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Only after disabling all output pipelines that will be changed can we
|
/* Only after disabling all output pipelines that will be changed can we
|
||||||
|
|
|
@ -1155,7 +1155,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
|
||||||
{
|
{
|
||||||
struct drm_device *dev = encoder->base.dev;
|
struct drm_device *dev = encoder->base.dev;
|
||||||
struct drm_i915_private *dev_priv = dev->dev_private;
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
||||||
struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
|
struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
|
||||||
struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
|
struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
|
||||||
enum port port = dp_to_dig_port(intel_dp)->port;
|
enum port port = dp_to_dig_port(intel_dp)->port;
|
||||||
struct intel_crtc *intel_crtc = encoder->new_crtc;
|
struct intel_crtc *intel_crtc = encoder->new_crtc;
|
||||||
|
@ -1324,7 +1324,7 @@ static void intel_dp_prepare(struct intel_encoder *encoder)
|
||||||
struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
|
struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
|
||||||
enum port port = dp_to_dig_port(intel_dp)->port;
|
enum port port = dp_to_dig_port(intel_dp)->port;
|
||||||
struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
|
struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
|
||||||
struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
|
struct drm_display_mode *adjusted_mode = &crtc->config.base.adjusted_mode;
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* There are four kinds of DP registers:
|
* There are four kinds of DP registers:
|
||||||
|
@ -2050,7 +2050,7 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
|
||||||
flags |= DRM_MODE_FLAG_NVSYNC;
|
flags |= DRM_MODE_FLAG_NVSYNC;
|
||||||
}
|
}
|
||||||
|
|
||||||
pipe_config->adjusted_mode.flags |= flags;
|
pipe_config->base.adjusted_mode.flags |= flags;
|
||||||
|
|
||||||
if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
|
if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
|
||||||
tmp & DP_COLOR_RANGE_16_235)
|
tmp & DP_COLOR_RANGE_16_235)
|
||||||
|
@ -2073,7 +2073,7 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
|
||||||
if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
|
if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
|
||||||
ironlake_check_encoder_dotclock(pipe_config, dotclock);
|
ironlake_check_encoder_dotclock(pipe_config, dotclock);
|
||||||
|
|
||||||
pipe_config->adjusted_mode.crtc_clock = dotclock;
|
pipe_config->base.adjusted_mode.crtc_clock = dotclock;
|
||||||
|
|
||||||
if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
|
if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
|
||||||
pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
|
pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
|
||||||
|
|
|
@ -38,7 +38,7 @@ static bool intel_dp_mst_compute_config(struct intel_encoder *encoder,
|
||||||
struct drm_device *dev = encoder->base.dev;
|
struct drm_device *dev = encoder->base.dev;
|
||||||
int bpp;
|
int bpp;
|
||||||
int lane_count, slots;
|
int lane_count, slots;
|
||||||
struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
|
struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
|
||||||
struct intel_connector *found = NULL, *intel_connector;
|
struct intel_connector *found = NULL, *intel_connector;
|
||||||
int mst_pbn;
|
int mst_pbn;
|
||||||
|
|
||||||
|
@ -254,7 +254,7 @@ static void intel_dp_mst_enc_get_config(struct intel_encoder *encoder,
|
||||||
default:
|
default:
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
pipe_config->adjusted_mode.flags |= flags;
|
pipe_config->base.adjusted_mode.flags |= flags;
|
||||||
intel_dp_get_m_n(crtc, pipe_config);
|
intel_dp_get_m_n(crtc, pipe_config);
|
||||||
|
|
||||||
intel_ddi_clock_get(&intel_dig_port->base, pipe_config);
|
intel_ddi_clock_get(&intel_dig_port->base, pipe_config);
|
||||||
|
|
|
@ -264,6 +264,8 @@ struct intel_plane_config {
|
||||||
};
|
};
|
||||||
|
|
||||||
struct intel_crtc_state {
|
struct intel_crtc_state {
|
||||||
|
struct drm_crtc_state base;
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* quirks - bitfield with hw state readout quirks
|
* quirks - bitfield with hw state readout quirks
|
||||||
*
|
*
|
||||||
|
@ -276,16 +278,6 @@ struct intel_crtc_state {
|
||||||
#define PIPE_CONFIG_QUIRK_INHERITED_MODE (1<<1) /* mode inherited from firmware */
|
#define PIPE_CONFIG_QUIRK_INHERITED_MODE (1<<1) /* mode inherited from firmware */
|
||||||
unsigned long quirks;
|
unsigned long quirks;
|
||||||
|
|
||||||
/* User requested mode, only valid as a starting point to
|
|
||||||
* compute adjusted_mode, except in the case of (S)DVO where
|
|
||||||
* it's also for the output timings of the (S)DVO chip.
|
|
||||||
* adjusted_mode will then correspond to the S(DVO) chip's
|
|
||||||
* preferred input timings. */
|
|
||||||
struct drm_display_mode requested_mode;
|
|
||||||
/* Actual pipe timings ie. what we program into the pipe timing
|
|
||||||
* registers. adjusted_mode.crtc_clock is the pipe pixel clock. */
|
|
||||||
struct drm_display_mode adjusted_mode;
|
|
||||||
|
|
||||||
/* Pipe source size (ie. panel fitter input size)
|
/* Pipe source size (ie. panel fitter input size)
|
||||||
* All planes will be positioned inside this space,
|
* All planes will be positioned inside this space,
|
||||||
* and get clipped at the edges. */
|
* and get clipped at the edges. */
|
||||||
|
|
|
@ -84,8 +84,8 @@ static bool intel_dsi_compute_config(struct intel_encoder *encoder,
|
||||||
base);
|
base);
|
||||||
struct intel_connector *intel_connector = intel_dsi->attached_connector;
|
struct intel_connector *intel_connector = intel_dsi->attached_connector;
|
||||||
struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
|
struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
|
||||||
struct drm_display_mode *adjusted_mode = &config->adjusted_mode;
|
struct drm_display_mode *adjusted_mode = &config->base.adjusted_mode;
|
||||||
struct drm_display_mode *mode = &config->requested_mode;
|
struct drm_display_mode *mode = &config->base.mode;
|
||||||
|
|
||||||
DRM_DEBUG_KMS("\n");
|
DRM_DEBUG_KMS("\n");
|
||||||
|
|
||||||
|
@ -452,7 +452,7 @@ static void intel_dsi_get_config(struct intel_encoder *encoder,
|
||||||
if (!pclk)
|
if (!pclk)
|
||||||
return;
|
return;
|
||||||
|
|
||||||
pipe_config->adjusted_mode.crtc_clock = pclk;
|
pipe_config->base.adjusted_mode.crtc_clock = pclk;
|
||||||
pipe_config->port_clock = pclk;
|
pipe_config->port_clock = pclk;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -566,7 +566,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
|
||||||
struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
|
struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
|
||||||
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
|
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
|
||||||
struct drm_display_mode *adjusted_mode =
|
struct drm_display_mode *adjusted_mode =
|
||||||
&intel_crtc->config.adjusted_mode;
|
&intel_crtc->config.base.adjusted_mode;
|
||||||
enum port port;
|
enum port port;
|
||||||
unsigned int bpp = intel_crtc->config.pipe_bpp;
|
unsigned int bpp = intel_crtc->config.pipe_bpp;
|
||||||
u32 val, tmp;
|
u32 val, tmp;
|
||||||
|
|
|
@ -160,9 +160,9 @@ static void intel_dvo_get_config(struct intel_encoder *encoder,
|
||||||
else
|
else
|
||||||
flags |= DRM_MODE_FLAG_NVSYNC;
|
flags |= DRM_MODE_FLAG_NVSYNC;
|
||||||
|
|
||||||
pipe_config->adjusted_mode.flags |= flags;
|
pipe_config->base.adjusted_mode.flags |= flags;
|
||||||
|
|
||||||
pipe_config->adjusted_mode.crtc_clock = pipe_config->port_clock;
|
pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
|
||||||
}
|
}
|
||||||
|
|
||||||
static void intel_disable_dvo(struct intel_encoder *encoder)
|
static void intel_disable_dvo(struct intel_encoder *encoder)
|
||||||
|
@ -186,8 +186,8 @@ static void intel_enable_dvo(struct intel_encoder *encoder)
|
||||||
u32 temp = I915_READ(dvo_reg);
|
u32 temp = I915_READ(dvo_reg);
|
||||||
|
|
||||||
intel_dvo->dev.dev_ops->mode_set(&intel_dvo->dev,
|
intel_dvo->dev.dev_ops->mode_set(&intel_dvo->dev,
|
||||||
&crtc->config.requested_mode,
|
&crtc->config.base.mode,
|
||||||
&crtc->config.adjusted_mode);
|
&crtc->config.base.adjusted_mode);
|
||||||
|
|
||||||
I915_WRITE(dvo_reg, temp | DVO_ENABLE);
|
I915_WRITE(dvo_reg, temp | DVO_ENABLE);
|
||||||
I915_READ(dvo_reg);
|
I915_READ(dvo_reg);
|
||||||
|
@ -264,7 +264,7 @@ static bool intel_dvo_compute_config(struct intel_encoder *encoder,
|
||||||
struct intel_crtc_state *pipe_config)
|
struct intel_crtc_state *pipe_config)
|
||||||
{
|
{
|
||||||
struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
|
struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
|
||||||
struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
|
struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
|
||||||
|
|
||||||
/* If we have timings from the BIOS for the panel, put them in
|
/* If we have timings from the BIOS for the panel, put them in
|
||||||
* to the adjusted mode. The CRTC will be set up for this mode,
|
* to the adjusted mode. The CRTC will be set up for this mode,
|
||||||
|
@ -295,7 +295,7 @@ static void intel_dvo_pre_enable(struct intel_encoder *encoder)
|
||||||
struct drm_device *dev = encoder->base.dev;
|
struct drm_device *dev = encoder->base.dev;
|
||||||
struct drm_i915_private *dev_priv = dev->dev_private;
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
||||||
struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
|
struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
|
||||||
struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
|
struct drm_display_mode *adjusted_mode = &crtc->config.base.adjusted_mode;
|
||||||
struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
|
struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
|
||||||
int pipe = crtc->pipe;
|
int pipe = crtc->pipe;
|
||||||
u32 dvo_val;
|
u32 dvo_val;
|
||||||
|
|
|
@ -542,7 +542,7 @@ void intel_fbc_update(struct drm_device *dev)
|
||||||
intel_crtc = to_intel_crtc(crtc);
|
intel_crtc = to_intel_crtc(crtc);
|
||||||
fb = crtc->primary->fb;
|
fb = crtc->primary->fb;
|
||||||
obj = intel_fb_obj(fb);
|
obj = intel_fb_obj(fb);
|
||||||
adjusted_mode = &intel_crtc->config.adjusted_mode;
|
adjusted_mode = &intel_crtc->config.base.adjusted_mode;
|
||||||
|
|
||||||
if (i915.enable_fbc < 0) {
|
if (i915.enable_fbc < 0) {
|
||||||
if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
|
if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
|
||||||
|
|
|
@ -581,7 +581,7 @@ static bool intel_fbdev_init_bios(struct drm_device *dev,
|
||||||
* pipe. Note we need to use the selected fb's pitch and bpp
|
* pipe. Note we need to use the selected fb's pitch and bpp
|
||||||
* rather than the current pipe's, since they differ.
|
* rather than the current pipe's, since they differ.
|
||||||
*/
|
*/
|
||||||
cur_size = intel_crtc->config.adjusted_mode.crtc_hdisplay;
|
cur_size = intel_crtc->config.base.adjusted_mode.crtc_hdisplay;
|
||||||
cur_size = cur_size * fb->base.bits_per_pixel / 8;
|
cur_size = cur_size * fb->base.bits_per_pixel / 8;
|
||||||
if (fb->base.pitches[0] < cur_size) {
|
if (fb->base.pitches[0] < cur_size) {
|
||||||
DRM_DEBUG_KMS("fb not wide enough for plane %c (%d vs %d)\n",
|
DRM_DEBUG_KMS("fb not wide enough for plane %c (%d vs %d)\n",
|
||||||
|
@ -592,13 +592,13 @@ static bool intel_fbdev_init_bios(struct drm_device *dev,
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
|
||||||
cur_size = intel_crtc->config.adjusted_mode.crtc_vdisplay;
|
cur_size = intel_crtc->config.base.adjusted_mode.crtc_vdisplay;
|
||||||
cur_size = ALIGN(cur_size, plane_config->tiled ? (IS_GEN2(dev) ? 16 : 8) : 1);
|
cur_size = ALIGN(cur_size, plane_config->tiled ? (IS_GEN2(dev) ? 16 : 8) : 1);
|
||||||
cur_size *= fb->base.pitches[0];
|
cur_size *= fb->base.pitches[0];
|
||||||
DRM_DEBUG_KMS("pipe %c area: %dx%d, bpp: %d, size: %d\n",
|
DRM_DEBUG_KMS("pipe %c area: %dx%d, bpp: %d, size: %d\n",
|
||||||
pipe_name(intel_crtc->pipe),
|
pipe_name(intel_crtc->pipe),
|
||||||
intel_crtc->config.adjusted_mode.crtc_hdisplay,
|
intel_crtc->config.base.adjusted_mode.crtc_hdisplay,
|
||||||
intel_crtc->config.adjusted_mode.crtc_vdisplay,
|
intel_crtc->config.base.adjusted_mode.crtc_vdisplay,
|
||||||
fb->base.bits_per_pixel,
|
fb->base.bits_per_pixel,
|
||||||
cur_size);
|
cur_size);
|
||||||
|
|
||||||
|
|
|
@ -700,7 +700,7 @@ static void intel_hdmi_prepare(struct intel_encoder *encoder)
|
||||||
struct drm_i915_private *dev_priv = dev->dev_private;
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
||||||
struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
|
struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
|
||||||
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
|
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
|
||||||
struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
|
struct drm_display_mode *adjusted_mode = &crtc->config.base.adjusted_mode;
|
||||||
u32 hdmi_val;
|
u32 hdmi_val;
|
||||||
|
|
||||||
hdmi_val = SDVO_ENCODING_HDMI;
|
hdmi_val = SDVO_ENCODING_HDMI;
|
||||||
|
@ -792,7 +792,7 @@ static void intel_hdmi_get_config(struct intel_encoder *encoder,
|
||||||
tmp & HDMI_COLOR_RANGE_16_235)
|
tmp & HDMI_COLOR_RANGE_16_235)
|
||||||
pipe_config->limited_color_range = true;
|
pipe_config->limited_color_range = true;
|
||||||
|
|
||||||
pipe_config->adjusted_mode.flags |= flags;
|
pipe_config->base.adjusted_mode.flags |= flags;
|
||||||
|
|
||||||
if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
|
if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
|
||||||
dotclock = pipe_config->port_clock * 2 / 3;
|
dotclock = pipe_config->port_clock * 2 / 3;
|
||||||
|
@ -802,7 +802,7 @@ static void intel_hdmi_get_config(struct intel_encoder *encoder,
|
||||||
if (HAS_PCH_SPLIT(dev_priv->dev))
|
if (HAS_PCH_SPLIT(dev_priv->dev))
|
||||||
ironlake_check_encoder_dotclock(pipe_config, dotclock);
|
ironlake_check_encoder_dotclock(pipe_config, dotclock);
|
||||||
|
|
||||||
pipe_config->adjusted_mode.crtc_clock = dotclock;
|
pipe_config->base.adjusted_mode.crtc_clock = dotclock;
|
||||||
}
|
}
|
||||||
|
|
||||||
static void intel_enable_hdmi(struct intel_encoder *encoder)
|
static void intel_enable_hdmi(struct intel_encoder *encoder)
|
||||||
|
@ -979,8 +979,8 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder,
|
||||||
{
|
{
|
||||||
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
|
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
|
||||||
struct drm_device *dev = encoder->base.dev;
|
struct drm_device *dev = encoder->base.dev;
|
||||||
struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
|
struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
|
||||||
int clock_12bpc = pipe_config->adjusted_mode.crtc_clock * 3 / 2;
|
int clock_12bpc = pipe_config->base.adjusted_mode.crtc_clock * 3 / 2;
|
||||||
int portclock_limit = hdmi_portclock_limit(intel_hdmi, false);
|
int portclock_limit = hdmi_portclock_limit(intel_hdmi, false);
|
||||||
int desired_bpp;
|
int desired_bpp;
|
||||||
|
|
||||||
|
@ -1252,7 +1252,7 @@ static void intel_hdmi_pre_enable(struct intel_encoder *encoder)
|
||||||
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
|
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
|
||||||
struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
|
struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
|
||||||
struct drm_display_mode *adjusted_mode =
|
struct drm_display_mode *adjusted_mode =
|
||||||
&intel_crtc->config.adjusted_mode;
|
&intel_crtc->config.base.adjusted_mode;
|
||||||
|
|
||||||
intel_hdmi_prepare(encoder);
|
intel_hdmi_prepare(encoder);
|
||||||
|
|
||||||
|
@ -1270,7 +1270,7 @@ static void vlv_hdmi_pre_enable(struct intel_encoder *encoder)
|
||||||
struct intel_crtc *intel_crtc =
|
struct intel_crtc *intel_crtc =
|
||||||
to_intel_crtc(encoder->base.crtc);
|
to_intel_crtc(encoder->base.crtc);
|
||||||
struct drm_display_mode *adjusted_mode =
|
struct drm_display_mode *adjusted_mode =
|
||||||
&intel_crtc->config.adjusted_mode;
|
&intel_crtc->config.base.adjusted_mode;
|
||||||
enum dpio_channel port = vlv_dport_to_channel(dport);
|
enum dpio_channel port = vlv_dport_to_channel(dport);
|
||||||
int pipe = intel_crtc->pipe;
|
int pipe = intel_crtc->pipe;
|
||||||
u32 val;
|
u32 val;
|
||||||
|
@ -1467,7 +1467,7 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
|
||||||
struct intel_crtc *intel_crtc =
|
struct intel_crtc *intel_crtc =
|
||||||
to_intel_crtc(encoder->base.crtc);
|
to_intel_crtc(encoder->base.crtc);
|
||||||
struct drm_display_mode *adjusted_mode =
|
struct drm_display_mode *adjusted_mode =
|
||||||
&intel_crtc->config.adjusted_mode;
|
&intel_crtc->config.base.adjusted_mode;
|
||||||
enum dpio_channel ch = vlv_dport_to_channel(dport);
|
enum dpio_channel ch = vlv_dport_to_channel(dport);
|
||||||
int pipe = intel_crtc->pipe;
|
int pipe = intel_crtc->pipe;
|
||||||
int data, i;
|
int data, i;
|
||||||
|
|
|
@ -115,7 +115,7 @@ static void intel_lvds_get_config(struct intel_encoder *encoder,
|
||||||
else
|
else
|
||||||
flags |= DRM_MODE_FLAG_PVSYNC;
|
flags |= DRM_MODE_FLAG_PVSYNC;
|
||||||
|
|
||||||
pipe_config->adjusted_mode.flags |= flags;
|
pipe_config->base.adjusted_mode.flags |= flags;
|
||||||
|
|
||||||
/* gen2/3 store dither state in pfit control, needs to match */
|
/* gen2/3 store dither state in pfit control, needs to match */
|
||||||
if (INTEL_INFO(dev)->gen < 4) {
|
if (INTEL_INFO(dev)->gen < 4) {
|
||||||
|
@ -129,7 +129,7 @@ static void intel_lvds_get_config(struct intel_encoder *encoder,
|
||||||
if (HAS_PCH_SPLIT(dev_priv->dev))
|
if (HAS_PCH_SPLIT(dev_priv->dev))
|
||||||
ironlake_check_encoder_dotclock(pipe_config, dotclock);
|
ironlake_check_encoder_dotclock(pipe_config, dotclock);
|
||||||
|
|
||||||
pipe_config->adjusted_mode.crtc_clock = dotclock;
|
pipe_config->base.adjusted_mode.crtc_clock = dotclock;
|
||||||
}
|
}
|
||||||
|
|
||||||
static void intel_pre_enable_lvds(struct intel_encoder *encoder)
|
static void intel_pre_enable_lvds(struct intel_encoder *encoder)
|
||||||
|
@ -139,7 +139,7 @@ static void intel_pre_enable_lvds(struct intel_encoder *encoder)
|
||||||
struct drm_i915_private *dev_priv = dev->dev_private;
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
||||||
struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
|
struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
|
||||||
const struct drm_display_mode *adjusted_mode =
|
const struct drm_display_mode *adjusted_mode =
|
||||||
&crtc->config.adjusted_mode;
|
&crtc->config.base.adjusted_mode;
|
||||||
int pipe = crtc->pipe;
|
int pipe = crtc->pipe;
|
||||||
u32 temp;
|
u32 temp;
|
||||||
|
|
||||||
|
@ -284,7 +284,7 @@ static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder,
|
||||||
to_lvds_encoder(&intel_encoder->base);
|
to_lvds_encoder(&intel_encoder->base);
|
||||||
struct intel_connector *intel_connector =
|
struct intel_connector *intel_connector =
|
||||||
&lvds_encoder->attached_connector->base;
|
&lvds_encoder->attached_connector->base;
|
||||||
struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
|
struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
|
||||||
struct intel_crtc *intel_crtc = lvds_encoder->base.new_crtc;
|
struct intel_crtc *intel_crtc = lvds_encoder->base.new_crtc;
|
||||||
unsigned int lvds_bpp;
|
unsigned int lvds_bpp;
|
||||||
|
|
||||||
|
|
|
@ -104,7 +104,7 @@ intel_pch_panel_fitting(struct intel_crtc *intel_crtc,
|
||||||
struct drm_display_mode *adjusted_mode;
|
struct drm_display_mode *adjusted_mode;
|
||||||
int x, y, width, height;
|
int x, y, width, height;
|
||||||
|
|
||||||
adjusted_mode = &pipe_config->adjusted_mode;
|
adjusted_mode = &pipe_config->base.adjusted_mode;
|
||||||
|
|
||||||
x = y = width = height = 0;
|
x = y = width = height = 0;
|
||||||
|
|
||||||
|
@ -226,7 +226,7 @@ static inline u32 panel_fitter_scaling(u32 source, u32 target)
|
||||||
static void i965_scale_aspect(struct intel_crtc_state *pipe_config,
|
static void i965_scale_aspect(struct intel_crtc_state *pipe_config,
|
||||||
u32 *pfit_control)
|
u32 *pfit_control)
|
||||||
{
|
{
|
||||||
struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
|
struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
|
||||||
u32 scaled_width = adjusted_mode->hdisplay *
|
u32 scaled_width = adjusted_mode->hdisplay *
|
||||||
pipe_config->pipe_src_h;
|
pipe_config->pipe_src_h;
|
||||||
u32 scaled_height = pipe_config->pipe_src_w *
|
u32 scaled_height = pipe_config->pipe_src_w *
|
||||||
|
@ -247,7 +247,7 @@ static void i9xx_scale_aspect(struct intel_crtc_state *pipe_config,
|
||||||
u32 *pfit_control, u32 *pfit_pgm_ratios,
|
u32 *pfit_control, u32 *pfit_pgm_ratios,
|
||||||
u32 *border)
|
u32 *border)
|
||||||
{
|
{
|
||||||
struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
|
struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
|
||||||
u32 scaled_width = adjusted_mode->hdisplay *
|
u32 scaled_width = adjusted_mode->hdisplay *
|
||||||
pipe_config->pipe_src_h;
|
pipe_config->pipe_src_h;
|
||||||
u32 scaled_height = pipe_config->pipe_src_w *
|
u32 scaled_height = pipe_config->pipe_src_w *
|
||||||
|
@ -308,7 +308,7 @@ void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc,
|
||||||
u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0;
|
u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0;
|
||||||
struct drm_display_mode *adjusted_mode;
|
struct drm_display_mode *adjusted_mode;
|
||||||
|
|
||||||
adjusted_mode = &pipe_config->adjusted_mode;
|
adjusted_mode = &pipe_config->base.adjusted_mode;
|
||||||
|
|
||||||
/* Native modes don't need fitting */
|
/* Native modes don't need fitting */
|
||||||
if (adjusted_mode->hdisplay == pipe_config->pipe_src_w &&
|
if (adjusted_mode->hdisplay == pipe_config->pipe_src_w &&
|
||||||
|
|
|
@ -539,7 +539,7 @@ static void pineview_update_wm(struct drm_crtc *unused_crtc)
|
||||||
int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
|
int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
|
||||||
int clock;
|
int clock;
|
||||||
|
|
||||||
adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
|
adjusted_mode = &to_intel_crtc(crtc)->config.base.adjusted_mode;
|
||||||
clock = adjusted_mode->crtc_clock;
|
clock = adjusted_mode->crtc_clock;
|
||||||
|
|
||||||
/* Display SR */
|
/* Display SR */
|
||||||
|
@ -608,7 +608,7 @@ static bool g4x_compute_wm0(struct drm_device *dev,
|
||||||
return false;
|
return false;
|
||||||
}
|
}
|
||||||
|
|
||||||
adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
|
adjusted_mode = &to_intel_crtc(crtc)->config.base.adjusted_mode;
|
||||||
clock = adjusted_mode->crtc_clock;
|
clock = adjusted_mode->crtc_clock;
|
||||||
htotal = adjusted_mode->crtc_htotal;
|
htotal = adjusted_mode->crtc_htotal;
|
||||||
hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
|
hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
|
||||||
|
@ -695,7 +695,7 @@ static bool g4x_compute_srwm(struct drm_device *dev,
|
||||||
}
|
}
|
||||||
|
|
||||||
crtc = intel_get_crtc_for_plane(dev, plane);
|
crtc = intel_get_crtc_for_plane(dev, plane);
|
||||||
adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
|
adjusted_mode = &to_intel_crtc(crtc)->config.base.adjusted_mode;
|
||||||
clock = adjusted_mode->crtc_clock;
|
clock = adjusted_mode->crtc_clock;
|
||||||
htotal = adjusted_mode->crtc_htotal;
|
htotal = adjusted_mode->crtc_htotal;
|
||||||
hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
|
hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
|
||||||
|
@ -729,7 +729,7 @@ static bool vlv_compute_drain_latency(struct drm_crtc *crtc,
|
||||||
{
|
{
|
||||||
struct drm_device *dev = crtc->dev;
|
struct drm_device *dev = crtc->dev;
|
||||||
int entries;
|
int entries;
|
||||||
int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
|
int clock = to_intel_crtc(crtc)->config.base.adjusted_mode.crtc_clock;
|
||||||
|
|
||||||
if (WARN(clock == 0, "Pixel clock is zero!\n"))
|
if (WARN(clock == 0, "Pixel clock is zero!\n"))
|
||||||
return false;
|
return false;
|
||||||
|
@ -1059,7 +1059,7 @@ static void i965_update_wm(struct drm_crtc *unused_crtc)
|
||||||
/* self-refresh has much higher latency */
|
/* self-refresh has much higher latency */
|
||||||
static const int sr_latency_ns = 12000;
|
static const int sr_latency_ns = 12000;
|
||||||
const struct drm_display_mode *adjusted_mode =
|
const struct drm_display_mode *adjusted_mode =
|
||||||
&to_intel_crtc(crtc)->config.adjusted_mode;
|
&to_intel_crtc(crtc)->config.base.adjusted_mode;
|
||||||
int clock = adjusted_mode->crtc_clock;
|
int clock = adjusted_mode->crtc_clock;
|
||||||
int htotal = adjusted_mode->crtc_htotal;
|
int htotal = adjusted_mode->crtc_htotal;
|
||||||
int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
|
int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
|
||||||
|
@ -1144,7 +1144,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
|
||||||
if (IS_GEN2(dev))
|
if (IS_GEN2(dev))
|
||||||
cpp = 4;
|
cpp = 4;
|
||||||
|
|
||||||
adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
|
adjusted_mode = &to_intel_crtc(crtc)->config.base.adjusted_mode;
|
||||||
planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
|
planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
|
||||||
wm_info, fifo_size, cpp,
|
wm_info, fifo_size, cpp,
|
||||||
pessimal_latency_ns);
|
pessimal_latency_ns);
|
||||||
|
@ -1166,7 +1166,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
|
||||||
if (IS_GEN2(dev))
|
if (IS_GEN2(dev))
|
||||||
cpp = 4;
|
cpp = 4;
|
||||||
|
|
||||||
adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
|
adjusted_mode = &to_intel_crtc(crtc)->config.base.adjusted_mode;
|
||||||
planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
|
planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
|
||||||
wm_info, fifo_size, cpp,
|
wm_info, fifo_size, cpp,
|
||||||
pessimal_latency_ns);
|
pessimal_latency_ns);
|
||||||
|
@ -1205,7 +1205,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
|
||||||
/* self-refresh has much higher latency */
|
/* self-refresh has much higher latency */
|
||||||
static const int sr_latency_ns = 6000;
|
static const int sr_latency_ns = 6000;
|
||||||
const struct drm_display_mode *adjusted_mode =
|
const struct drm_display_mode *adjusted_mode =
|
||||||
&to_intel_crtc(enabled)->config.adjusted_mode;
|
&to_intel_crtc(enabled)->config.base.adjusted_mode;
|
||||||
int clock = adjusted_mode->crtc_clock;
|
int clock = adjusted_mode->crtc_clock;
|
||||||
int htotal = adjusted_mode->crtc_htotal;
|
int htotal = adjusted_mode->crtc_htotal;
|
||||||
int hdisplay = to_intel_crtc(enabled)->config.pipe_src_w;
|
int hdisplay = to_intel_crtc(enabled)->config.pipe_src_w;
|
||||||
|
@ -1261,7 +1261,7 @@ static void i845_update_wm(struct drm_crtc *unused_crtc)
|
||||||
if (crtc == NULL)
|
if (crtc == NULL)
|
||||||
return;
|
return;
|
||||||
|
|
||||||
adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
|
adjusted_mode = &to_intel_crtc(crtc)->config.base.adjusted_mode;
|
||||||
planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
|
planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
|
||||||
&i845_wm_info,
|
&i845_wm_info,
|
||||||
dev_priv->display.get_fifo_size(dev, 0),
|
dev_priv->display.get_fifo_size(dev, 0),
|
||||||
|
@ -1280,7 +1280,7 @@ static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
|
||||||
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
|
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
|
||||||
uint32_t pixel_rate;
|
uint32_t pixel_rate;
|
||||||
|
|
||||||
pixel_rate = intel_crtc->config.adjusted_mode.crtc_clock;
|
pixel_rate = intel_crtc->config.base.adjusted_mode.crtc_clock;
|
||||||
|
|
||||||
/* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
|
/* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
|
||||||
* adjust the pixel_rate here. */
|
* adjust the pixel_rate here. */
|
||||||
|
@ -1643,7 +1643,7 @@ hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
|
||||||
{
|
{
|
||||||
struct drm_i915_private *dev_priv = dev->dev_private;
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
||||||
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
|
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
|
||||||
struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
|
struct drm_display_mode *mode = &intel_crtc->config.base.adjusted_mode;
|
||||||
u32 linetime, ips_linetime;
|
u32 linetime, ips_linetime;
|
||||||
|
|
||||||
if (!intel_crtc_active(crtc))
|
if (!intel_crtc_active(crtc))
|
||||||
|
@ -1903,7 +1903,7 @@ static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
|
||||||
return;
|
return;
|
||||||
|
|
||||||
p->active = true;
|
p->active = true;
|
||||||
p->pipe_htotal = intel_crtc->config.adjusted_mode.crtc_htotal;
|
p->pipe_htotal = intel_crtc->config.base.adjusted_mode.crtc_htotal;
|
||||||
p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
|
p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
|
||||||
p->pri.bytes_per_pixel = crtc->primary->fb->bits_per_pixel / 8;
|
p->pri.bytes_per_pixel = crtc->primary->fb->bits_per_pixel / 8;
|
||||||
p->cur.bytes_per_pixel = 4;
|
p->cur.bytes_per_pixel = 4;
|
||||||
|
@ -2559,7 +2559,7 @@ skl_allocate_pipe_ddb(struct drm_crtc *crtc,
|
||||||
static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
|
static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
|
||||||
{
|
{
|
||||||
/* TODO: Take into account the scalers once we support them */
|
/* TODO: Take into account the scalers once we support them */
|
||||||
return config->adjusted_mode.crtc_clock;
|
return config->base.adjusted_mode.crtc_clock;
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
@ -2647,7 +2647,7 @@ static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc,
|
||||||
|
|
||||||
p->active = intel_crtc_active(crtc);
|
p->active = intel_crtc_active(crtc);
|
||||||
if (p->active) {
|
if (p->active) {
|
||||||
p->pipe_htotal = intel_crtc->config.adjusted_mode.crtc_htotal;
|
p->pipe_htotal = intel_crtc->config.base.adjusted_mode.crtc_htotal;
|
||||||
p->pixel_rate = skl_pipe_pixel_rate(&intel_crtc->config);
|
p->pixel_rate = skl_pipe_pixel_rate(&intel_crtc->config);
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
|
|
@ -270,7 +270,7 @@ static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
|
||||||
}
|
}
|
||||||
|
|
||||||
if (IS_HASWELL(dev) &&
|
if (IS_HASWELL(dev) &&
|
||||||
intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
|
intel_crtc->config.base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
|
||||||
DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
|
DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
|
||||||
return false;
|
return false;
|
||||||
}
|
}
|
||||||
|
|
|
@ -1115,8 +1115,8 @@ static bool intel_sdvo_compute_config(struct intel_encoder *encoder,
|
||||||
struct intel_crtc_state *pipe_config)
|
struct intel_crtc_state *pipe_config)
|
||||||
{
|
{
|
||||||
struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
|
struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
|
||||||
struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
|
struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
|
||||||
struct drm_display_mode *mode = &pipe_config->requested_mode;
|
struct drm_display_mode *mode = &pipe_config->base.mode;
|
||||||
|
|
||||||
DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n");
|
DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n");
|
||||||
pipe_config->pipe_bpp = 8*3;
|
pipe_config->pipe_bpp = 8*3;
|
||||||
|
@ -1181,8 +1181,8 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder)
|
||||||
struct drm_i915_private *dev_priv = dev->dev_private;
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
||||||
struct intel_crtc *crtc = to_intel_crtc(intel_encoder->base.crtc);
|
struct intel_crtc *crtc = to_intel_crtc(intel_encoder->base.crtc);
|
||||||
struct drm_display_mode *adjusted_mode =
|
struct drm_display_mode *adjusted_mode =
|
||||||
&crtc->config.adjusted_mode;
|
&crtc->config.base.adjusted_mode;
|
||||||
struct drm_display_mode *mode = &crtc->config.requested_mode;
|
struct drm_display_mode *mode = &crtc->config.base.mode;
|
||||||
struct intel_sdvo *intel_sdvo = to_sdvo(intel_encoder);
|
struct intel_sdvo *intel_sdvo = to_sdvo(intel_encoder);
|
||||||
u32 sdvox;
|
u32 sdvox;
|
||||||
struct intel_sdvo_in_out_map in_out;
|
struct intel_sdvo_in_out_map in_out;
|
||||||
|
@ -1370,7 +1370,7 @@ static void intel_sdvo_get_config(struct intel_encoder *encoder,
|
||||||
flags |= DRM_MODE_FLAG_NVSYNC;
|
flags |= DRM_MODE_FLAG_NVSYNC;
|
||||||
}
|
}
|
||||||
|
|
||||||
pipe_config->adjusted_mode.flags |= flags;
|
pipe_config->base.adjusted_mode.flags |= flags;
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* pixel multiplier readout is tricky: Only on i915g/gm it is stored in
|
* pixel multiplier readout is tricky: Only on i915g/gm it is stored in
|
||||||
|
@ -1392,7 +1392,7 @@ static void intel_sdvo_get_config(struct intel_encoder *encoder,
|
||||||
if (HAS_PCH_SPLIT(dev))
|
if (HAS_PCH_SPLIT(dev))
|
||||||
ironlake_check_encoder_dotclock(pipe_config, dotclock);
|
ironlake_check_encoder_dotclock(pipe_config, dotclock);
|
||||||
|
|
||||||
pipe_config->adjusted_mode.crtc_clock = dotclock;
|
pipe_config->base.adjusted_mode.crtc_clock = dotclock;
|
||||||
|
|
||||||
/* Cross check the port pixel multiplier with the sdvo encoder state. */
|
/* Cross check the port pixel multiplier with the sdvo encoder state. */
|
||||||
if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT,
|
if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT,
|
||||||
|
|
|
@ -80,7 +80,7 @@ static int usecs_to_scanlines(const struct drm_display_mode *mode, int usecs)
|
||||||
bool intel_pipe_update_start(struct intel_crtc *crtc, uint32_t *start_vbl_count)
|
bool intel_pipe_update_start(struct intel_crtc *crtc, uint32_t *start_vbl_count)
|
||||||
{
|
{
|
||||||
struct drm_device *dev = crtc->base.dev;
|
struct drm_device *dev = crtc->base.dev;
|
||||||
const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
|
const struct drm_display_mode *mode = &crtc->config.base.adjusted_mode;
|
||||||
enum pipe pipe = crtc->pipe;
|
enum pipe pipe = crtc->pipe;
|
||||||
long timeout = msecs_to_jiffies_timeout(1);
|
long timeout = msecs_to_jiffies_timeout(1);
|
||||||
int scanline, min, max, vblank_start;
|
int scanline, min, max, vblank_start;
|
||||||
|
|
|
@ -910,7 +910,7 @@ static void
|
||||||
intel_tv_get_config(struct intel_encoder *encoder,
|
intel_tv_get_config(struct intel_encoder *encoder,
|
||||||
struct intel_crtc_state *pipe_config)
|
struct intel_crtc_state *pipe_config)
|
||||||
{
|
{
|
||||||
pipe_config->adjusted_mode.crtc_clock = pipe_config->port_clock;
|
pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
|
||||||
}
|
}
|
||||||
|
|
||||||
static bool
|
static bool
|
||||||
|
@ -923,12 +923,12 @@ intel_tv_compute_config(struct intel_encoder *encoder,
|
||||||
if (!tv_mode)
|
if (!tv_mode)
|
||||||
return false;
|
return false;
|
||||||
|
|
||||||
pipe_config->adjusted_mode.crtc_clock = tv_mode->clock;
|
pipe_config->base.adjusted_mode.crtc_clock = tv_mode->clock;
|
||||||
DRM_DEBUG_KMS("forcing bpc to 8 for TV\n");
|
DRM_DEBUG_KMS("forcing bpc to 8 for TV\n");
|
||||||
pipe_config->pipe_bpp = 8*3;
|
pipe_config->pipe_bpp = 8*3;
|
||||||
|
|
||||||
/* TV has it's own notion of sync and other mode flags, so clear them. */
|
/* TV has it's own notion of sync and other mode flags, so clear them. */
|
||||||
pipe_config->adjusted_mode.flags = 0;
|
pipe_config->base.adjusted_mode.flags = 0;
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* FIXME: We don't check whether the input mode is actually what we want
|
* FIXME: We don't check whether the input mode is actually what we want
|
||||||
|
|
Loading…
Reference in a new issue