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drm/i915: Do not use {HAS_*, IS_*, INTEL_INFO}(dev_priv->dev)
dev_priv is what the macro works hard to extract, pass it directly. > sed 's/\([A-Z].*(dev_priv\)->dev)/\1)/g' v2: - Include all wrapper macros too (Chris) v3: - Include sed cmdline (Chris) v4: - Break long line - Rebase Cc: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1460016485-8089-1-git-send-email-joonas.lahtinen@linux.intel.com
This commit is contained in:
parent
9458f4ba7d
commit
2d1fe07340
15 changed files with 56 additions and 55 deletions
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@ -2415,7 +2415,7 @@ static int i915_guc_load_status_info(struct seq_file *m, void *data)
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struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
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u32 tmp, i;
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if (!HAS_GUC_UCODE(dev_priv->dev))
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if (!HAS_GUC_UCODE(dev_priv))
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return 0;
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seq_printf(m, "GuC firmware status:\n");
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@ -2489,7 +2489,7 @@ static int i915_guc_info(struct seq_file *m, void *data)
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struct intel_engine_cs *engine;
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u64 total = 0;
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if (!HAS_GUC_SCHED(dev_priv->dev))
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if (!HAS_GUC_SCHED(dev_priv))
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return 0;
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if (mutex_lock_interruptible(&dev->struct_mutex))
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@ -1400,7 +1400,7 @@ static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
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if (err)
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goto err2;
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if (!IS_CHERRYVIEW(dev_priv->dev))
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if (!IS_CHERRYVIEW(dev_priv))
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vlv_save_gunit_s0ix_state(dev_priv);
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err = vlv_force_gfx_clock(dev_priv, false);
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@ -1432,7 +1432,7 @@ static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
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*/
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ret = vlv_force_gfx_clock(dev_priv, true);
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if (!IS_CHERRYVIEW(dev_priv->dev))
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if (!IS_CHERRYVIEW(dev_priv))
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vlv_restore_gunit_s0ix_state(dev_priv);
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err = vlv_allow_gt_wake(dev_priv, true);
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@ -2306,7 +2306,7 @@ void i915_check_and_clear_faults(struct drm_device *dev)
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static void i915_ggtt_flush(struct drm_i915_private *dev_priv)
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{
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if (INTEL_INFO(dev_priv->dev)->gen < 6) {
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if (INTEL_INFO(dev_priv)->gen < 6) {
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intel_gtt_chipset_flush();
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} else {
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I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
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@ -2977,7 +2977,7 @@ static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv)
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GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) |
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GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
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if (!USES_PPGTT(dev_priv->dev))
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if (!USES_PPGTT(dev_priv))
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/* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,
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* so RTL will always use the value corresponding to
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* pat_sel = 000".
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@ -669,7 +669,8 @@ i915_error_object_create(struct drm_i915_private *dev_priv,
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}
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/* Cannot access snooped pages through the aperture */
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if (use_ggtt && src->cache_level != I915_CACHE_NONE && !HAS_LLC(dev_priv->dev))
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if (use_ggtt && src->cache_level != I915_CACHE_NONE &&
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!HAS_LLC(dev_priv))
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goto unwind;
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dst->page_count = num_pages;
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@ -884,7 +885,7 @@ static void gen6_record_semaphore_state(struct drm_i915_private *dev_priv,
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ering->semaphore_seqno[0] = engine->semaphore.sync_seqno[0];
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ering->semaphore_seqno[1] = engine->semaphore.sync_seqno[1];
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if (HAS_VEBOX(dev_priv->dev)) {
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if (HAS_VEBOX(dev_priv)) {
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ering->semaphore_mboxes[2] =
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I915_READ(RING_SYNC_2(engine->mmio_base));
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ering->semaphore_seqno[2] = engine->semaphore.sync_seqno[2];
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@ -1051,7 +1052,7 @@ static void i915_gem_record_rings(struct drm_device *dev,
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request->batch_obj,
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vm);
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if (HAS_BROKEN_CS_TLB(dev_priv->dev))
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if (HAS_BROKEN_CS_TLB(dev_priv))
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error->ring[i].wa_batchbuffer =
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i915_error_ggtt_object_create(dev_priv,
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engine->scratch.obj);
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@ -1218,7 +1218,7 @@ static void ivybridge_parity_work(struct work_struct *work)
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i915_reg_t reg;
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slice--;
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if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev)))
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if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv)))
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break;
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dev_priv->l3_parity.which_slice &= ~(1<<slice);
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@ -1257,7 +1257,7 @@ static void ivybridge_parity_work(struct work_struct *work)
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out:
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WARN_ON(dev_priv->l3_parity.which_slice);
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spin_lock_irq(&dev_priv->irq_lock);
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gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev));
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gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv));
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spin_unlock_irq(&dev_priv->irq_lock);
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mutex_unlock(&dev_priv->dev->struct_mutex);
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@ -1626,7 +1626,7 @@ static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
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if (INTEL_INFO(dev_priv)->gen >= 8)
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return;
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if (HAS_VEBOX(dev_priv->dev)) {
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if (HAS_VEBOX(dev_priv)) {
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if (pm_iir & PM_VEBOX_USER_INTERRUPT)
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notify_ring(&dev_priv->engine[VECS]);
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@ -2828,7 +2828,7 @@ semaphore_wait_to_signaller_ring(struct intel_engine_cs *engine, u32 ipehr,
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struct drm_i915_private *dev_priv = engine->dev->dev_private;
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struct intel_engine_cs *signaller;
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if (INTEL_INFO(dev_priv->dev)->gen >= 8) {
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if (INTEL_INFO(dev_priv)->gen >= 8) {
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for_each_engine(signaller, dev_priv) {
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if (engine == signaller)
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continue;
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@ -373,7 +373,7 @@ static void ilk_audio_codec_disable(struct intel_encoder *encoder)
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if (WARN_ON(port == PORT_A))
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return;
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if (HAS_PCH_IBX(dev_priv->dev)) {
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if (HAS_PCH_IBX(dev_priv)) {
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aud_config = IBX_AUD_CFG(pipe);
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aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
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} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
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@ -1167,7 +1167,7 @@ static void assert_fdi_tx(struct drm_i915_private *dev_priv,
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enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
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pipe);
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if (HAS_DDI(dev_priv->dev)) {
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if (HAS_DDI(dev_priv)) {
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/* DDI does not have a specific FDI_TX register */
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u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
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cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
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@ -1203,11 +1203,11 @@ static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
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u32 val;
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/* ILK FDI PLL is always enabled */
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if (INTEL_INFO(dev_priv->dev)->gen == 5)
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if (INTEL_INFO(dev_priv)->gen == 5)
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return;
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/* On Haswell, DDI ports are responsible for the FDI PLL setup */
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if (HAS_DDI(dev_priv->dev))
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if (HAS_DDI(dev_priv))
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return;
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val = I915_READ(FDI_TX_CTL(pipe));
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@ -1415,11 +1415,11 @@ static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
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if ((val & DP_PORT_EN) == 0)
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return false;
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if (HAS_PCH_CPT(dev_priv->dev)) {
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if (HAS_PCH_CPT(dev_priv)) {
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u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
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if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
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return false;
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} else if (IS_CHERRYVIEW(dev_priv->dev)) {
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} else if (IS_CHERRYVIEW(dev_priv)) {
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if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
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return false;
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} else {
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@ -1435,10 +1435,10 @@ static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
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if ((val & SDVO_ENABLE) == 0)
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return false;
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if (HAS_PCH_CPT(dev_priv->dev)) {
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if (HAS_PCH_CPT(dev_priv)) {
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if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
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return false;
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} else if (IS_CHERRYVIEW(dev_priv->dev)) {
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} else if (IS_CHERRYVIEW(dev_priv)) {
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if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
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return false;
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} else {
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@ -1454,7 +1454,7 @@ static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
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if ((val & LVDS_PORT_EN) == 0)
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return false;
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if (HAS_PCH_CPT(dev_priv->dev)) {
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if (HAS_PCH_CPT(dev_priv)) {
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if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
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return false;
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} else {
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@ -1469,7 +1469,7 @@ static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
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{
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if ((val & ADPA_DAC_ENABLE) == 0)
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return false;
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if (HAS_PCH_CPT(dev_priv->dev)) {
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if (HAS_PCH_CPT(dev_priv)) {
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if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
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return false;
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} else {
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@ -1488,7 +1488,7 @@ static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
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"PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
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i915_mmio_reg_offset(reg), pipe_name(pipe));
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I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
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I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
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&& (val & DP_PIPEB_SELECT),
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"IBX PCH dp port still using transcoder B\n");
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}
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@ -1501,7 +1501,7 @@ static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
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"PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
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i915_mmio_reg_offset(reg), pipe_name(pipe));
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I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
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I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
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&& (val & SDVO_PIPE_B_SELECT),
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"IBX PCH hdmi port still using transcoder B\n");
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}
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@ -1826,7 +1826,7 @@ static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
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val = I915_READ(reg);
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pipeconf_val = I915_READ(PIPECONF(pipe));
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if (HAS_PCH_IBX(dev_priv->dev)) {
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if (HAS_PCH_IBX(dev_priv)) {
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/*
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* Make the BPC in transcoder be consistent with
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* that in pipeconf reg. For HDMI we must use 8bpc
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@ -1841,7 +1841,7 @@ static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
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val &= ~TRANS_INTERLACE_MASK;
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if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
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if (HAS_PCH_IBX(dev_priv->dev) &&
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if (HAS_PCH_IBX(dev_priv) &&
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intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
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val |= TRANS_LEGACY_INTERLACED_ILK;
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else
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@ -1953,7 +1953,7 @@ static void intel_enable_pipe(struct intel_crtc *crtc)
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assert_cursor_disabled(dev_priv, pipe);
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assert_sprites_disabled(dev_priv, pipe);
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if (HAS_PCH_LPT(dev_priv->dev))
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if (HAS_PCH_LPT(dev_priv))
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pch_transcoder = TRANSCODER_A;
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else
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pch_transcoder = pipe;
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@ -1963,7 +1963,7 @@ static void intel_enable_pipe(struct intel_crtc *crtc)
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* a plane. On ILK+ the pipe PLLs are integrated, so we don't
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* need the check.
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*/
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if (HAS_GMCH_DISPLAY(dev_priv->dev))
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if (HAS_GMCH_DISPLAY(dev_priv))
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if (crtc->config->has_dsi_encoder)
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assert_dsi_pll_enabled(dev_priv);
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else
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@ -6501,7 +6501,7 @@ static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
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return false;
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/* HSW can handle pixel rate up to cdclk? */
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if (IS_HASWELL(dev_priv->dev))
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if (IS_HASWELL(dev_priv))
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return true;
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/*
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@ -9265,7 +9265,7 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
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ironlake_get_fdi_m_n_config(crtc, pipe_config);
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if (HAS_PCH_IBX(dev_priv->dev)) {
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if (HAS_PCH_IBX(dev_priv)) {
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pll_id = (enum intel_dpll_id) crtc->pipe;
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} else {
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tmp = I915_READ(PCH_DPLL_SEL);
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@ -16174,7 +16174,7 @@ intel_display_capture_error_state(struct drm_device *dev)
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/* Note: this does not include DSI transcoders. */
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error->num_transcoders = INTEL_INFO(dev)->num_pipes;
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if (HAS_DDI(dev_priv->dev))
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if (HAS_DDI(dev_priv))
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error->num_transcoders++; /* Account for eDP. */
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for (i = 0; i < error->num_transcoders; i++) {
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@ -298,7 +298,7 @@ static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
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u32 val;
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bool enabled;
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I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
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I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
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val = I915_READ(PCH_DREF_CONTROL);
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enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
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@ -333,7 +333,7 @@ bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
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old = !intel_crtc->pch_fifo_underrun_disabled;
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intel_crtc->pch_fifo_underrun_disabled = !enable;
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if (HAS_PCH_IBX(dev_priv->dev))
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if (HAS_PCH_IBX(dev_priv))
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ibx_set_fifo_underrun_reporting(dev_priv->dev, pch_transcoder,
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enable);
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else
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@ -363,7 +363,7 @@ void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
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return;
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/* GMCH can't disable fifo underruns, filter them. */
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if (HAS_GMCH_DISPLAY(dev_priv->dev) &&
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if (HAS_GMCH_DISPLAY(dev_priv) &&
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to_intel_crtc(crtc)->cpu_fifo_underrun_disabled)
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return;
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@ -638,7 +638,7 @@ static bool intel_hdmi_set_gcp_infoframe(struct drm_encoder *encoder)
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reg = HSW_TVIDEO_DIP_GCP(crtc->config->cpu_transcoder);
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else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
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reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
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else if (HAS_PCH_SPLIT(dev_priv->dev))
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else if (HAS_PCH_SPLIT(dev_priv))
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reg = TVIDEO_DIP_GCP(crtc->pipe);
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else
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return false;
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@ -124,7 +124,7 @@ static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable)
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u32 val;
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/* When using bit bashing for I2C, this bit needs to be set to 1 */
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if (!IS_PINEVIEW(dev_priv->dev))
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if (!IS_PINEVIEW(dev_priv))
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return;
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val = I915_READ(DSPCLK_GATE_D);
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@ -264,7 +264,7 @@ gmbus_wait_hw_status(struct drm_i915_private *dev_priv,
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u32 gmbus2 = 0;
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DEFINE_WAIT(wait);
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if (!HAS_GMBUS_IRQ(dev_priv->dev))
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if (!HAS_GMBUS_IRQ(dev_priv))
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gmbus4_irq_en = 0;
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/* Important: The hw handles only the first bit, so set only one! Since
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@ -300,7 +300,7 @@ gmbus_wait_idle(struct drm_i915_private *dev_priv)
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#define C ((I915_READ_NOTRACE(GMBUS2) & GMBUS_ACTIVE) == 0)
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if (!HAS_GMBUS_IRQ(dev_priv->dev))
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if (!HAS_GMBUS_IRQ(dev_priv))
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return wait_for(C, 10);
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/* Important: The hw handles only the first bit, so set only one! */
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|
@ -4302,7 +4302,7 @@ static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
|
|||
* the hw runs at the minimal clock before selecting the desired
|
||||
* frequency, if the down threshold expires in that window we will not
|
||||
* receive a down interrupt. */
|
||||
if (IS_GEN9(dev_priv->dev)) {
|
||||
if (IS_GEN9(dev_priv)) {
|
||||
limits = (dev_priv->rps.max_freq_softlimit) << 23;
|
||||
if (val <= dev_priv->rps.min_freq_softlimit)
|
||||
limits |= (dev_priv->rps.min_freq_softlimit) << 14;
|
||||
|
@ -7340,12 +7340,12 @@ static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
|
|||
|
||||
int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
|
||||
{
|
||||
if (IS_GEN9(dev_priv->dev))
|
||||
if (IS_GEN9(dev_priv))
|
||||
return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
|
||||
GEN9_FREQ_SCALER);
|
||||
else if (IS_CHERRYVIEW(dev_priv->dev))
|
||||
else if (IS_CHERRYVIEW(dev_priv))
|
||||
return chv_gpu_freq(dev_priv, val);
|
||||
else if (IS_VALLEYVIEW(dev_priv->dev))
|
||||
else if (IS_VALLEYVIEW(dev_priv))
|
||||
return byt_gpu_freq(dev_priv, val);
|
||||
else
|
||||
return val * GT_FREQUENCY_MULTIPLIER;
|
||||
|
@ -7353,12 +7353,12 @@ int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
|
|||
|
||||
int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
|
||||
{
|
||||
if (IS_GEN9(dev_priv->dev))
|
||||
if (IS_GEN9(dev_priv))
|
||||
return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
|
||||
GT_FREQUENCY_MULTIPLIER);
|
||||
else if (IS_CHERRYVIEW(dev_priv->dev))
|
||||
else if (IS_CHERRYVIEW(dev_priv))
|
||||
return chv_freq_opcode(dev_priv, val);
|
||||
else if (IS_VALLEYVIEW(dev_priv->dev))
|
||||
else if (IS_VALLEYVIEW(dev_priv))
|
||||
return byt_freq_opcode(dev_priv, val);
|
||||
else
|
||||
return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
|
||||
|
|
|
@ -563,7 +563,7 @@ static void intel_psr_work(struct work_struct *work)
|
|||
* PSR might take some time to get fully disabled
|
||||
* and be ready for re-enable.
|
||||
*/
|
||||
if (HAS_DDI(dev_priv->dev)) {
|
||||
if (HAS_DDI(dev_priv)) {
|
||||
if (wait_for((I915_READ(EDP_PSR_STATUS_CTL) &
|
||||
EDP_PSR_STATUS_STATE_MASK) == 0, 50)) {
|
||||
DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
|
||||
|
|
|
@ -2039,17 +2039,17 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
|
|||
* The enabling order will be from lower to higher indexed wells,
|
||||
* the disabling order is reversed.
|
||||
*/
|
||||
if (IS_HASWELL(dev_priv->dev)) {
|
||||
if (IS_HASWELL(dev_priv)) {
|
||||
set_power_wells(power_domains, hsw_power_wells);
|
||||
} else if (IS_BROADWELL(dev_priv->dev)) {
|
||||
} else if (IS_BROADWELL(dev_priv)) {
|
||||
set_power_wells(power_domains, bdw_power_wells);
|
||||
} else if (IS_SKYLAKE(dev_priv->dev) || IS_KABYLAKE(dev_priv->dev)) {
|
||||
} else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
|
||||
set_power_wells(power_domains, skl_power_wells);
|
||||
} else if (IS_BROXTON(dev_priv->dev)) {
|
||||
} else if (IS_BROXTON(dev_priv)) {
|
||||
set_power_wells(power_domains, bxt_power_wells);
|
||||
} else if (IS_CHERRYVIEW(dev_priv->dev)) {
|
||||
} else if (IS_CHERRYVIEW(dev_priv)) {
|
||||
set_power_wells(power_domains, chv_power_wells);
|
||||
} else if (IS_VALLEYVIEW(dev_priv->dev)) {
|
||||
} else if (IS_VALLEYVIEW(dev_priv)) {
|
||||
set_power_wells(power_domains, vlv_power_wells);
|
||||
} else {
|
||||
set_power_wells(power_domains, i9xx_always_on_power_well);
|
||||
|
|
|
@ -204,7 +204,7 @@ static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
|
|||
|
||||
/* On VLV, FIFO will be shared by both SW and HW.
|
||||
* So, we need to read the FREE_ENTRIES everytime */
|
||||
if (IS_VALLEYVIEW(dev_priv->dev))
|
||||
if (IS_VALLEYVIEW(dev_priv))
|
||||
dev_priv->uncore.fifo_count = fifo_free_entries(dev_priv);
|
||||
|
||||
if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
|
||||
|
@ -1161,7 +1161,7 @@ static void intel_uncore_fw_domains_init(struct drm_device *dev)
|
|||
{
|
||||
struct drm_i915_private *dev_priv = dev->dev_private;
|
||||
|
||||
if (INTEL_INFO(dev_priv->dev)->gen <= 5)
|
||||
if (INTEL_INFO(dev_priv)->gen <= 5)
|
||||
return;
|
||||
|
||||
if (IS_GEN9(dev)) {
|
||||
|
|
Loading…
Reference in a new issue