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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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drm/msm: update generated headers
Signed-off-by: Rob Clark <robdclark@gmail.com>
This commit is contained in:
parent
657c63f0af
commit
2d3584eb87
17 changed files with 675 additions and 215 deletions
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@ -8,15 +8,15 @@ This file was generated by the rules-ng-ng headergen tool in this git repository
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|||
git clone https://github.com/freedreno/envytools.git
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The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 364 bytes, from 2013-11-30 14:47:15)
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- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2014-06-02 15:21:30)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10551 bytes, from 2014-11-13 22:44:30)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14895 bytes, from 2015-04-19 15:23:28)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 66709 bytes, from 2015-04-12 18:16:35)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 60633 bytes, from 2015-05-20 14:48:19)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 364 bytes, from 2015-05-20 20:03:07)
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- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2015-05-20 20:03:14)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10551 bytes, from 2015-05-20 20:03:14)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14968 bytes, from 2015-05-20 20:12:27)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 67120 bytes, from 2015-08-14 23:22:03)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 63785 bytes, from 2015-08-14 18:27:06)
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Copyright (C) 2013-2014 by the following authors:
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Copyright (C) 2013-2015 by the following authors:
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- Rob Clark <robdclark@gmail.com> (robclark)
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Permission is hereby granted, free of charge, to any person obtaining
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@ -8,13 +8,13 @@ This file was generated by the rules-ng-ng headergen tool in this git repository
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|||
git clone https://github.com/freedreno/envytools.git
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||||
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||||
The rules-ng-ng source files this header was generated from are:
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||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 364 bytes, from 2013-11-30 14:47:15)
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- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2014-06-02 15:21:30)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10551 bytes, from 2014-11-13 22:44:30)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14895 bytes, from 2015-04-19 15:23:28)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 66709 bytes, from 2015-04-12 18:16:35)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 60633 bytes, from 2015-05-20 14:48:19)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 364 bytes, from 2015-05-20 20:03:07)
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- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07)
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||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2015-05-20 20:03:14)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10551 bytes, from 2015-05-20 20:03:14)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14968 bytes, from 2015-05-20 20:12:27)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 67120 bytes, from 2015-08-14 23:22:03)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 63785 bytes, from 2015-08-14 18:27:06)
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Copyright (C) 2013-2015 by the following authors:
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- Rob Clark <robdclark@gmail.com> (robclark)
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@ -326,6 +326,13 @@ enum a3xx_tex_type {
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A3XX_TEX_3D = 3,
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};
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enum a3xx_tex_msaa {
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A3XX_TPL1_MSAA1X = 0,
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A3XX_TPL1_MSAA2X = 1,
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A3XX_TPL1_MSAA4X = 2,
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A3XX_TPL1_MSAA8X = 3,
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};
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#define A3XX_INT0_RBBM_GPU_IDLE 0x00000001
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#define A3XX_INT0_RBBM_AHB_ERROR 0x00000002
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#define A3XX_INT0_RBBM_REG_TIMEOUT 0x00000004
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@ -2652,6 +2659,7 @@ static inline uint32_t A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES(uint32_t val)
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#define REG_A3XX_VGT_IMMED_DATA 0x000021fd
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#define REG_A3XX_TEX_SAMP_0 0x00000000
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#define A3XX_TEX_SAMP_0_CLAMPENABLE 0x00000001
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#define A3XX_TEX_SAMP_0_MIPFILTER_LINEAR 0x00000002
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#define A3XX_TEX_SAMP_0_XY_MAG__MASK 0x0000000c
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#define A3XX_TEX_SAMP_0_XY_MAG__SHIFT 2
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@ -2695,6 +2703,7 @@ static inline uint32_t A3XX_TEX_SAMP_0_COMPARE_FUNC(enum adreno_compare_func val
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{
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return ((val) << A3XX_TEX_SAMP_0_COMPARE_FUNC__SHIFT) & A3XX_TEX_SAMP_0_COMPARE_FUNC__MASK;
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}
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#define A3XX_TEX_SAMP_0_CUBEMAPSEAMLESSFILTOFF 0x01000000
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#define A3XX_TEX_SAMP_0_UNNORM_COORDS 0x80000000
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#define REG_A3XX_TEX_SAMP_1 0x00000001
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@ -2750,6 +2759,12 @@ static inline uint32_t A3XX_TEX_CONST_0_MIPLVLS(uint32_t val)
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{
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return ((val) << A3XX_TEX_CONST_0_MIPLVLS__SHIFT) & A3XX_TEX_CONST_0_MIPLVLS__MASK;
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}
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#define A3XX_TEX_CONST_0_MSAATEX__MASK 0x00300000
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#define A3XX_TEX_CONST_0_MSAATEX__SHIFT 20
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static inline uint32_t A3XX_TEX_CONST_0_MSAATEX(enum a3xx_tex_msaa val)
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{
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return ((val) << A3XX_TEX_CONST_0_MSAATEX__SHIFT) & A3XX_TEX_CONST_0_MSAATEX__MASK;
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}
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#define A3XX_TEX_CONST_0_FMT__MASK 0x1fc00000
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#define A3XX_TEX_CONST_0_FMT__SHIFT 22
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static inline uint32_t A3XX_TEX_CONST_0_FMT(enum a3xx_tex_fmt val)
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@ -2785,7 +2800,7 @@ static inline uint32_t A3XX_TEX_CONST_1_FETCHSIZE(enum a3xx_tex_fetchsize val)
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}
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#define REG_A3XX_TEX_CONST_2 0x00000002
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#define A3XX_TEX_CONST_2_INDX__MASK 0x000000ff
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#define A3XX_TEX_CONST_2_INDX__MASK 0x000001ff
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#define A3XX_TEX_CONST_2_INDX__SHIFT 0
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static inline uint32_t A3XX_TEX_CONST_2_INDX(uint32_t val)
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{
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@ -2805,7 +2820,7 @@ static inline uint32_t A3XX_TEX_CONST_2_SWAP(enum a3xx_color_swap val)
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}
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#define REG_A3XX_TEX_CONST_3 0x00000003
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#define A3XX_TEX_CONST_3_LAYERSZ1__MASK 0x00007fff
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#define A3XX_TEX_CONST_3_LAYERSZ1__MASK 0x0001ffff
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#define A3XX_TEX_CONST_3_LAYERSZ1__SHIFT 0
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static inline uint32_t A3XX_TEX_CONST_3_LAYERSZ1(uint32_t val)
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{
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@ -8,13 +8,13 @@ This file was generated by the rules-ng-ng headergen tool in this git repository
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|||
git clone https://github.com/freedreno/envytools.git
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||||
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||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 364 bytes, from 2013-11-30 14:47:15)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2014-06-02 15:21:30)
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||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10551 bytes, from 2014-11-13 22:44:30)
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||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14895 bytes, from 2015-04-19 15:23:28)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 66709 bytes, from 2015-04-12 18:16:35)
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||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 60633 bytes, from 2015-05-20 14:48:19)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 364 bytes, from 2015-05-20 20:03:07)
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- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2015-05-20 20:03:14)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10551 bytes, from 2015-05-20 20:03:14)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14968 bytes, from 2015-05-20 20:12:27)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 67120 bytes, from 2015-08-14 23:22:03)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 63785 bytes, from 2015-08-14 18:27:06)
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Copyright (C) 2013-2015 by the following authors:
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- Rob Clark <robdclark@gmail.com> (robclark)
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@ -227,6 +227,7 @@ enum a4xx_depth_format {
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DEPTH4_NONE = 0,
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DEPTH4_16 = 1,
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DEPTH4_24_8 = 2,
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DEPTH4_32 = 3,
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};
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enum a4xx_tess_spacing {
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@ -429,7 +430,7 @@ static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val)
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return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK;
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}
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#define A4XX_RB_MRT_BUF_INFO_COLOR_SRGB 0x00002000
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#define A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK 0x007fc000
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#define A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK 0xffffc000
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#define A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT 14
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static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val)
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{
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@ -439,7 +440,7 @@ static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val)
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static inline uint32_t REG_A4XX_RB_MRT_BASE(uint32_t i0) { return 0x000020a6 + 0x5*i0; }
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static inline uint32_t REG_A4XX_RB_MRT_CONTROL3(uint32_t i0) { return 0x000020a7 + 0x5*i0; }
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#define A4XX_RB_MRT_CONTROL3_STRIDE__MASK 0x0001fff8
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#define A4XX_RB_MRT_CONTROL3_STRIDE__MASK 0x03fffff8
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#define A4XX_RB_MRT_CONTROL3_STRIDE__SHIFT 3
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static inline uint32_t A4XX_RB_MRT_CONTROL3_STRIDE(uint32_t val)
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{
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@ -570,6 +571,15 @@ static inline uint32_t A4XX_RB_FS_OUTPUT_SAMPLE_MASK(uint32_t val)
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return ((val) << A4XX_RB_FS_OUTPUT_SAMPLE_MASK__SHIFT) & A4XX_RB_FS_OUTPUT_SAMPLE_MASK__MASK;
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}
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#define REG_A4XX_RB_SAMPLE_COUNT_CONTROL 0x000020fa
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#define A4XX_RB_SAMPLE_COUNT_CONTROL_COPY 0x00000002
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#define A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__MASK 0xfffffffc
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#define A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__SHIFT 2
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static inline uint32_t A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR(uint32_t val)
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{
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return ((val >> 2) << A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__SHIFT) & A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__MASK;
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}
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#define REG_A4XX_RB_RENDER_COMPONENTS 0x000020fb
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#define A4XX_RB_RENDER_COMPONENTS_RT0__MASK 0x0000000f
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#define A4XX_RB_RENDER_COMPONENTS_RT0__SHIFT 0
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#define REG_A4XX_RB_STENCIL_CONTROL2 0x00002107
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#define A4XX_RB_STENCIL_CONTROL2_STENCIL_BUFFER 0x00000001
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#define REG_A4XX_RB_STENCIL_INFO 0x00002108
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#define A4XX_RB_STENCIL_INFO_SEPARATE_STENCIL 0x00000001
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#define A4XX_RB_STENCIL_INFO_STENCIL_BASE__MASK 0xfffff000
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#define A4XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT 12
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static inline uint32_t A4XX_RB_STENCIL_INFO_STENCIL_BASE(uint32_t val)
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{
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return ((val >> 12) << A4XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT) & A4XX_RB_STENCIL_INFO_STENCIL_BASE__MASK;
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}
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#define REG_A4XX_RB_STENCIL_PITCH 0x00002109
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#define A4XX_RB_STENCIL_PITCH__MASK 0xffffffff
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#define A4XX_RB_STENCIL_PITCH__SHIFT 0
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static inline uint32_t A4XX_RB_STENCIL_PITCH(uint32_t val)
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{
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return ((val >> 5) << A4XX_RB_STENCIL_PITCH__SHIFT) & A4XX_RB_STENCIL_PITCH__MASK;
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}
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#define REG_A4XX_RB_STENCILREFMASK 0x0000210b
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#define A4XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff
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#define A4XX_RB_STENCILREFMASK_STENCILREF__SHIFT 0
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{
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return ((val) << A4XX_SP_FS_MRT_REG_MRTFORMAT__SHIFT) & A4XX_SP_FS_MRT_REG_MRTFORMAT__MASK;
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}
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#define A4XX_SP_FS_MRT_REG_COLOR_SRGB 0x00040000
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#define REG_A4XX_SP_CS_CTRL_REG0 0x00002300
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@ -1470,6 +1498,76 @@ static inline uint32_t A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
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#define REG_A4XX_SP_HS_LENGTH_REG 0x00002312
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#define REG_A4XX_SP_DS_PARAM_REG 0x0000231a
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#define A4XX_SP_DS_PARAM_REG_POSREGID__MASK 0x000000ff
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#define A4XX_SP_DS_PARAM_REG_POSREGID__SHIFT 0
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static inline uint32_t A4XX_SP_DS_PARAM_REG_POSREGID(uint32_t val)
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{
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return ((val) << A4XX_SP_DS_PARAM_REG_POSREGID__SHIFT) & A4XX_SP_DS_PARAM_REG_POSREGID__MASK;
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}
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#define A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__MASK 0xfff00000
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#define A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__SHIFT 20
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static inline uint32_t A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR(uint32_t val)
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{
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return ((val) << A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__SHIFT) & A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__MASK;
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}
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static inline uint32_t REG_A4XX_SP_DS_OUT(uint32_t i0) { return 0x0000231b + 0x1*i0; }
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static inline uint32_t REG_A4XX_SP_DS_OUT_REG(uint32_t i0) { return 0x0000231b + 0x1*i0; }
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#define A4XX_SP_DS_OUT_REG_A_REGID__MASK 0x000001ff
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#define A4XX_SP_DS_OUT_REG_A_REGID__SHIFT 0
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static inline uint32_t A4XX_SP_DS_OUT_REG_A_REGID(uint32_t val)
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{
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return ((val) << A4XX_SP_DS_OUT_REG_A_REGID__SHIFT) & A4XX_SP_DS_OUT_REG_A_REGID__MASK;
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}
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#define A4XX_SP_DS_OUT_REG_A_COMPMASK__MASK 0x00001e00
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#define A4XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT 9
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static inline uint32_t A4XX_SP_DS_OUT_REG_A_COMPMASK(uint32_t val)
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{
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return ((val) << A4XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT) & A4XX_SP_DS_OUT_REG_A_COMPMASK__MASK;
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}
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#define A4XX_SP_DS_OUT_REG_B_REGID__MASK 0x01ff0000
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#define A4XX_SP_DS_OUT_REG_B_REGID__SHIFT 16
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static inline uint32_t A4XX_SP_DS_OUT_REG_B_REGID(uint32_t val)
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{
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return ((val) << A4XX_SP_DS_OUT_REG_B_REGID__SHIFT) & A4XX_SP_DS_OUT_REG_B_REGID__MASK;
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}
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#define A4XX_SP_DS_OUT_REG_B_COMPMASK__MASK 0x1e000000
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#define A4XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT 25
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static inline uint32_t A4XX_SP_DS_OUT_REG_B_COMPMASK(uint32_t val)
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{
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return ((val) << A4XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_DS_OUT_REG_B_COMPMASK__MASK;
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}
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static inline uint32_t REG_A4XX_SP_DS_VPC_DST(uint32_t i0) { return 0x0000232c + 0x1*i0; }
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static inline uint32_t REG_A4XX_SP_DS_VPC_DST_REG(uint32_t i0) { return 0x0000232c + 0x1*i0; }
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#define A4XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
|
||||
#define A4XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT 0
|
||||
static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC0(uint32_t val)
|
||||
{
|
||||
return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK;
|
||||
}
|
||||
#define A4XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00
|
||||
#define A4XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT 8
|
||||
static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC1(uint32_t val)
|
||||
{
|
||||
return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK;
|
||||
}
|
||||
#define A4XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000
|
||||
#define A4XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT 16
|
||||
static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC2(uint32_t val)
|
||||
{
|
||||
return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK;
|
||||
}
|
||||
#define A4XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
|
||||
#define A4XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT 24
|
||||
static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC3(uint32_t val)
|
||||
{
|
||||
return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK;
|
||||
}
|
||||
|
||||
#define REG_A4XX_SP_DS_OBJ_OFFSET_REG 0x00002334
|
||||
#define A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
|
||||
#define A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
|
||||
|
@ -1492,6 +1590,82 @@ static inline uint32_t A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
|
|||
|
||||
#define REG_A4XX_SP_DS_LENGTH_REG 0x00002339
|
||||
|
||||
#define REG_A4XX_SP_GS_PARAM_REG 0x00002341
|
||||
#define A4XX_SP_GS_PARAM_REG_POSREGID__MASK 0x000000ff
|
||||
#define A4XX_SP_GS_PARAM_REG_POSREGID__SHIFT 0
|
||||
static inline uint32_t A4XX_SP_GS_PARAM_REG_POSREGID(uint32_t val)
|
||||
{
|
||||
return ((val) << A4XX_SP_GS_PARAM_REG_POSREGID__SHIFT) & A4XX_SP_GS_PARAM_REG_POSREGID__MASK;
|
||||
}
|
||||
#define A4XX_SP_GS_PARAM_REG_PRIMREGID__MASK 0x0000ff00
|
||||
#define A4XX_SP_GS_PARAM_REG_PRIMREGID__SHIFT 8
|
||||
static inline uint32_t A4XX_SP_GS_PARAM_REG_PRIMREGID(uint32_t val)
|
||||
{
|
||||
return ((val) << A4XX_SP_GS_PARAM_REG_PRIMREGID__SHIFT) & A4XX_SP_GS_PARAM_REG_PRIMREGID__MASK;
|
||||
}
|
||||
#define A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__MASK 0xfff00000
|
||||
#define A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__SHIFT 20
|
||||
static inline uint32_t A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR(uint32_t val)
|
||||
{
|
||||
return ((val) << A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__SHIFT) & A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__MASK;
|
||||
}
|
||||
|
||||
static inline uint32_t REG_A4XX_SP_GS_OUT(uint32_t i0) { return 0x00002342 + 0x1*i0; }
|
||||
|
||||
static inline uint32_t REG_A4XX_SP_GS_OUT_REG(uint32_t i0) { return 0x00002342 + 0x1*i0; }
|
||||
#define A4XX_SP_GS_OUT_REG_A_REGID__MASK 0x000001ff
|
||||
#define A4XX_SP_GS_OUT_REG_A_REGID__SHIFT 0
|
||||
static inline uint32_t A4XX_SP_GS_OUT_REG_A_REGID(uint32_t val)
|
||||
{
|
||||
return ((val) << A4XX_SP_GS_OUT_REG_A_REGID__SHIFT) & A4XX_SP_GS_OUT_REG_A_REGID__MASK;
|
||||
}
|
||||
#define A4XX_SP_GS_OUT_REG_A_COMPMASK__MASK 0x00001e00
|
||||
#define A4XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT 9
|
||||
static inline uint32_t A4XX_SP_GS_OUT_REG_A_COMPMASK(uint32_t val)
|
||||
{
|
||||
return ((val) << A4XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT) & A4XX_SP_GS_OUT_REG_A_COMPMASK__MASK;
|
||||
}
|
||||
#define A4XX_SP_GS_OUT_REG_B_REGID__MASK 0x01ff0000
|
||||
#define A4XX_SP_GS_OUT_REG_B_REGID__SHIFT 16
|
||||
static inline uint32_t A4XX_SP_GS_OUT_REG_B_REGID(uint32_t val)
|
||||
{
|
||||
return ((val) << A4XX_SP_GS_OUT_REG_B_REGID__SHIFT) & A4XX_SP_GS_OUT_REG_B_REGID__MASK;
|
||||
}
|
||||
#define A4XX_SP_GS_OUT_REG_B_COMPMASK__MASK 0x1e000000
|
||||
#define A4XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT 25
|
||||
static inline uint32_t A4XX_SP_GS_OUT_REG_B_COMPMASK(uint32_t val)
|
||||
{
|
||||
return ((val) << A4XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_GS_OUT_REG_B_COMPMASK__MASK;
|
||||
}
|
||||
|
||||
static inline uint32_t REG_A4XX_SP_GS_VPC_DST(uint32_t i0) { return 0x00002353 + 0x1*i0; }
|
||||
|
||||
static inline uint32_t REG_A4XX_SP_GS_VPC_DST_REG(uint32_t i0) { return 0x00002353 + 0x1*i0; }
|
||||
#define A4XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
|
||||
#define A4XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT 0
|
||||
static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC0(uint32_t val)
|
||||
{
|
||||
return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK;
|
||||
}
|
||||
#define A4XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00
|
||||
#define A4XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT 8
|
||||
static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC1(uint32_t val)
|
||||
{
|
||||
return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK;
|
||||
}
|
||||
#define A4XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000
|
||||
#define A4XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT 16
|
||||
static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC2(uint32_t val)
|
||||
{
|
||||
return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK;
|
||||
}
|
||||
#define A4XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
|
||||
#define A4XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT 24
|
||||
static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC3(uint32_t val)
|
||||
{
|
||||
return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK;
|
||||
}
|
||||
|
||||
#define REG_A4XX_SP_GS_OBJ_OFFSET_REG 0x0000235b
|
||||
#define A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
|
||||
#define A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
|
||||
|
@ -1693,6 +1867,18 @@ static inline uint32_t A4XX_VFD_CONTROL_3_REGID_VTXCNT(uint32_t val)
|
|||
{
|
||||
return ((val) << A4XX_VFD_CONTROL_3_REGID_VTXCNT__SHIFT) & A4XX_VFD_CONTROL_3_REGID_VTXCNT__MASK;
|
||||
}
|
||||
#define A4XX_VFD_CONTROL_3_REGID_TESSX__MASK 0x00ff0000
|
||||
#define A4XX_VFD_CONTROL_3_REGID_TESSX__SHIFT 16
|
||||
static inline uint32_t A4XX_VFD_CONTROL_3_REGID_TESSX(uint32_t val)
|
||||
{
|
||||
return ((val) << A4XX_VFD_CONTROL_3_REGID_TESSX__SHIFT) & A4XX_VFD_CONTROL_3_REGID_TESSX__MASK;
|
||||
}
|
||||
#define A4XX_VFD_CONTROL_3_REGID_TESSY__MASK 0xff000000
|
||||
#define A4XX_VFD_CONTROL_3_REGID_TESSY__SHIFT 24
|
||||
static inline uint32_t A4XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val)
|
||||
{
|
||||
return ((val) << A4XX_VFD_CONTROL_3_REGID_TESSY__SHIFT) & A4XX_VFD_CONTROL_3_REGID_TESSY__MASK;
|
||||
}
|
||||
|
||||
#define REG_A4XX_VFD_CONTROL_4 0x00002204
|
||||
|
||||
|
@ -2489,6 +2675,8 @@ static inline uint32_t A4XX_UNKNOWN_20F7(float val)
|
|||
|
||||
#define REG_A4XX_UNKNOWN_22D7 0x000022d7
|
||||
|
||||
#define REG_A4XX_UNKNOWN_2352 0x00002352
|
||||
|
||||
#define REG_A4XX_TEX_SAMP_0 0x00000000
|
||||
#define A4XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR 0x00000001
|
||||
#define A4XX_TEX_SAMP_0_XY_MAG__MASK 0x00000006
|
||||
|
|
|
@ -8,15 +8,15 @@ This file was generated by the rules-ng-ng headergen tool in this git repository
|
|||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 364 bytes, from 2013-11-30 14:47:15)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2014-06-02 15:21:30)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10551 bytes, from 2014-11-13 22:44:30)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14895 bytes, from 2015-04-19 15:23:28)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 66709 bytes, from 2015-04-12 18:16:35)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 60633 bytes, from 2015-05-20 14:48:19)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 364 bytes, from 2015-05-20 20:03:07)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10551 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14968 bytes, from 2015-05-20 20:12:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 67120 bytes, from 2015-08-14 23:22:03)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 63785 bytes, from 2015-08-14 18:27:06)
|
||||
|
||||
Copyright (C) 2013-2014 by the following authors:
|
||||
Copyright (C) 2013-2015 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
|
|
|
@ -8,13 +8,13 @@ This file was generated by the rules-ng-ng headergen tool in this git repository
|
|||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 364 bytes, from 2013-11-30 14:47:15)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2014-06-02 15:21:30)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10551 bytes, from 2014-11-13 22:44:30)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14895 bytes, from 2015-04-19 15:23:28)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 66709 bytes, from 2015-04-12 18:16:35)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 60633 bytes, from 2015-05-20 14:48:19)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 364 bytes, from 2015-05-20 20:03:07)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10551 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14968 bytes, from 2015-05-20 20:12:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 67120 bytes, from 2015-08-14 23:22:03)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 63785 bytes, from 2015-08-14 18:27:06)
|
||||
|
||||
Copyright (C) 2013-2015 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
|
@ -67,7 +67,7 @@ enum vgt_event_type {
|
|||
|
||||
enum pc_di_primtype {
|
||||
DI_PT_NONE = 0,
|
||||
DI_PT_POINTLIST_A2XX = 1,
|
||||
DI_PT_POINTLIST_PSIZE = 1,
|
||||
DI_PT_LINELIST = 2,
|
||||
DI_PT_LINESTRIP = 3,
|
||||
DI_PT_TRILIST = 4,
|
||||
|
@ -75,7 +75,7 @@ enum pc_di_primtype {
|
|||
DI_PT_TRISTRIP = 6,
|
||||
DI_PT_LINELOOP = 7,
|
||||
DI_PT_RECTLIST = 8,
|
||||
DI_PT_POINTLIST_A3XX = 9,
|
||||
DI_PT_POINTLIST = 9,
|
||||
DI_PT_LINE_ADJ = 10,
|
||||
DI_PT_LINESTRIP_ADJ = 11,
|
||||
DI_PT_TRI_ADJ = 12,
|
||||
|
|
|
@ -8,17 +8,17 @@ This file was generated by the rules-ng-ng headergen tool in this git repository
|
|||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2014-12-05 15:34:49)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-03-24 22:05:22)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2352 bytes, from 2015-04-12 15:02:42)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 35083 bytes, from 2015-04-12 15:04:03)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 22094 bytes, from 2015-05-12 12:45:23)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2014-10-31 16:48:57)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29012 bytes, from 2015-05-12 12:45:23)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-12 12:45:23)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2576 bytes, from 2015-07-09 22:10:24)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 36021 bytes, from 2015-07-09 22:10:24)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 26057 bytes, from 2015-08-14 21:47:57)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2015-05-20 20:03:07)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29154 bytes, from 2015-08-10 21:25:43)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-20 20:03:14)
|
||||
|
||||
Copyright (C) 2013-2015 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
|
@ -382,6 +382,11 @@ static inline uint32_t DSI_TRIG_CTRL_STREAM(uint32_t val)
|
|||
#define REG_DSI_TRIG_DMA 0x0000008c
|
||||
|
||||
#define REG_DSI_DLN0_PHY_ERR 0x000000b0
|
||||
#define DSI_DLN0_PHY_ERR_DLN0_ERR_ESC 0x00000001
|
||||
#define DSI_DLN0_PHY_ERR_DLN0_ERR_SYNC_ESC 0x00000010
|
||||
#define DSI_DLN0_PHY_ERR_DLN0_ERR_CONTROL 0x00000100
|
||||
#define DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP0 0x00001000
|
||||
#define DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP1 0x00010000
|
||||
|
||||
#define REG_DSI_TIMEOUT_STATUS 0x000000bc
|
||||
|
||||
|
@ -435,6 +440,9 @@ static inline uint32_t DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(enum dsi_lane_swap val)
|
|||
#define REG_DSI_PHY_RESET 0x00000128
|
||||
#define DSI_PHY_RESET_RESET 0x00000001
|
||||
|
||||
#define REG_DSI_T_CLK_PRE_EXTEND 0x0000017c
|
||||
#define DSI_T_CLK_PRE_EXTEND_INC_BY_2_BYTECLK 0x00000001
|
||||
|
||||
#define REG_DSI_RDBK_DATA_CTRL 0x000001d0
|
||||
#define DSI_RDBK_DATA_CTRL_COUNT__MASK 0x00ff0000
|
||||
#define DSI_RDBK_DATA_CTRL_COUNT__SHIFT 16
|
||||
|
@ -830,6 +838,7 @@ static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)
|
|||
#define REG_DSI_28nm_PHY_BIST_CTRL_5 0x000001c8
|
||||
|
||||
#define REG_DSI_28nm_PHY_GLBL_TEST_CTRL 0x000001d4
|
||||
#define DSI_28nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL 0x00000001
|
||||
|
||||
#define REG_DSI_28nm_PHY_LDO_CNTRL 0x000001dc
|
||||
|
||||
|
@ -994,5 +1003,185 @@ static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8(uint32_t val)
|
|||
|
||||
#define REG_DSI_28nm_PHY_PLL_CTRL_54 0x000000d4
|
||||
|
||||
static inline uint32_t REG_DSI_20nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; }
|
||||
|
||||
static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; }
|
||||
|
||||
static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; }
|
||||
|
||||
static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; }
|
||||
|
||||
static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_3(uint32_t i0) { return 0x0000000c + 0x40*i0; }
|
||||
|
||||
static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_4(uint32_t i0) { return 0x00000010 + 0x40*i0; }
|
||||
|
||||
static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000014 + 0x40*i0; }
|
||||
|
||||
static inline uint32_t REG_DSI_20nm_PHY_LN_DEBUG_SEL(uint32_t i0) { return 0x00000018 + 0x40*i0; }
|
||||
|
||||
static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x0000001c + 0x40*i0; }
|
||||
|
||||
static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000020 + 0x40*i0; }
|
||||
|
||||
#define REG_DSI_20nm_PHY_LNCK_CFG_0 0x00000100
|
||||
|
||||
#define REG_DSI_20nm_PHY_LNCK_CFG_1 0x00000104
|
||||
|
||||
#define REG_DSI_20nm_PHY_LNCK_CFG_2 0x00000108
|
||||
|
||||
#define REG_DSI_20nm_PHY_LNCK_CFG_3 0x0000010c
|
||||
|
||||
#define REG_DSI_20nm_PHY_LNCK_CFG_4 0x00000110
|
||||
|
||||
#define REG_DSI_20nm_PHY_LNCK_TEST_DATAPATH 0x00000114
|
||||
|
||||
#define REG_DSI_20nm_PHY_LNCK_DEBUG_SEL 0x00000118
|
||||
|
||||
#define REG_DSI_20nm_PHY_LNCK_TEST_STR0 0x0000011c
|
||||
|
||||
#define REG_DSI_20nm_PHY_LNCK_TEST_STR1 0x00000120
|
||||
|
||||
#define REG_DSI_20nm_PHY_TIMING_CTRL_0 0x00000140
|
||||
#define DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK 0x000000ff
|
||||
#define DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT 0
|
||||
static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val)
|
||||
{
|
||||
return ((val) << DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK;
|
||||
}
|
||||
|
||||
#define REG_DSI_20nm_PHY_TIMING_CTRL_1 0x00000144
|
||||
#define DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK 0x000000ff
|
||||
#define DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT 0
|
||||
static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val)
|
||||
{
|
||||
return ((val) << DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK;
|
||||
}
|
||||
|
||||
#define REG_DSI_20nm_PHY_TIMING_CTRL_2 0x00000148
|
||||
#define DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK 0x000000ff
|
||||
#define DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT 0
|
||||
static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val)
|
||||
{
|
||||
return ((val) << DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK;
|
||||
}
|
||||
|
||||
#define REG_DSI_20nm_PHY_TIMING_CTRL_3 0x0000014c
|
||||
#define DSI_20nm_PHY_TIMING_CTRL_3_CLK_ZERO_8 0x00000001
|
||||
|
||||
#define REG_DSI_20nm_PHY_TIMING_CTRL_4 0x00000150
|
||||
#define DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff
|
||||
#define DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT 0
|
||||
static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val)
|
||||
{
|
||||
return ((val) << DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK;
|
||||
}
|
||||
|
||||
#define REG_DSI_20nm_PHY_TIMING_CTRL_5 0x00000154
|
||||
#define DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff
|
||||
#define DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT 0
|
||||
static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val)
|
||||
{
|
||||
return ((val) << DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK;
|
||||
}
|
||||
|
||||
#define REG_DSI_20nm_PHY_TIMING_CTRL_6 0x00000158
|
||||
#define DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff
|
||||
#define DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT 0
|
||||
static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val)
|
||||
{
|
||||
return ((val) << DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK;
|
||||
}
|
||||
|
||||
#define REG_DSI_20nm_PHY_TIMING_CTRL_7 0x0000015c
|
||||
#define DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff
|
||||
#define DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT 0
|
||||
static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val)
|
||||
{
|
||||
return ((val) << DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK;
|
||||
}
|
||||
|
||||
#define REG_DSI_20nm_PHY_TIMING_CTRL_8 0x00000160
|
||||
#define DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff
|
||||
#define DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT 0
|
||||
static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val)
|
||||
{
|
||||
return ((val) << DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__MASK;
|
||||
}
|
||||
|
||||
#define REG_DSI_20nm_PHY_TIMING_CTRL_9 0x00000164
|
||||
#define DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__MASK 0x00000007
|
||||
#define DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT 0
|
||||
static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_9_TA_GO(uint32_t val)
|
||||
{
|
||||
return ((val) << DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__MASK;
|
||||
}
|
||||
#define DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__MASK 0x00000070
|
||||
#define DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT 4
|
||||
static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val)
|
||||
{
|
||||
return ((val) << DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__MASK;
|
||||
}
|
||||
|
||||
#define REG_DSI_20nm_PHY_TIMING_CTRL_10 0x00000168
|
||||
#define DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__MASK 0x00000007
|
||||
#define DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT 0
|
||||
static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_10_TA_GET(uint32_t val)
|
||||
{
|
||||
return ((val) << DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__MASK;
|
||||
}
|
||||
|
||||
#define REG_DSI_20nm_PHY_TIMING_CTRL_11 0x0000016c
|
||||
#define DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff
|
||||
#define DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0
|
||||
static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)
|
||||
{
|
||||
return ((val) << DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK;
|
||||
}
|
||||
|
||||
#define REG_DSI_20nm_PHY_CTRL_0 0x00000170
|
||||
|
||||
#define REG_DSI_20nm_PHY_CTRL_1 0x00000174
|
||||
|
||||
#define REG_DSI_20nm_PHY_CTRL_2 0x00000178
|
||||
|
||||
#define REG_DSI_20nm_PHY_CTRL_3 0x0000017c
|
||||
|
||||
#define REG_DSI_20nm_PHY_CTRL_4 0x00000180
|
||||
|
||||
#define REG_DSI_20nm_PHY_STRENGTH_0 0x00000184
|
||||
|
||||
#define REG_DSI_20nm_PHY_STRENGTH_1 0x00000188
|
||||
|
||||
#define REG_DSI_20nm_PHY_BIST_CTRL_0 0x000001b4
|
||||
|
||||
#define REG_DSI_20nm_PHY_BIST_CTRL_1 0x000001b8
|
||||
|
||||
#define REG_DSI_20nm_PHY_BIST_CTRL_2 0x000001bc
|
||||
|
||||
#define REG_DSI_20nm_PHY_BIST_CTRL_3 0x000001c0
|
||||
|
||||
#define REG_DSI_20nm_PHY_BIST_CTRL_4 0x000001c4
|
||||
|
||||
#define REG_DSI_20nm_PHY_BIST_CTRL_5 0x000001c8
|
||||
|
||||
#define REG_DSI_20nm_PHY_GLBL_TEST_CTRL 0x000001d4
|
||||
#define DSI_20nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL 0x00000001
|
||||
|
||||
#define REG_DSI_20nm_PHY_LDO_CNTRL 0x000001dc
|
||||
|
||||
#define REG_DSI_20nm_PHY_REGULATOR_CTRL_0 0x00000000
|
||||
|
||||
#define REG_DSI_20nm_PHY_REGULATOR_CTRL_1 0x00000004
|
||||
|
||||
#define REG_DSI_20nm_PHY_REGULATOR_CTRL_2 0x00000008
|
||||
|
||||
#define REG_DSI_20nm_PHY_REGULATOR_CTRL_3 0x0000000c
|
||||
|
||||
#define REG_DSI_20nm_PHY_REGULATOR_CTRL_4 0x00000010
|
||||
|
||||
#define REG_DSI_20nm_PHY_REGULATOR_CTRL_5 0x00000014
|
||||
|
||||
#define REG_DSI_20nm_PHY_REGULATOR_CAL_PWR_CFG 0x00000018
|
||||
|
||||
|
||||
#endif /* DSI_XML */
|
||||
|
|
|
@ -8,19 +8,19 @@ This file was generated by the rules-ng-ng headergen tool in this git repository
|
|||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2014-12-05 15:34:49)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-03-24 22:05:22)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2352 bytes, from 2015-04-12 15:02:42)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 35083 bytes, from 2015-04-12 15:04:03)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 22094 bytes, from 2015-05-12 12:45:23)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2014-10-31 16:48:57)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29012 bytes, from 2015-05-12 12:45:23)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-12 12:45:23)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2576 bytes, from 2015-07-09 22:10:24)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 36021 bytes, from 2015-07-09 22:10:24)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 26057 bytes, from 2015-08-14 21:47:57)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2015-05-20 20:03:07)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29154 bytes, from 2015-08-10 21:25:43)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-20 20:03:14)
|
||||
|
||||
Copyright (C) 2013-2014 by the following authors:
|
||||
Copyright (C) 2013-2015 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
|
|
|
@ -8,19 +8,19 @@ This file was generated by the rules-ng-ng headergen tool in this git repository
|
|||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2014-12-05 15:34:49)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-03-24 22:05:22)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2352 bytes, from 2015-04-12 15:02:42)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 35083 bytes, from 2015-04-12 15:04:03)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 22094 bytes, from 2015-05-12 12:45:23)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2014-10-31 16:48:57)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29012 bytes, from 2015-05-12 12:45:23)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-12 12:45:23)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2576 bytes, from 2015-07-09 22:10:24)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 36021 bytes, from 2015-07-09 22:10:24)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 26057 bytes, from 2015-08-14 21:47:57)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2015-05-20 20:03:07)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29154 bytes, from 2015-08-10 21:25:43)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-20 20:03:14)
|
||||
|
||||
Copyright (C) 2013 by the following authors:
|
||||
Copyright (C) 2013-2015 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
|
|
|
@ -8,17 +8,17 @@ This file was generated by the rules-ng-ng headergen tool in this git repository
|
|||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2014-12-05 15:34:49)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-03-24 22:05:22)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2352 bytes, from 2015-04-12 15:02:42)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 35083 bytes, from 2015-04-12 15:04:03)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 22094 bytes, from 2015-05-12 12:45:23)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2014-10-31 16:48:57)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29012 bytes, from 2015-05-12 12:45:23)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-12 12:45:23)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2576 bytes, from 2015-07-09 22:10:24)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 36021 bytes, from 2015-07-09 22:10:24)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 26057 bytes, from 2015-08-14 21:47:57)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2015-05-20 20:03:07)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29154 bytes, from 2015-08-10 21:25:43)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-20 20:03:14)
|
||||
|
||||
Copyright (C) 2013-2015 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
|
|
|
@ -8,17 +8,17 @@ This file was generated by the rules-ng-ng headergen tool in this git repository
|
|||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2014-12-05 15:34:49)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-03-24 22:05:22)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2352 bytes, from 2015-04-12 15:02:42)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 35083 bytes, from 2015-04-12 15:04:03)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 22094 bytes, from 2015-05-12 12:45:23)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2014-10-31 16:48:57)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29012 bytes, from 2015-05-12 12:45:23)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-12 12:45:23)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2576 bytes, from 2015-07-09 22:10:24)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 36021 bytes, from 2015-07-09 22:10:24)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 26057 bytes, from 2015-08-14 21:47:57)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2015-05-20 20:03:07)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29154 bytes, from 2015-08-10 21:25:43)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-20 20:03:14)
|
||||
|
||||
Copyright (C) 2013-2015 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
|
@ -441,6 +441,12 @@ static inline uint32_t HDMI_DDC_REF_REFTIMER(uint32_t val)
|
|||
|
||||
#define REG_HDMI_HDCP_SW_LOWER_AKSV 0x00000288
|
||||
|
||||
#define REG_HDMI_CEC_CTRL 0x0000028c
|
||||
|
||||
#define REG_HDMI_CEC_WR_DATA 0x00000290
|
||||
|
||||
#define REG_HDMI_CEC_CEC_RETRANSMIT 0x00000294
|
||||
|
||||
#define REG_HDMI_CEC_STATUS 0x00000298
|
||||
|
||||
#define REG_HDMI_CEC_INT 0x0000029c
|
||||
|
|
|
@ -8,19 +8,19 @@ This file was generated by the rules-ng-ng headergen tool in this git repository
|
|||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2014-12-05 15:34:49)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-03-24 22:05:22)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2352 bytes, from 2015-04-12 15:02:42)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 35083 bytes, from 2015-04-12 15:04:03)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 22094 bytes, from 2015-05-12 12:45:23)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2014-10-31 16:48:57)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29012 bytes, from 2015-05-12 12:45:23)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-12 12:45:23)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2576 bytes, from 2015-07-09 22:10:24)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 36021 bytes, from 2015-07-09 22:10:24)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 26057 bytes, from 2015-08-14 21:47:57)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2015-05-20 20:03:07)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29154 bytes, from 2015-08-10 21:25:43)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-20 20:03:14)
|
||||
|
||||
Copyright (C) 2013 by the following authors:
|
||||
Copyright (C) 2013-2015 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
|
|
|
@ -8,17 +8,17 @@ This file was generated by the rules-ng-ng headergen tool in this git repository
|
|||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2014-12-05 15:34:49)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-03-24 22:05:22)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2352 bytes, from 2015-04-12 15:02:42)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 35083 bytes, from 2015-04-12 15:04:03)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 22094 bytes, from 2015-05-12 12:45:23)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2014-10-31 16:48:57)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29012 bytes, from 2015-05-12 12:45:23)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-12 12:45:23)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2576 bytes, from 2015-07-09 22:10:24)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 36021 bytes, from 2015-07-09 22:10:24)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 26057 bytes, from 2015-08-14 21:47:57)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2015-05-20 20:03:07)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29154 bytes, from 2015-08-10 21:25:43)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-20 20:03:14)
|
||||
|
||||
Copyright (C) 2013-2015 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
|
|
|
@ -8,17 +8,17 @@ This file was generated by the rules-ng-ng headergen tool in this git repository
|
|||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2014-12-05 15:34:49)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-03-24 22:05:22)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2352 bytes, from 2015-04-12 15:02:42)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 35083 bytes, from 2015-04-12 15:04:03)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 22094 bytes, from 2015-05-12 12:45:23)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2014-10-31 16:48:57)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29012 bytes, from 2015-05-12 12:45:23)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-12 12:45:23)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2576 bytes, from 2015-07-09 22:10:24)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 36021 bytes, from 2015-07-09 22:10:24)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 26057 bytes, from 2015-08-14 21:47:57)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2015-05-20 20:03:07)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29154 bytes, from 2015-08-10 21:25:43)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-20 20:03:14)
|
||||
|
||||
Copyright (C) 2013-2015 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
|
@ -381,49 +381,49 @@ static inline uint32_t REG_MDP5_CTL_LAYER(uint32_t i0, uint32_t i1) { return 0x0
|
|||
static inline uint32_t REG_MDP5_CTL_LAYER_REG(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER(i1); }
|
||||
#define MDP5_CTL_LAYER_REG_VIG0__MASK 0x00000007
|
||||
#define MDP5_CTL_LAYER_REG_VIG0__SHIFT 0
|
||||
static inline uint32_t MDP5_CTL_LAYER_REG_VIG0(enum mdp_mixer_stage_id val)
|
||||
static inline uint32_t MDP5_CTL_LAYER_REG_VIG0(uint32_t val)
|
||||
{
|
||||
return ((val) << MDP5_CTL_LAYER_REG_VIG0__SHIFT) & MDP5_CTL_LAYER_REG_VIG0__MASK;
|
||||
}
|
||||
#define MDP5_CTL_LAYER_REG_VIG1__MASK 0x00000038
|
||||
#define MDP5_CTL_LAYER_REG_VIG1__SHIFT 3
|
||||
static inline uint32_t MDP5_CTL_LAYER_REG_VIG1(enum mdp_mixer_stage_id val)
|
||||
static inline uint32_t MDP5_CTL_LAYER_REG_VIG1(uint32_t val)
|
||||
{
|
||||
return ((val) << MDP5_CTL_LAYER_REG_VIG1__SHIFT) & MDP5_CTL_LAYER_REG_VIG1__MASK;
|
||||
}
|
||||
#define MDP5_CTL_LAYER_REG_VIG2__MASK 0x000001c0
|
||||
#define MDP5_CTL_LAYER_REG_VIG2__SHIFT 6
|
||||
static inline uint32_t MDP5_CTL_LAYER_REG_VIG2(enum mdp_mixer_stage_id val)
|
||||
static inline uint32_t MDP5_CTL_LAYER_REG_VIG2(uint32_t val)
|
||||
{
|
||||
return ((val) << MDP5_CTL_LAYER_REG_VIG2__SHIFT) & MDP5_CTL_LAYER_REG_VIG2__MASK;
|
||||
}
|
||||
#define MDP5_CTL_LAYER_REG_RGB0__MASK 0x00000e00
|
||||
#define MDP5_CTL_LAYER_REG_RGB0__SHIFT 9
|
||||
static inline uint32_t MDP5_CTL_LAYER_REG_RGB0(enum mdp_mixer_stage_id val)
|
||||
static inline uint32_t MDP5_CTL_LAYER_REG_RGB0(uint32_t val)
|
||||
{
|
||||
return ((val) << MDP5_CTL_LAYER_REG_RGB0__SHIFT) & MDP5_CTL_LAYER_REG_RGB0__MASK;
|
||||
}
|
||||
#define MDP5_CTL_LAYER_REG_RGB1__MASK 0x00007000
|
||||
#define MDP5_CTL_LAYER_REG_RGB1__SHIFT 12
|
||||
static inline uint32_t MDP5_CTL_LAYER_REG_RGB1(enum mdp_mixer_stage_id val)
|
||||
static inline uint32_t MDP5_CTL_LAYER_REG_RGB1(uint32_t val)
|
||||
{
|
||||
return ((val) << MDP5_CTL_LAYER_REG_RGB1__SHIFT) & MDP5_CTL_LAYER_REG_RGB1__MASK;
|
||||
}
|
||||
#define MDP5_CTL_LAYER_REG_RGB2__MASK 0x00038000
|
||||
#define MDP5_CTL_LAYER_REG_RGB2__SHIFT 15
|
||||
static inline uint32_t MDP5_CTL_LAYER_REG_RGB2(enum mdp_mixer_stage_id val)
|
||||
static inline uint32_t MDP5_CTL_LAYER_REG_RGB2(uint32_t val)
|
||||
{
|
||||
return ((val) << MDP5_CTL_LAYER_REG_RGB2__SHIFT) & MDP5_CTL_LAYER_REG_RGB2__MASK;
|
||||
}
|
||||
#define MDP5_CTL_LAYER_REG_DMA0__MASK 0x001c0000
|
||||
#define MDP5_CTL_LAYER_REG_DMA0__SHIFT 18
|
||||
static inline uint32_t MDP5_CTL_LAYER_REG_DMA0(enum mdp_mixer_stage_id val)
|
||||
static inline uint32_t MDP5_CTL_LAYER_REG_DMA0(uint32_t val)
|
||||
{
|
||||
return ((val) << MDP5_CTL_LAYER_REG_DMA0__SHIFT) & MDP5_CTL_LAYER_REG_DMA0__MASK;
|
||||
}
|
||||
#define MDP5_CTL_LAYER_REG_DMA1__MASK 0x00e00000
|
||||
#define MDP5_CTL_LAYER_REG_DMA1__SHIFT 21
|
||||
static inline uint32_t MDP5_CTL_LAYER_REG_DMA1(enum mdp_mixer_stage_id val)
|
||||
static inline uint32_t MDP5_CTL_LAYER_REG_DMA1(uint32_t val)
|
||||
{
|
||||
return ((val) << MDP5_CTL_LAYER_REG_DMA1__SHIFT) & MDP5_CTL_LAYER_REG_DMA1__MASK;
|
||||
}
|
||||
|
@ -431,13 +431,13 @@ static inline uint32_t MDP5_CTL_LAYER_REG_DMA1(enum mdp_mixer_stage_id val)
|
|||
#define MDP5_CTL_LAYER_REG_CURSOR_OUT 0x02000000
|
||||
#define MDP5_CTL_LAYER_REG_VIG3__MASK 0x1c000000
|
||||
#define MDP5_CTL_LAYER_REG_VIG3__SHIFT 26
|
||||
static inline uint32_t MDP5_CTL_LAYER_REG_VIG3(enum mdp_mixer_stage_id val)
|
||||
static inline uint32_t MDP5_CTL_LAYER_REG_VIG3(uint32_t val)
|
||||
{
|
||||
return ((val) << MDP5_CTL_LAYER_REG_VIG3__SHIFT) & MDP5_CTL_LAYER_REG_VIG3__MASK;
|
||||
}
|
||||
#define MDP5_CTL_LAYER_REG_RGB3__MASK 0xe0000000
|
||||
#define MDP5_CTL_LAYER_REG_RGB3__SHIFT 29
|
||||
static inline uint32_t MDP5_CTL_LAYER_REG_RGB3(enum mdp_mixer_stage_id val)
|
||||
static inline uint32_t MDP5_CTL_LAYER_REG_RGB3(uint32_t val)
|
||||
{
|
||||
return ((val) << MDP5_CTL_LAYER_REG_RGB3__SHIFT) & MDP5_CTL_LAYER_REG_RGB3__MASK;
|
||||
}
|
||||
|
@ -499,6 +499,44 @@ static inline uint32_t REG_MDP5_CTL_START(uint32_t i0) { return 0x0000001c + __o
|
|||
|
||||
static inline uint32_t REG_MDP5_CTL_PACK_3D(uint32_t i0) { return 0x00000020 + __offset_CTL(i0); }
|
||||
|
||||
static inline uint32_t __offset_LAYER_EXT(uint32_t idx)
|
||||
{
|
||||
switch (idx) {
|
||||
case 0: return 0x00000040;
|
||||
case 1: return 0x00000044;
|
||||
case 2: return 0x00000048;
|
||||
case 3: return 0x0000004c;
|
||||
case 4: return 0x00000050;
|
||||
case 5: return 0x00000054;
|
||||
default: return INVALID_IDX(idx);
|
||||
}
|
||||
}
|
||||
static inline uint32_t REG_MDP5_CTL_LAYER_EXT(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER_EXT(i1); }
|
||||
|
||||
static inline uint32_t REG_MDP5_CTL_LAYER_EXT_REG(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER_EXT(i1); }
|
||||
#define MDP5_CTL_LAYER_EXT_REG_VIG0_BIT3 0x00000001
|
||||
#define MDP5_CTL_LAYER_EXT_REG_VIG1_BIT3 0x00000004
|
||||
#define MDP5_CTL_LAYER_EXT_REG_VIG2_BIT3 0x00000010
|
||||
#define MDP5_CTL_LAYER_EXT_REG_VIG3_BIT3 0x00000040
|
||||
#define MDP5_CTL_LAYER_EXT_REG_RGB0_BIT3 0x00000100
|
||||
#define MDP5_CTL_LAYER_EXT_REG_RGB1_BIT3 0x00000400
|
||||
#define MDP5_CTL_LAYER_EXT_REG_RGB2_BIT3 0x00001000
|
||||
#define MDP5_CTL_LAYER_EXT_REG_RGB3_BIT3 0x00004000
|
||||
#define MDP5_CTL_LAYER_EXT_REG_DMA0_BIT3 0x00010000
|
||||
#define MDP5_CTL_LAYER_EXT_REG_DMA1_BIT3 0x00040000
|
||||
#define MDP5_CTL_LAYER_EXT_REG_CURSOR0__MASK 0x00f00000
|
||||
#define MDP5_CTL_LAYER_EXT_REG_CURSOR0__SHIFT 20
|
||||
static inline uint32_t MDP5_CTL_LAYER_EXT_REG_CURSOR0(enum mdp_mixer_stage_id val)
|
||||
{
|
||||
return ((val) << MDP5_CTL_LAYER_EXT_REG_CURSOR0__SHIFT) & MDP5_CTL_LAYER_EXT_REG_CURSOR0__MASK;
|
||||
}
|
||||
#define MDP5_CTL_LAYER_EXT_REG_CURSOR1__MASK 0x3c000000
|
||||
#define MDP5_CTL_LAYER_EXT_REG_CURSOR1__SHIFT 26
|
||||
static inline uint32_t MDP5_CTL_LAYER_EXT_REG_CURSOR1(enum mdp_mixer_stage_id val)
|
||||
{
|
||||
return ((val) << MDP5_CTL_LAYER_EXT_REG_CURSOR1__SHIFT) & MDP5_CTL_LAYER_EXT_REG_CURSOR1__MASK;
|
||||
}
|
||||
|
||||
static inline uint32_t __offset_PIPE(enum mdp5_pipe idx)
|
||||
{
|
||||
switch (idx) {
|
||||
|
@ -803,11 +841,11 @@ static inline uint32_t MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT(uint32_t val)
|
|||
}
|
||||
#define MDP5_PIPE_SRC_FORMAT_UNPACK_TIGHT 0x00020000
|
||||
#define MDP5_PIPE_SRC_FORMAT_UNPACK_ALIGN_MSB 0x00040000
|
||||
#define MDP5_PIPE_SRC_FORMAT_NUM_PLANES__MASK 0x00180000
|
||||
#define MDP5_PIPE_SRC_FORMAT_NUM_PLANES__SHIFT 19
|
||||
static inline uint32_t MDP5_PIPE_SRC_FORMAT_NUM_PLANES(enum mdp_fetch_type val)
|
||||
#define MDP5_PIPE_SRC_FORMAT_FETCH_TYPE__MASK 0x00180000
|
||||
#define MDP5_PIPE_SRC_FORMAT_FETCH_TYPE__SHIFT 19
|
||||
static inline uint32_t MDP5_PIPE_SRC_FORMAT_FETCH_TYPE(enum mdp_fetch_type val)
|
||||
{
|
||||
return ((val) << MDP5_PIPE_SRC_FORMAT_NUM_PLANES__SHIFT) & MDP5_PIPE_SRC_FORMAT_NUM_PLANES__MASK;
|
||||
return ((val) << MDP5_PIPE_SRC_FORMAT_FETCH_TYPE__SHIFT) & MDP5_PIPE_SRC_FORMAT_FETCH_TYPE__MASK;
|
||||
}
|
||||
#define MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__MASK 0x01800000
|
||||
#define MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__SHIFT 23
|
||||
|
@ -897,41 +935,41 @@ static inline uint32_t MDP5_PIPE_DECIMATION_HORZ(uint32_t val)
|
|||
static inline uint32_t REG_MDP5_PIPE_SCALE_CONFIG(enum mdp5_pipe i0) { return 0x00000204 + __offset_PIPE(i0); }
|
||||
#define MDP5_PIPE_SCALE_CONFIG_SCALEX_EN 0x00000001
|
||||
#define MDP5_PIPE_SCALE_CONFIG_SCALEY_EN 0x00000002
|
||||
#define MDP5_PIPE_SCALE_CONFIG_SCALEX_MIN_FILTER__MASK 0x00000300
|
||||
#define MDP5_PIPE_SCALE_CONFIG_SCALEX_MIN_FILTER__SHIFT 8
|
||||
static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_MIN_FILTER(enum mdp5_scale_filter val)
|
||||
#define MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0__MASK 0x00000300
|
||||
#define MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0__SHIFT 8
|
||||
static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0(enum mdp5_scale_filter val)
|
||||
{
|
||||
return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEX_MIN_FILTER__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEX_MIN_FILTER__MASK;
|
||||
return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0__MASK;
|
||||
}
|
||||
#define MDP5_PIPE_SCALE_CONFIG_SCALEY_MIN_FILTER__MASK 0x00000c00
|
||||
#define MDP5_PIPE_SCALE_CONFIG_SCALEY_MIN_FILTER__SHIFT 10
|
||||
static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_MIN_FILTER(enum mdp5_scale_filter val)
|
||||
#define MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0__MASK 0x00000c00
|
||||
#define MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0__SHIFT 10
|
||||
static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0(enum mdp5_scale_filter val)
|
||||
{
|
||||
return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEY_MIN_FILTER__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEY_MIN_FILTER__MASK;
|
||||
return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0__MASK;
|
||||
}
|
||||
#define MDP5_PIPE_SCALE_CONFIG_SCALEX_CR_FILTER__MASK 0x00003000
|
||||
#define MDP5_PIPE_SCALE_CONFIG_SCALEX_CR_FILTER__SHIFT 12
|
||||
static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_CR_FILTER(enum mdp5_scale_filter val)
|
||||
#define MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2__MASK 0x00003000
|
||||
#define MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2__SHIFT 12
|
||||
static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2(enum mdp5_scale_filter val)
|
||||
{
|
||||
return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEX_CR_FILTER__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEX_CR_FILTER__MASK;
|
||||
return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2__MASK;
|
||||
}
|
||||
#define MDP5_PIPE_SCALE_CONFIG_SCALEY_CR_FILTER__MASK 0x0000c000
|
||||
#define MDP5_PIPE_SCALE_CONFIG_SCALEY_CR_FILTER__SHIFT 14
|
||||
static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_CR_FILTER(enum mdp5_scale_filter val)
|
||||
#define MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2__MASK 0x0000c000
|
||||
#define MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2__SHIFT 14
|
||||
static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2(enum mdp5_scale_filter val)
|
||||
{
|
||||
return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEY_CR_FILTER__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEY_CR_FILTER__MASK;
|
||||
return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2__MASK;
|
||||
}
|
||||
#define MDP5_PIPE_SCALE_CONFIG_SCALEX_MAX_FILTER__MASK 0x00030000
|
||||
#define MDP5_PIPE_SCALE_CONFIG_SCALEX_MAX_FILTER__SHIFT 16
|
||||
static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_MAX_FILTER(enum mdp5_scale_filter val)
|
||||
#define MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3__MASK 0x00030000
|
||||
#define MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3__SHIFT 16
|
||||
static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3(enum mdp5_scale_filter val)
|
||||
{
|
||||
return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEX_MAX_FILTER__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEX_MAX_FILTER__MASK;
|
||||
return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3__MASK;
|
||||
}
|
||||
#define MDP5_PIPE_SCALE_CONFIG_SCALEY_MAX_FILTER__MASK 0x000c0000
|
||||
#define MDP5_PIPE_SCALE_CONFIG_SCALEY_MAX_FILTER__SHIFT 18
|
||||
static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_MAX_FILTER(enum mdp5_scale_filter val)
|
||||
#define MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3__MASK 0x000c0000
|
||||
#define MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3__SHIFT 18
|
||||
static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3(enum mdp5_scale_filter val)
|
||||
{
|
||||
return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEY_MAX_FILTER__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEY_MAX_FILTER__MASK;
|
||||
return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3__MASK;
|
||||
}
|
||||
|
||||
static inline uint32_t REG_MDP5_PIPE_SCALE_PHASE_STEP_X(enum mdp5_pipe i0) { return 0x00000210 + __offset_PIPE(i0); }
|
||||
|
@ -984,9 +1022,22 @@ static inline uint32_t REG_MDP5_LM_BORDER_COLOR_0(uint32_t i0) { return 0x000000
|
|||
|
||||
static inline uint32_t REG_MDP5_LM_BORDER_COLOR_1(uint32_t i0) { return 0x00000010 + __offset_LM(i0); }
|
||||
|
||||
static inline uint32_t REG_MDP5_LM_BLEND(uint32_t i0, uint32_t i1) { return 0x00000020 + __offset_LM(i0) + 0x30*i1; }
|
||||
static inline uint32_t __offset_BLEND(uint32_t idx)
|
||||
{
|
||||
switch (idx) {
|
||||
case 0: return 0x00000020;
|
||||
case 1: return 0x00000050;
|
||||
case 2: return 0x00000080;
|
||||
case 3: return 0x000000b0;
|
||||
case 4: return 0x00000230;
|
||||
case 5: return 0x00000260;
|
||||
case 6: return 0x00000290;
|
||||
default: return INVALID_IDX(idx);
|
||||
}
|
||||
}
|
||||
static inline uint32_t REG_MDP5_LM_BLEND(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_LM(i0) + __offset_BLEND(i1); }
|
||||
|
||||
static inline uint32_t REG_MDP5_LM_BLEND_OP_MODE(uint32_t i0, uint32_t i1) { return 0x00000020 + __offset_LM(i0) + 0x30*i1; }
|
||||
static inline uint32_t REG_MDP5_LM_BLEND_OP_MODE(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_LM(i0) + __offset_BLEND(i1); }
|
||||
#define MDP5_LM_BLEND_OP_MODE_FG_ALPHA__MASK 0x00000003
|
||||
#define MDP5_LM_BLEND_OP_MODE_FG_ALPHA__SHIFT 0
|
||||
static inline uint32_t MDP5_LM_BLEND_OP_MODE_FG_ALPHA(enum mdp_alpha_type val)
|
||||
|
@ -1008,25 +1059,25 @@ static inline uint32_t MDP5_LM_BLEND_OP_MODE_BG_ALPHA(enum mdp_alpha_type val)
|
|||
#define MDP5_LM_BLEND_OP_MODE_BG_INV_MOD_ALPHA 0x00001000
|
||||
#define MDP5_LM_BLEND_OP_MODE_BG_TRANSP_EN 0x00002000
|
||||
|
||||
static inline uint32_t REG_MDP5_LM_BLEND_FG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000024 + __offset_LM(i0) + 0x30*i1; }
|
||||
static inline uint32_t REG_MDP5_LM_BLEND_FG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000004 + __offset_LM(i0) + __offset_BLEND(i1); }
|
||||
|
||||
static inline uint32_t REG_MDP5_LM_BLEND_BG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000028 + __offset_LM(i0) + 0x30*i1; }
|
||||
static inline uint32_t REG_MDP5_LM_BLEND_BG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000008 + __offset_LM(i0) + __offset_BLEND(i1); }
|
||||
|
||||
static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000002c + __offset_LM(i0) + 0x30*i1; }
|
||||
static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000000c + __offset_LM(i0) + __offset_BLEND(i1); }
|
||||
|
||||
static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00000030 + __offset_LM(i0) + 0x30*i1; }
|
||||
static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00000010 + __offset_LM(i0) + __offset_BLEND(i1); }
|
||||
|
||||
static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000034 + __offset_LM(i0) + 0x30*i1; }
|
||||
static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000014 + __offset_LM(i0) + __offset_BLEND(i1); }
|
||||
|
||||
static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000038 + __offset_LM(i0) + 0x30*i1; }
|
||||
static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000018 + __offset_LM(i0) + __offset_BLEND(i1); }
|
||||
|
||||
static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000003c + __offset_LM(i0) + 0x30*i1; }
|
||||
static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000001c + __offset_LM(i0) + __offset_BLEND(i1); }
|
||||
|
||||
static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00000040 + __offset_LM(i0) + 0x30*i1; }
|
||||
static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00000020 + __offset_LM(i0) + __offset_BLEND(i1); }
|
||||
|
||||
static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000044 + __offset_LM(i0) + 0x30*i1; }
|
||||
static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000024 + __offset_LM(i0) + __offset_BLEND(i1); }
|
||||
|
||||
static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000048 + __offset_LM(i0) + 0x30*i1; }
|
||||
static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000028 + __offset_LM(i0) + __offset_BLEND(i1); }
|
||||
|
||||
static inline uint32_t REG_MDP5_LM_CURSOR_IMG_SIZE(uint32_t i0) { return 0x000000e0 + __offset_LM(i0); }
|
||||
#define MDP5_LM_CURSOR_IMG_SIZE_SRC_W__MASK 0x0000ffff
|
||||
|
@ -1260,6 +1311,13 @@ static inline uint32_t REG_MDP5_PP_FBC_LOSSY_MODE(uint32_t i0) { return 0x000000
|
|||
static inline uint32_t __offset_WB(uint32_t idx)
|
||||
{
|
||||
switch (idx) {
|
||||
#if 0 /* TEMPORARY until patch that adds wb.base[] is merged */
|
||||
case 0: return (mdp5_cfg->wb.base[0]);
|
||||
case 1: return (mdp5_cfg->wb.base[1]);
|
||||
case 2: return (mdp5_cfg->wb.base[2]);
|
||||
case 3: return (mdp5_cfg->wb.base[3]);
|
||||
case 4: return (mdp5_cfg->wb.base[4]);
|
||||
#endif
|
||||
default: return INVALID_IDX(idx);
|
||||
}
|
||||
}
|
||||
|
|
|
@ -390,10 +390,10 @@ static uint32_t get_scalex_config(uint32_t src, uint32_t dest)
|
|||
|
||||
filter = (src <= dest) ? SCALE_FILTER_BIL : SCALE_FILTER_PCMN;
|
||||
|
||||
return MDP5_PIPE_SCALE_CONFIG_SCALEX_EN |
|
||||
MDP5_PIPE_SCALE_CONFIG_SCALEX_MIN_FILTER(filter) |
|
||||
MDP5_PIPE_SCALE_CONFIG_SCALEX_CR_FILTER(filter) |
|
||||
MDP5_PIPE_SCALE_CONFIG_SCALEX_MAX_FILTER(filter);
|
||||
return MDP5_PIPE_SCALE_CONFIG_SCALEX_EN |
|
||||
MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0(filter) |
|
||||
MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2(filter) |
|
||||
MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3(filter);
|
||||
}
|
||||
|
||||
static uint32_t get_scaley_config(uint32_t src, uint32_t dest)
|
||||
|
@ -402,10 +402,10 @@ static uint32_t get_scaley_config(uint32_t src, uint32_t dest)
|
|||
|
||||
filter = (src <= dest) ? SCALE_FILTER_BIL : SCALE_FILTER_PCMN;
|
||||
|
||||
return MDP5_PIPE_SCALE_CONFIG_SCALEY_EN |
|
||||
MDP5_PIPE_SCALE_CONFIG_SCALEY_MIN_FILTER(filter) |
|
||||
MDP5_PIPE_SCALE_CONFIG_SCALEY_CR_FILTER(filter) |
|
||||
MDP5_PIPE_SCALE_CONFIG_SCALEY_MAX_FILTER(filter);
|
||||
return MDP5_PIPE_SCALE_CONFIG_SCALEY_EN |
|
||||
MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0(filter) |
|
||||
MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2(filter) |
|
||||
MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3(filter);
|
||||
}
|
||||
|
||||
static int mdp5_plane_mode_set(struct drm_plane *plane,
|
||||
|
@ -516,7 +516,7 @@ static int mdp5_plane_mode_set(struct drm_plane *plane,
|
|||
MDP5_PIPE_SRC_FORMAT_CPP(format->cpp - 1) |
|
||||
MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT(format->unpack_count - 1) |
|
||||
COND(format->unpack_tight, MDP5_PIPE_SRC_FORMAT_UNPACK_TIGHT) |
|
||||
MDP5_PIPE_SRC_FORMAT_NUM_PLANES(format->fetch_type) |
|
||||
MDP5_PIPE_SRC_FORMAT_FETCH_TYPE(format->fetch_type) |
|
||||
MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP(format->chroma_sample));
|
||||
|
||||
mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_UNPACK(pipe),
|
||||
|
|
|
@ -8,17 +8,17 @@ This file was generated by the rules-ng-ng headergen tool in this git repository
|
|||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2014-12-05 15:34:49)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-03-24 22:05:22)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2352 bytes, from 2015-04-12 15:02:42)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 35083 bytes, from 2015-04-12 15:04:03)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 22094 bytes, from 2015-05-12 12:45:23)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2014-10-31 16:48:57)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29012 bytes, from 2015-05-12 12:45:23)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-12 12:45:23)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2576 bytes, from 2015-07-09 22:10:24)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 36021 bytes, from 2015-07-09 22:10:24)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 26057 bytes, from 2015-08-14 21:47:57)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2015-05-20 20:03:07)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29154 bytes, from 2015-08-10 21:25:43)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-20 20:03:14)
|
||||
|
||||
Copyright (C) 2013-2015 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
|
@ -46,7 +46,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
|||
|
||||
|
||||
enum mdp_chroma_samp_type {
|
||||
CHROMA_RGB = 0,
|
||||
CHROMA_FULL = 0,
|
||||
CHROMA_H2V1 = 1,
|
||||
CHROMA_H1V2 = 2,
|
||||
CHROMA_420 = 3,
|
||||
|
@ -65,6 +65,10 @@ enum mdp_mixer_stage_id {
|
|||
STAGE1 = 3,
|
||||
STAGE2 = 4,
|
||||
STAGE3 = 5,
|
||||
STAGE4 = 6,
|
||||
STAGE5 = 7,
|
||||
STAGE6 = 8,
|
||||
STAGE_MAX = 8,
|
||||
};
|
||||
|
||||
enum mdp_alpha_type {
|
||||
|
|
|
@ -95,23 +95,23 @@ static struct csc_cfg csc_convert[CSC_MAX] = {
|
|||
static const struct mdp_format formats[] = {
|
||||
/* name a r g b e0 e1 e2 e3 alpha tight cpp cnt ... */
|
||||
FMT(ARGB8888, 8, 8, 8, 8, 1, 0, 2, 3, true, true, 4, 4,
|
||||
MDP_PLANE_INTERLEAVED, CHROMA_RGB),
|
||||
MDP_PLANE_INTERLEAVED, CHROMA_FULL),
|
||||
FMT(ABGR8888, 8, 8, 8, 8, 2, 0, 1, 3, true, true, 4, 4,
|
||||
MDP_PLANE_INTERLEAVED, CHROMA_RGB),
|
||||
MDP_PLANE_INTERLEAVED, CHROMA_FULL),
|
||||
FMT(RGBA8888, 8, 8, 8, 8, 3, 1, 0, 2, true, true, 4, 4,
|
||||
MDP_PLANE_INTERLEAVED, CHROMA_RGB),
|
||||
MDP_PLANE_INTERLEAVED, CHROMA_FULL),
|
||||
FMT(BGRA8888, 8, 8, 8, 8, 3, 2, 0, 1, true, true, 4, 4,
|
||||
MDP_PLANE_INTERLEAVED, CHROMA_RGB),
|
||||
MDP_PLANE_INTERLEAVED, CHROMA_FULL),
|
||||
FMT(XRGB8888, 8, 8, 8, 8, 1, 0, 2, 3, false, true, 4, 4,
|
||||
MDP_PLANE_INTERLEAVED, CHROMA_RGB),
|
||||
MDP_PLANE_INTERLEAVED, CHROMA_FULL),
|
||||
FMT(RGB888, 0, 8, 8, 8, 1, 0, 2, 0, false, true, 3, 3,
|
||||
MDP_PLANE_INTERLEAVED, CHROMA_RGB),
|
||||
MDP_PLANE_INTERLEAVED, CHROMA_FULL),
|
||||
FMT(BGR888, 0, 8, 8, 8, 2, 0, 1, 0, false, true, 3, 3,
|
||||
MDP_PLANE_INTERLEAVED, CHROMA_RGB),
|
||||
MDP_PLANE_INTERLEAVED, CHROMA_FULL),
|
||||
FMT(RGB565, 0, 5, 6, 5, 1, 0, 2, 0, false, true, 2, 3,
|
||||
MDP_PLANE_INTERLEAVED, CHROMA_RGB),
|
||||
MDP_PLANE_INTERLEAVED, CHROMA_FULL),
|
||||
FMT(BGR565, 0, 5, 6, 5, 2, 0, 1, 0, false, true, 2, 3,
|
||||
MDP_PLANE_INTERLEAVED, CHROMA_RGB),
|
||||
MDP_PLANE_INTERLEAVED, CHROMA_FULL),
|
||||
|
||||
/* --- RGB formats above / YUV formats below this line --- */
|
||||
|
||||
|
|
|
@ -92,7 +92,7 @@ struct mdp_format {
|
|||
enum mdp_chroma_samp_type chroma_sample;
|
||||
};
|
||||
#define to_mdp_format(x) container_of(x, struct mdp_format, base)
|
||||
#define MDP_FORMAT_IS_YUV(mdp_format) ((mdp_format)->chroma_sample > CHROMA_RGB)
|
||||
#define MDP_FORMAT_IS_YUV(mdp_format) ((mdp_format)->chroma_sample > CHROMA_FULL)
|
||||
|
||||
uint32_t mdp_get_formats(uint32_t *formats, uint32_t max_formats, bool rgb_only);
|
||||
const struct msm_format *mdp_get_format(struct msm_kms *kms, uint32_t format);
|
||||
|
|
Loading…
Reference in a new issue