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mtd: rawnand: stm32_fmc2: remove useless inline comments
Remove inline comments that are useless since function label are self explanatory. Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/1588756279-17289-3-git-send-email-christophe.kerello@st.com
This commit is contained in:
Christophe Kerello
Miquel Raynal
parent
71d1f1d595
commit
2d3d54bf12
1 changed files with 0 additions and 40 deletions
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@ -281,7 +281,6 @@ static inline struct stm32_fmc2_nfc *to_stm32_nfc(struct nand_controller *base)
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return container_of(base, struct stm32_fmc2_nfc, base);
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}
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/* Timings configuration */
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static void stm32_fmc2_timings_init(struct nand_chip *chip)
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{
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struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
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@ -313,7 +312,6 @@ static void stm32_fmc2_timings_init(struct nand_chip *chip)
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writel_relaxed(patt, fmc2->io_base + FMC2_PATT);
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}
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/* Controller configuration */
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static void stm32_fmc2_setup(struct nand_chip *chip)
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{
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struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
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@ -341,7 +339,6 @@ static void stm32_fmc2_setup(struct nand_chip *chip)
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writel_relaxed(pcr, fmc2->io_base + FMC2_PCR);
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}
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/* Select target */
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static int stm32_fmc2_select_chip(struct nand_chip *chip, int chipnr)
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{
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struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
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@ -353,11 +350,7 @@ static int stm32_fmc2_select_chip(struct nand_chip *chip, int chipnr)
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return 0;
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fmc2->cs_sel = nand->cs_used[chipnr];
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/* FMC2 setup routine */
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stm32_fmc2_setup(chip);
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/* Apply timings */
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stm32_fmc2_timings_init(chip);
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if (fmc2->dma_tx_ch && fmc2->dma_rx_ch) {
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@ -407,7 +400,6 @@ static int stm32_fmc2_select_chip(struct nand_chip *chip, int chipnr)
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return 0;
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}
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/* Set bus width to 16-bit or 8-bit */
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static void stm32_fmc2_set_buswidth_16(struct stm32_fmc2_nfc *fmc2, bool set)
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{
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u32 pcr = readl_relaxed(fmc2->io_base + FMC2_PCR);
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@ -418,7 +410,6 @@ static void stm32_fmc2_set_buswidth_16(struct stm32_fmc2_nfc *fmc2, bool set)
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writel_relaxed(pcr, fmc2->io_base + FMC2_PCR);
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}
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/* Enable/disable ECC */
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static void stm32_fmc2_set_ecc(struct stm32_fmc2_nfc *fmc2, bool enable)
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{
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u32 pcr = readl(fmc2->io_base + FMC2_PCR);
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@ -429,7 +420,6 @@ static void stm32_fmc2_set_ecc(struct stm32_fmc2_nfc *fmc2, bool enable)
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writel(pcr, fmc2->io_base + FMC2_PCR);
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}
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/* Enable irq sources in case of the sequencer is used */
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static inline void stm32_fmc2_enable_seq_irq(struct stm32_fmc2_nfc *fmc2)
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{
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u32 csqier = readl_relaxed(fmc2->io_base + FMC2_CSQIER);
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@ -441,7 +431,6 @@ static inline void stm32_fmc2_enable_seq_irq(struct stm32_fmc2_nfc *fmc2)
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writel_relaxed(csqier, fmc2->io_base + FMC2_CSQIER);
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}
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/* Disable irq sources in case of the sequencer is used */
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static inline void stm32_fmc2_disable_seq_irq(struct stm32_fmc2_nfc *fmc2)
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{
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u32 csqier = readl_relaxed(fmc2->io_base + FMC2_CSQIER);
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@ -453,13 +442,11 @@ static inline void stm32_fmc2_disable_seq_irq(struct stm32_fmc2_nfc *fmc2)
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fmc2->irq_state = FMC2_IRQ_UNKNOWN;
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}
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/* Clear irq sources in case of the sequencer is used */
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static inline void stm32_fmc2_clear_seq_irq(struct stm32_fmc2_nfc *fmc2)
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{
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writel_relaxed(FMC2_CSQICR_CLEAR_IRQ, fmc2->io_base + FMC2_CSQICR);
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}
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/* Enable irq sources in case of bch is used */
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static inline void stm32_fmc2_enable_bch_irq(struct stm32_fmc2_nfc *fmc2,
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int mode)
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{
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@ -475,7 +462,6 @@ static inline void stm32_fmc2_enable_bch_irq(struct stm32_fmc2_nfc *fmc2,
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writel_relaxed(bchier, fmc2->io_base + FMC2_BCHIER);
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}
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/* Disable irq sources in case of bch is used */
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static inline void stm32_fmc2_disable_bch_irq(struct stm32_fmc2_nfc *fmc2)
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{
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u32 bchier = readl_relaxed(fmc2->io_base + FMC2_BCHIER);
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@ -488,7 +474,6 @@ static inline void stm32_fmc2_disable_bch_irq(struct stm32_fmc2_nfc *fmc2)
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fmc2->irq_state = FMC2_IRQ_UNKNOWN;
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}
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/* Clear irq sources in case of bch is used */
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static inline void stm32_fmc2_clear_bch_irq(struct stm32_fmc2_nfc *fmc2)
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{
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writel_relaxed(FMC2_BCHICR_CLEAR_IRQ, fmc2->io_base + FMC2_BCHICR);
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@ -549,10 +534,7 @@ static int stm32_fmc2_ham_calculate(struct nand_chip *chip, const u8 *data,
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}
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heccr = readl_relaxed(fmc2->io_base + FMC2_HECCR);
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stm32_fmc2_ham_set_ecc(heccr, ecc);
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/* Disable ECC */
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stm32_fmc2_set_ecc(fmc2, false);
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return 0;
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@ -654,13 +636,11 @@ static int stm32_fmc2_bch_calculate(struct nand_chip *chip, const u8 *data,
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ecc[12] = bchpbr;
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}
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/* Disable ECC */
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stm32_fmc2_set_ecc(fmc2, false);
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return 0;
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}
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/* BCH algorithm correction */
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static int stm32_fmc2_bch_decode(int eccsize, u8 *dat, u32 *ecc_sta)
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{
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u32 bchdsr0 = ecc_sta[0];
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@ -720,7 +700,6 @@ static int stm32_fmc2_bch_correct(struct nand_chip *chip, u8 *dat,
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ecc_sta[3] = readl_relaxed(fmc2->io_base + FMC2_BCHDSR3);
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ecc_sta[4] = readl_relaxed(fmc2->io_base + FMC2_BCHDSR4);
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/* Disable ECC */
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stm32_fmc2_set_ecc(fmc2, false);
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return stm32_fmc2_bch_decode(chip->ecc.size, dat, ecc_sta);
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@ -1054,7 +1033,6 @@ static int stm32_fmc2_sequencer_write_page(struct nand_chip *chip,
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{
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int ret;
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/* Select the target */
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ret = stm32_fmc2_select_chip(chip, chip->cur_cs);
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if (ret)
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return ret;
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@ -1069,7 +1047,6 @@ static int stm32_fmc2_sequencer_write_page_raw(struct nand_chip *chip,
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{
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int ret;
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/* Select the target */
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ret = stm32_fmc2_select_chip(chip, chip->cur_cs);
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if (ret)
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return ret;
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@ -1153,7 +1130,6 @@ static int stm32_fmc2_sequencer_read_page(struct nand_chip *chip, u8 *buf,
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u16 sta_map;
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int ret;
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/* Select the target */
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ret = stm32_fmc2_select_chip(chip, chip->cur_cs);
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if (ret)
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return ret;
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@ -1199,7 +1175,6 @@ static int stm32_fmc2_sequencer_read_page_raw(struct nand_chip *chip, u8 *buf,
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struct mtd_info *mtd = nand_to_mtd(chip);
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int ret;
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/* Select the target */
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ret = stm32_fmc2_select_chip(chip, chip->cur_cs);
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if (ret)
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return ret;
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@ -1409,7 +1384,6 @@ static int stm32_fmc2_exec_op(struct nand_chip *chip,
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return ret;
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}
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/* Controller initialization */
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static void stm32_fmc2_init(struct stm32_fmc2_nfc *fmc2)
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{
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u32 pcr = readl_relaxed(fmc2->io_base + FMC2_PCR);
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@ -1452,7 +1426,6 @@ static void stm32_fmc2_init(struct stm32_fmc2_nfc *fmc2)
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writel_relaxed(FMC2_PATT_DEFAULT, fmc2->io_base + FMC2_PATT);
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}
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/* Controller timings */
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static void stm32_fmc2_calc_timings(struct nand_chip *chip,
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const struct nand_sdr_timings *sdrt)
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{
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@ -1596,14 +1569,11 @@ static int stm32_fmc2_setup_interface(struct nand_chip *chip, int chipnr,
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return 0;
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stm32_fmc2_calc_timings(chip, sdrt);
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/* Apply timings */
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stm32_fmc2_timings_init(chip);
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return 0;
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}
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/* DMA configuration */
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static int stm32_fmc2_dma_setup(struct stm32_fmc2_nfc *fmc2)
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{
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int ret = 0;
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@ -1667,7 +1637,6 @@ static int stm32_fmc2_dma_setup(struct stm32_fmc2_nfc *fmc2)
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return ret;
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}
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/* NAND callbacks setup */
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static void stm32_fmc2_nand_callbacks_setup(struct nand_chip *chip)
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{
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struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
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@ -1708,7 +1677,6 @@ static void stm32_fmc2_nand_callbacks_setup(struct nand_chip *chip)
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chip->ecc.bytes = chip->options & NAND_BUSWIDTH_16 ? 8 : 7;
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}
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/* FMC2 layout */
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static int stm32_fmc2_nand_ooblayout_ecc(struct mtd_info *mtd, int section,
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struct mtd_oob_region *oobregion)
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{
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@ -1744,7 +1712,6 @@ static const struct mtd_ooblayout_ops stm32_fmc2_nand_ooblayout_ops = {
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.free = stm32_fmc2_nand_ooblayout_free,
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};
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/* FMC2 caps */
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static int stm32_fmc2_calc_ecc_bytes(int step_size, int strength)
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{
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/* Hamming */
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@ -1763,7 +1730,6 @@ NAND_ECC_CAPS_SINGLE(stm32_fmc2_ecc_caps, stm32_fmc2_calc_ecc_bytes,
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FMC2_ECC_STEP_SIZE,
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FMC2_ECC_HAM, FMC2_ECC_BCH4, FMC2_ECC_BCH8);
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/* FMC2 controller ops */
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static int stm32_fmc2_attach_chip(struct nand_chip *chip)
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{
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struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
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@ -1797,13 +1763,10 @@ static int stm32_fmc2_attach_chip(struct nand_chip *chip)
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if (chip->bbt_options & NAND_BBT_USE_FLASH)
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chip->bbt_options |= NAND_BBT_NO_OOB;
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/* NAND callbacks setup */
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stm32_fmc2_nand_callbacks_setup(chip);
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/* Define ECC layout */
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mtd_set_ooblayout(mtd, &stm32_fmc2_nand_ooblayout_ops);
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/* Configure bus width to 16-bit */
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if (chip->options & NAND_BUSWIDTH_16)
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stm32_fmc2_set_buswidth_16(fmc2, true);
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@ -1816,7 +1779,6 @@ static const struct nand_controller_ops stm32_fmc2_nand_controller_ops = {
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.setup_data_interface = stm32_fmc2_setup_interface,
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};
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/* FMC2 probe */
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static int stm32_fmc2_parse_child(struct stm32_fmc2_nfc *fmc2,
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struct device_node *dn)
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{
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@ -1976,12 +1938,10 @@ static int stm32_fmc2_probe(struct platform_device *pdev)
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reset_control_deassert(rstc);
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}
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/* DMA setup */
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ret = stm32_fmc2_dma_setup(fmc2);
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if (ret)
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goto err_release_dma;
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/* FMC2 init routine */
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stm32_fmc2_init(fmc2);
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nand = &fmc2->nand;
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