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clk: imx: remove clk_count of imx_register_uart_clocks
The clk count has been get with of_clk_get_parent_count, there is no need to pass clk_count from users. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230104110032.1220721-4-peng.fan@oss.nxp.com
This commit is contained in:
parent
8658f0acc8
commit
2d5513bf75
17 changed files with 21 additions and 21 deletions
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@ -218,7 +218,7 @@ static int __init __mx25_clocks_init(void __iomem *ccm_base)
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*/
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clk_set_parent(clk[cko_sel], clk[ipg]);
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imx_register_uart_clocks(6);
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imx_register_uart_clocks();
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return 0;
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}
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@ -165,7 +165,7 @@ static void __init _mx27_clocks_init(unsigned long fref)
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clk_prepare_enable(clk[IMX27_CLK_EMI_AHB_GATE]);
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imx_register_uart_clocks(7);
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imx_register_uart_clocks();
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imx_print_silicon_rev("i.MX27", mx27_revision());
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}
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@ -235,7 +235,7 @@ static void __init _mx35_clocks_init(void)
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*/
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clk_prepare_enable(clk[scc_gate]);
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imx_register_uart_clocks(4);
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imx_register_uart_clocks();
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imx_print_silicon_rev("i.MX35", mx35_revision());
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}
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@ -358,7 +358,7 @@ static void __init mx50_clocks_init(struct device_node *np)
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r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000);
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clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r);
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imx_register_uart_clocks(5);
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imx_register_uart_clocks();
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}
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CLK_OF_DECLARE(imx50_ccm, "fsl,imx50-ccm", mx50_clocks_init);
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@ -464,7 +464,7 @@ static void __init mx51_clocks_init(struct device_node *np)
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val |= 1 << 23;
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writel(val, MXC_CCM_CLPCR);
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imx_register_uart_clocks(3);
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imx_register_uart_clocks();
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}
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CLK_OF_DECLARE(imx51_ccm, "fsl,imx51-ccm", mx51_clocks_init);
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@ -609,6 +609,6 @@ static void __init mx53_clocks_init(struct device_node *np)
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r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000);
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clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r);
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imx_register_uart_clocks(5);
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imx_register_uart_clocks();
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}
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CLK_OF_DECLARE(imx53_ccm, "fsl,imx53-ccm", mx53_clocks_init);
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@ -974,6 +974,6 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
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hws[IMX6QDL_CLK_PLL3_USB_OTG]->clk);
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}
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imx_register_uart_clocks(2);
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imx_register_uart_clocks();
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}
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CLK_OF_DECLARE(imx6q, "fsl,imx6q-ccm", imx6q_clocks_init);
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@ -440,6 +440,6 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
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clk_set_parent(hws[IMX6SL_CLK_LCDIF_AXI_SEL]->clk,
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hws[IMX6SL_CLK_PLL2_PFD2]->clk);
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imx_register_uart_clocks(2);
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imx_register_uart_clocks();
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}
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CLK_OF_DECLARE(imx6sl, "fsl,imx6sl-ccm", imx6sl_clocks_init);
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@ -340,7 +340,7 @@ static void __init imx6sll_clocks_init(struct device_node *ccm_node)
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of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data);
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imx_register_uart_clocks(5);
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imx_register_uart_clocks();
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/* Lower the AHB clock rate before changing the clock source. */
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clk_set_rate(hws[IMX6SLL_CLK_AHB]->clk, 99000000);
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@ -548,6 +548,6 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
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clk_set_parent(hws[IMX6SX_CLK_QSPI1_SEL]->clk, hws[IMX6SX_CLK_PLL2_BUS]->clk);
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clk_set_parent(hws[IMX6SX_CLK_QSPI2_SEL]->clk, hws[IMX6SX_CLK_PLL2_BUS]->clk);
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imx_register_uart_clocks(2);
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imx_register_uart_clocks();
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}
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CLK_OF_DECLARE(imx6sx, "fsl,imx6sx-ccm", imx6sx_clocks_init);
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@ -882,7 +882,7 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
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hws[IMX7D_USB1_MAIN_480M_CLK] = imx_clk_hw_fixed_factor("pll_usb1_main_clk", "osc", 20, 1);
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hws[IMX7D_USB_MAIN_480M_CLK] = imx_clk_hw_fixed_factor("pll_usb_main_clk", "osc", 20, 1);
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imx_register_uart_clocks(7);
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imx_register_uart_clocks();
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}
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CLK_OF_DECLARE(imx7d, "fsl,imx7d-ccm", imx7d_clocks_init);
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@ -176,7 +176,7 @@ static void __init imx7ulp_clk_pcc2_init(struct device_node *np)
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of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
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imx_register_uart_clocks(2);
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imx_register_uart_clocks();
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}
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CLK_OF_DECLARE(imx7ulp_clk_pcc2, "fsl,imx7ulp-pcc2", imx7ulp_clk_pcc2_init);
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@ -223,7 +223,7 @@ static void __init imx7ulp_clk_pcc3_init(struct device_node *np)
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of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
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imx_register_uart_clocks(7);
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imx_register_uart_clocks();
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}
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CLK_OF_DECLARE(imx7ulp_clk_pcc3, "fsl,imx7ulp-pcc3", imx7ulp_clk_pcc3_init);
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@ -609,7 +609,7 @@ static int imx8mm_clocks_probe(struct platform_device *pdev)
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goto unregister_hws;
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}
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imx_register_uart_clocks(4);
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imx_register_uart_clocks();
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return 0;
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@ -602,7 +602,7 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)
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goto unregister_hws;
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}
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imx_register_uart_clocks(4);
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imx_register_uart_clocks();
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return 0;
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@ -723,7 +723,7 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
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of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data);
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imx_register_uart_clocks(4);
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imx_register_uart_clocks();
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return 0;
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}
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@ -601,7 +601,7 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
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goto unregister_hws;
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}
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imx_register_uart_clocks(4);
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imx_register_uart_clocks();
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return 0;
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@ -385,7 +385,7 @@ static int imx8ulp_clk_pcc3_init(struct platform_device *pdev)
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if (ret)
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return ret;
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imx_register_uart_clocks(1);
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imx_register_uart_clocks();
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/* register the pcc3 reset controller */
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return imx8ulp_pcc_reset_init(pdev, base, pcc3_resets, ARRAY_SIZE(pcc3_resets));
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@ -165,7 +165,7 @@ __setup_param("earlycon", imx_keep_uart_earlycon,
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__setup_param("earlyprintk", imx_keep_uart_earlyprintk,
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imx_keep_uart_clocks_param, 0);
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void imx_register_uart_clocks(unsigned int clk_count)
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void imx_register_uart_clocks(void)
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{
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unsigned int num __maybe_unused;
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@ -12,9 +12,9 @@ extern bool mcore_booted;
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void imx_check_clocks(struct clk *clks[], unsigned int count);
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void imx_check_clk_hws(struct clk_hw *clks[], unsigned int count);
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#ifndef MODULE
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void imx_register_uart_clocks(unsigned int clk_count);
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void imx_register_uart_clocks(void);
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#else
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static inline void imx_register_uart_clocks(unsigned int clk_count)
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static inline void imx_register_uart_clocks(void)
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{
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}
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#endif
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