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Qualcomm ARM64 updates for v6.8 

Support is added for the new Snapdragon 8 Gen 3 mobile platform, with
 support for the MTP and QRD development devices, the new Snapdragon X
 Elite compute platform with QCP and CRD development/references devices,
 the QCS6590/QCM6490 platform with support for the IDP development device
 and the Robotics RB3gen2 board, the Huawei Honor 5X/GR5 handset
 built on MSM8939, and Xiaomi Pad 6 on SM8250.
 
 On IPQ5018 and IPQ6018 platform support for CPUfreq, USB, and one
 additional QUP SPI controller is added.
 
 CPU OPP tables are selectively enabled based on fuses, for both IPQ5332
 and IPQ6018. IPQ6018 gains description of a few more SPI and UART nodes.
 
 Common elements of the IPQ9574 RDP boards are refactored into a common
 include file. IPQ9574 also gains description of its LEDs and WPS
 busttons.
 
 MSM8916 finally gets the DSP-based audio described, and this is enabled
 for a variety of boards. Acer Iconia Talk S and Loncheer L8910 gains
 notification LED, battery and charger support is added to Loncheer
 L8150, and GPU is enabled for Samsung Galaxy Tab A.
 
 Similariy DSP-based audio is added on MSM8939, the BAM-DMUX support is
 enabled as well. The Longcheer L9100 gains RGB notification LED support,
 and the wireless subsystem is enabled.
 
 Missing SPI controllers are described on MSM8953. On MSM8996 the MPM is
 enabled, to allow using wakeup interrupts. Interconnect providers, MPM
 and display are added to QCM2290.
 
 UFS, remoteprocs and WiFi is enabled for Fairphone FP5.
 On Fairphone FP3 audio, WiFi and Bluetooth are enabled.
 
 On the Robotics RB1, HDMI and the CAN bus controller are added. On
 Robotics RB2 Bluetooth, the modem remoteproc and WiFi are enabled.
 Bluetooth is enabled on the Robotics RB5.
 
 On SA8775P tsens and thermal is added, as well as the random number
 generator.
 
 Sound and RTC support is added for the Acer Aspire 1.
 
 On SC7280 DeviceTree is refactored, in order to allow non-Chrome devices
 to inherit the base dtsi. Support for UFS, crypto, TrustZone based
 remoteprocs, the Camera Control Interface (CCI) and random number
 generator support are added. Additionally a variety of smaller fixes are
 introduced.
 
 A variety of fixes are introduced for SC8180X, in particular missing
 power-domains and interconnects.
 
 On SC8280XP the camera clock controller is added, and a number of
 smaller fixes are introduced.
 
 The display subsystem in SDM670 is described.
 
 On SDX75 interconnect providers are added, as is USB3 and the related
 PHY, which is then enabled on the IDP device.
 
 On SM6115 interconnect providers are added and existing clients are
 wired up. A UART controller is added as well.
 
 The MPM is added, to provide wakeup interrutps, on SM6375. The modem
 subsystem, and WiFi are enabled on Sony Xperia 10 IV, a few regulator
 supplies are corrected.
 
 On SM8150 the DisplayPort controller is added, for USB Type-C output,
 which together with the addition of HDMI is described on the HDK board.
 
 GPU and random number generator support are added to SM8450, and enabled
 on the HDK board.
 
 On SM8550 GPU, IPA, random number generator, missing SoundWire ports are
 added, and enabled on both MTP and QRD devices.
 
 Additionally a large number of smaller functional and DeviceTree binding
 validation issues are corrected across a variety of platforms.
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Merge tag 'qcom-arm64-for-6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt

Qualcomm ARM64 updates for v6.8

Support is added for the new Snapdragon 8 Gen 3 mobile platform, with
support for the MTP and QRD development devices, the new Snapdragon X
Elite compute platform with QCP and CRD development/references devices,
the QCS6590/QCM6490 platform with support for the IDP development device
and the Robotics RB3gen2 board, the Huawei Honor 5X/GR5 handset
built on MSM8939, and Xiaomi Pad 6 on SM8250.

On IPQ5018 and IPQ6018 platform support for CPUfreq, USB, and one
additional QUP SPI controller is added.

CPU OPP tables are selectively enabled based on fuses, for both IPQ5332
and IPQ6018. IPQ6018 gains description of a few more SPI and UART nodes.

Common elements of the IPQ9574 RDP boards are refactored into a common
include file. IPQ9574 also gains description of its LEDs and WPS
busttons.

MSM8916 finally gets the DSP-based audio described, and this is enabled
for a variety of boards. Acer Iconia Talk S and Loncheer L8910 gains
notification LED, battery and charger support is added to Loncheer
L8150, and GPU is enabled for Samsung Galaxy Tab A.

Similariy DSP-based audio is added on MSM8939, the BAM-DMUX support is
enabled as well. The Longcheer L9100 gains RGB notification LED support,
and the wireless subsystem is enabled.

Missing SPI controllers are described on MSM8953. On MSM8996 the MPM is
enabled, to allow using wakeup interrupts. Interconnect providers, MPM
and display are added to QCM2290.

UFS, remoteprocs and WiFi is enabled for Fairphone FP5.
On Fairphone FP3 audio, WiFi and Bluetooth are enabled.

On the Robotics RB1, HDMI and the CAN bus controller are added. On
Robotics RB2 Bluetooth, the modem remoteproc and WiFi are enabled.
Bluetooth is enabled on the Robotics RB5.

On SA8775P tsens and thermal is added, as well as the random number
generator.

Sound and RTC support is added for the Acer Aspire 1.

On SC7280 DeviceTree is refactored, in order to allow non-Chrome devices
to inherit the base dtsi. Support for UFS, crypto, TrustZone based
remoteprocs, the Camera Control Interface (CCI) and random number
generator support are added. Additionally a variety of smaller fixes are
introduced.

A variety of fixes are introduced for SC8180X, in particular missing
power-domains and interconnects.

On SC8280XP the camera clock controller is added, and a number of
smaller fixes are introduced.

The display subsystem in SDM670 is described.

On SDX75 interconnect providers are added, as is USB3 and the related
PHY, which is then enabled on the IDP device.

On SM6115 interconnect providers are added and existing clients are
wired up. A UART controller is added as well.

The MPM is added, to provide wakeup interrutps, on SM6375. The modem
subsystem, and WiFi are enabled on Sony Xperia 10 IV, a few regulator
supplies are corrected.

On SM8150 the DisplayPort controller is added, for USB Type-C output,
which together with the addition of HDMI is described on the HDK board.

GPU and random number generator support are added to SM8450, and enabled
on the HDK board.

On SM8550 GPU, IPA, random number generator, missing SoundWire ports are
added, and enabled on both MTP and QRD devices.

Additionally a large number of smaller functional and DeviceTree binding
validation issues are corrected across a variety of platforms.

* tag 'qcom-arm64-for-6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (288 commits)
  arm64: dts: qcom: sc8180x-primus: Allow UFS regulators load/mode setting
  arm64: dts: qcom: sc8180x: Describe the GIC redistributor
  arm64: dts: qcom: sc8180x: Add interconnects to UFS
  arm64: dts: qcom: sc8180x: Add missing MDP clocks
  arm64: dts: qcom: sc8180x: Add UFS GDSC
  arm64: dts: qcom: sc7280*: move MPSS and WPSS memory to dtsi
  arm64: dts: qcom: sc7280: Rename reserved-memory nodes
  arm64: dts: qcom: sc7280: Remove unused second MPSS reg
  arm64: dts: qcom: sdm670: add display subsystem
  arm64: dts: qcom: sm8150-hdk: enable DisplayPort and USB-C altmode
  arm64: dts: qcom: sm8150: add USB-C ports to the OTG USB host
  arm64: dts: qcom: sm8150: add USB-C ports to the USB+DP QMP PHY
  arm64: dts: qcom: sm8150: add DisplayPort controller
  arm64: dts: qcom: sm8150-hdk: fix SS USB regulators
  arm64: dts: qcom: sm8150-hdk: enable HDMI output
  arm64: dts: qcom: sm8150: make dispcc cast minimal vote on MMCX
  arm64: dts: qcom: sm8650: add fastrpc-compute-cb nodes
  arm64: dts: qcom: sm8550-qrd: add PM8010 regulators
  arm64: dts: qcom: sm8550-mtp: Add pm8010 regulators
  arm64: dts: qcom: qcm2290: Hook up MPM
  ...

Link: https://lore.kernel.org/r/20231219145402.874161-1-andersson@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2023-12-22 11:45:14 +00:00
parent dd93766396 b7b9a6aa7a
commit 2d7123c7e1
146 changed files with 23561 additions and 1253 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
Documentation/devicetree/bindings/arm/cpus.yaml
View File

@ -198,6 +198,7 @@ properties:
- qcom,kryo660
- qcom,kryo685
- qcom,kryo780
- qcom,oryon
- qcom,scorpion
enable-method:

16
Documentation/devicetree/bindings/arm/qcom-soc.yaml
View File

@ -23,7 +23,7 @@ description: |
select:
properties:
compatible:
pattern: "^qcom,.*(apq|ipq|mdm|msm|qcm|qcs|sa|sc|sdm|sdx|sm)[0-9]+.*$"
pattern: "^qcom,.*(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1e)[0-9]+.*$"
required:
- compatible
@ -31,17 +31,17 @@ properties:
compatible:
oneOf:
# Preferred naming style for compatibles of SoC components:
- pattern: "^qcom,(apq|ipq|mdm|msm|qcm|qcs|sa|sc|sdm|sdx|sm)[0-9]+(pro)?-.*$"
- pattern: "^qcom,(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1e)[0-9]+(pro)?-.*$"
- pattern: "^qcom,(sa|sc)8[0-9]+[a-z][a-z]?-.*$"
# Legacy namings - variations of existing patterns/compatibles are OK,
# but do not add completely new entries to these:
- pattern: "^qcom,[ak]pss-wdt-(apq|ipq|mdm|msm|qcm|qcs|sa|sc|sdm|sdx|sm)[0-9]+.*$"
- pattern: "^qcom,gcc-(apq|ipq|mdm|msm|qcm|qcs|sa|sc|sdm|sdx|sm)[0-9]+.*$"
- pattern: "^qcom,mmcc-(apq|ipq|mdm|msm|qcm|qcs|sa|sc|sdm|sdx|sm)[0-9]+.*$"
- pattern: "^qcom,pcie-(apq|ipq|mdm|msm|qcm|qcs|sa|sc|sdm|sdx|sm)[0-9]+.*$"
- pattern: "^qcom,rpm-(apq|ipq|mdm|msm|qcm|qcs|sa|sc|sdm|sdx|sm)[0-9]+.*$"
- pattern: "^qcom,scm-(apq|ipq|mdm|msm|qcm|qcs|sa|sc|sdm|sdx|sm)[0-9]+.*$"
- pattern: "^qcom,[ak]pss-wdt-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm)[0-9]+.*$"
- pattern: "^qcom,gcc-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm)[0-9]+.*$"
- pattern: "^qcom,mmcc-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm)[0-9]+.*$"
- pattern: "^qcom,pcie-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1e)[0-9]+.*$"
- pattern: "^qcom,rpm-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm)[0-9]+.*$"
- pattern: "^qcom,scm-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1e)[0-9]+.*$"
- enum:
- qcom,dsi-ctrl-6g-qcm2290
- qcom,gpucc-sdm630

47
Documentation/devicetree/bindings/arm/qcom.yaml
View File

@ -87,29 +87,18 @@ description: |
sm8350
sm8450
sm8550
sm8650
x1e80100
The 'board' element must be one of the following strings:
adp
ap-al02-c2
ap-al02-c6
ap-al02-c7
ap-al02-c8
ap-al02-c9
ap-mi01.2
ap-mi01.3
ap-mi01.6
ap-mi01.9
cdp
cp01-c1
dragonboard
hk01
hk10-c1
hk10-c2
idp
liquid
rdp432-c2
mtp
qcp
qrd
rb2
ride
@ -138,7 +127,7 @@ description: |
There are many devices in the list below that run the standard ChromeOS
bootloader setup and use the open source depthcharge bootloader to boot the
OS. These devices do not use the scheme described above. For details, see:
https://docs.kernel.org/arm/google/chromebook-boot-flow.html
https://docs.kernel.org/arch/arm/google/chromebook-boot-flow.html
properties:
$nodename:
@ -186,11 +175,24 @@ properties:
- items:
- enum:
- microsoft,dempsey
- microsoft,makepeace
- microsoft,moneypenny
- samsung,s3ve3g
- const: qcom,msm8226
- items:
- enum:
- htc,memul
- microsoft,superman-lte
- microsoft,tesla
- motorola,peregrine
- const: qcom,msm8926
- const: qcom,msm8226
- items:
- enum:
- huawei,kiwi
- longcheer,l9100
- samsung,a7
- sony,kanuti-tulip
@ -397,6 +399,8 @@ properties:
- items:
- enum:
- fairphone,fp5
- qcom,qcm6490-idp
- qcom,qcs6490-rb3gen2
- const: qcom,qcm6490
- description: Qualcomm Technologies, Inc. Distributed Unit 1000 platform
@ -1009,6 +1013,7 @@ properties:
- sony,pdx203-generic
- sony,pdx206-generic
- xiaomi,elish
- xiaomi,pipa
- const: qcom,sm8250
- items:
@ -1034,6 +1039,18 @@ properties:
- qcom,sm8550-qrd
- const: qcom,sm8550
- items:
- enum:
- qcom,sm8650-mtp
- qcom,sm8650-qrd
- const: qcom,sm8650
- items:
- enum:
- qcom,x1e80100-crd
- qcom,x1e80100-qcp
- const: qcom,x1e80100
# Board compatibles go above
qcom,msm-id:

18
Documentation/devicetree/bindings/clock/qcom,camcc-sm8250.yaml
View File

@ -15,6 +15,9 @@ description: |
See also:: include/dt-bindings/clock/qcom,camcc-sm8250.h
allOf:
- $ref: qcom,gcc.yaml#
properties:
compatible:
const: qcom,sm8250-camcc
@ -33,15 +36,6 @@ properties:
- const: bi_tcxo_ao
- const: sleep_clk
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
power-domains:
items:
- description: MMCX power domain
@ -56,14 +50,10 @@ properties:
required:
- compatible
- reg
- clocks
- clock-names
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
unevaluatedProperties: false
examples:
- |

4
Documentation/devicetree/bindings/clock/qcom,gcc-ipq8074.yaml
View File

@ -27,11 +27,15 @@ properties:
items:
- description: board XO clock
- description: sleep clock
- description: Gen3 QMP PCIe PHY PIPE clock
- description: Gen2 QMP PCIe PHY PIPE clock
clock-names:
items:
- const: xo
- const: sleep_clk
- const: pcie0_pipe
- const: pcie1_pipe
required:
- compatible

2
Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml
View File

@ -35,6 +35,8 @@ properties:
- qcom,sm8350-rpmh-clk
- qcom,sm8450-rpmh-clk
- qcom,sm8550-rpmh-clk
- qcom,sm8650-rpmh-clk
- qcom,x1e80100-rpmh-clk
clocks:
maxItems: 1

18
Documentation/devicetree/bindings/clock/qcom,sc7180-camcc.yaml
View File

@ -15,6 +15,9 @@ description: |
See also:: include/dt-bindings/clock/qcom,camcc-sc7180.h
allOf:
- $ref: qcom,gcc.yaml#
properties:
compatible:
const: qcom,sc7180-camcc
@ -31,28 +34,15 @@ properties:
- const: iface
- const: xo
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
required:
- compatible
- reg
- clocks
- clock-names
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
unevaluatedProperties: false
examples:
- |

18
Documentation/devicetree/bindings/clock/qcom,sc7280-camcc.yaml
View File

@ -15,6 +15,9 @@ description: |
See also:: include/dt-bindings/clock/qcom,camcc-sc7280.h
allOf:
- $ref: qcom,gcc.yaml#
properties:
compatible:
const: qcom,sc7280-camcc
@ -31,28 +34,15 @@ properties:
- const: bi_tcxo_ao
- const: sleep_clk
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
required:
- compatible
- reg
- clocks
- clock-names
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
unevaluatedProperties: false
examples:
- |

18
Documentation/devicetree/bindings/clock/qcom,sdm845-camcc.yaml
View File

@ -15,6 +15,9 @@ description: |
See also:: include/dt-bindings/clock/qcom,camcc-sm845.h
allOf:
- $ref: qcom,gcc.yaml#
properties:
compatible:
const: qcom,sdm845-camcc
@ -27,28 +30,15 @@ properties:
items:
- const: bi_tcxo
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
required:
- compatible
- reg
- clocks
- clock-names
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
unevaluatedProperties: false
examples:
- |

20
Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml
View File

@ -16,10 +16,15 @@ description: |
See also::
include/dt-bindings/clock/qcom,sm8450-camcc.h
include/dt-bindings/clock/qcom,sm8550-camcc.h
include/dt-bindings/clock/qcom,sc8280xp-camcc.h
allOf:
- $ref: qcom,gcc.yaml#
properties:
compatible:
enum:
- qcom,sc8280xp-camcc
- qcom,sm8450-camcc
- qcom,sm8550-camcc
@ -40,29 +45,16 @@ properties:
description:
A phandle to an OPP node describing required MMCX performance point.
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
required:
- compatible
- reg
- clocks
- power-domains
- required-opps
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
unevaluatedProperties: false
examples:
- |

2
Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml
View File

@ -17,12 +17,14 @@ description: |
include/dt-bindings/clock/qcom,sm8450-gpucc.h
include/dt-bindings/clock/qcom,sm8550-gpucc.h
include/dt-bindings/reset/qcom,sm8450-gpucc.h
include/dt-bindings/reset/qcom,sm8650-gpucc.h
properties:
compatible:
enum:
- qcom,sm8450-gpucc
- qcom,sm8550-gpucc
- qcom,sm8650-gpucc
clocks:
items:

8
Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml
View File

@ -13,12 +13,16 @@ description: |
Qualcomm TCSR clock control module provides the clocks, resets and
power domains on SM8550
See also:: include/dt-bindings/clock/qcom,sm8550-tcsr.h
See also:
- include/dt-bindings/clock/qcom,sm8550-tcsr.h
- include/dt-bindings/clock/qcom,sm8650-tcsr.h
properties:
compatible:
items:
- const: qcom,sm8550-tcsr
- enum:
- qcom,sm8550-tcsr
- qcom,sm8650-tcsr
- const: syscon
clocks:

106
Documentation/devicetree/bindings/clock/qcom,sm8650-dispcc.yaml Normal file
View File

@ -0,0 +1,106 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sm8650-dispcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display Clock & Reset Controller for SM8650
maintainers:
- Bjorn Andersson <andersson@kernel.org>
- Neil Armstrong <neil.armstrong@linaro.org>
description: |
Qualcomm display clock control module provides the clocks, resets and power
domains on SM8650.
See also:: include/dt-bindings/clock/qcom,sm8650-dispcc.h
properties:
compatible:
enum:
- qcom,sm8650-dispcc
clocks:
items:
- description: Board XO source
- description: Board Always On XO source
- description: Display's AHB clock
- description: sleep clock
- description: Byte clock from DSI PHY0
- description: Pixel clock from DSI PHY0
- description: Byte clock from DSI PHY1
- description: Pixel clock from DSI PHY1
- description: Link clock from DP PHY0
- description: VCO DIV clock from DP PHY0
- description: Link clock from DP PHY1
- description: VCO DIV clock from DP PHY1
- description: Link clock from DP PHY2
- description: VCO DIV clock from DP PHY2
- description: Link clock from DP PHY3
- description: VCO DIV clock from DP PHY3
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
power-domains:
description:
A phandle and PM domain specifier for the MMCX power domain.
maxItems: 1
required-opps:
description:
A phandle to an OPP node describing required MMCX performance point.
maxItems: 1
required:
- compatible
- reg
- clocks
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,sm8650-gcc.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
clock-controller@af00000 {
compatible = "qcom,sm8650-dispcc";
reg = <0x0af00000 0x10000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&gcc GCC_DISP_AHB_CLK>,
<&sleep_clk>,
<&dsi0_phy 0>,
<&dsi0_phy 1>,
<&dsi1_phy 0>,
<&dsi1_phy 1>,
<&dp0_phy 0>,
<&dp0_phy 1>,
<&dp1_phy 0>,
<&dp1_phy 1>,
<&dp2_phy 0>,
<&dp2_phy 1>,
<&dp3_phy 0>,
<&dp3_phy 1>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
power-domains = <&rpmhpd RPMHPD_MMCX>;
required-opps = <&rpmhpd_opp_low_svs>;
};
...

65
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@ -0,0 +1,65 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sm8650-gcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller on SM8650
maintainers:
- Bjorn Andersson <andersson@kernel.org>
description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on SM8650
See also:: include/dt-bindings/clock/qcom,sm8650-gcc.h
properties:
compatible:
const: qcom,sm8650-gcc
clocks:
items:
- description: Board XO source
- description: Board Always On XO source
- description: Sleep clock source
- description: PCIE 0 Pipe clock source
- description: PCIE 1 Pipe clock source
- description: PCIE 1 Phy Auxiliary clock source
- description: UFS Phy Rx symbol 0 clock source
- description: UFS Phy Rx symbol 1 clock source
- description: UFS Phy Tx symbol 0 clock source
- description: USB3 Phy wrapper pipe clock source
required:
- compatible
- clocks
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
clock-controller@100000 {
compatible = "qcom,sm8650-gcc";
reg = <0x00100000 0x001f4200>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&sleep_clk>,
<&pcie0_phy>,
<&pcie1_phy>,
<&pcie_1_phy_aux_clk>,
<&ufs_mem_phy 0>,
<&ufs_mem_phy 1>,
<&ufs_mem_phy 2>,
<&usb_1_qmpphy>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...

72
Documentation/devicetree/bindings/clock/qcom,x1e80100-gcc.yaml Normal file
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@ -0,0 +1,72 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,x1e80100-gcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller on X1E80100
maintainers:
- Rajendra Nayak <quic_rjendra@quicinc.com>
description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on X1E80100
See also:: include/dt-bindings/clock/qcom,x1e80100-gcc.h
properties:
compatible:
const: qcom,x1e80100-gcc
clocks:
items:
- description: Board XO source
- description: Sleep clock source
- description: PCIe 3 pipe clock
- description: PCIe 4 pipe clock
- description: PCIe 5 pipe clock
- description: PCIe 6a pipe clock
- description: PCIe 6b pipe clock
- description: USB QMP Phy 0 clock source
- description: USB QMP Phy 1 clock source
- description: USB QMP Phy 2 clock source
power-domains:
description:
A phandle and PM domain specifier for the CX power domain.
maxItems: 1
required:
- compatible
- clocks
- power-domains
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/power/qcom,rpmhpd.h>
clock-controller@100000 {
compatible = "qcom,x1e80100-gcc";
reg = <0x00100000 0x200000>;
clocks = <&bi_tcxo_div2>,
<&sleep_clk>,
<&pcie3_phy>,
<&pcie4_phy>,
<&pcie5_phy>,
<&pcie6a_phy>,
<&pcie6b_phy>,
<&usb_1_ss0_qmpphy 0>,
<&usb_1_ss1_qmpphy 1>,
<&usb_1_ss2_qmpphy 2>;
power-domains = <&rpmhpd RPMHPD_CX>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...

152
Documentation/devicetree/bindings/interconnect/qcom,sm6115.yaml Normal file
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@ -0,0 +1,152 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interconnect/qcom,sm6115.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm SM6115 Network-On-Chip interconnect
maintainers:
- Konrad Dybcio <konradybcio@kernel.org>
description:
The Qualcomm SM6115 interconnect providers support adjusting the
bandwidth requirements between the various NoC fabrics.
properties:
compatible:
enum:
- qcom,sm6115-bimc
- qcom,sm6115-cnoc
- qcom,sm6115-snoc
reg:
maxItems: 1
clocks:
minItems: 1
maxItems: 4
clock-names:
minItems: 1
maxItems: 4
# Child node's properties
patternProperties:
'^interconnect-[a-z0-9]+$':
type: object
description:
The interconnect providers do not have a separate QoS register space,
but share parent's space.
$ref: qcom,rpm-common.yaml#
properties:
compatible:
enum:
- qcom,sm6115-clk-virt
- qcom,sm6115-mmrt-virt
- qcom,sm6115-mmnrt-virt
required:
- compatible
unevaluatedProperties: false
required:
- compatible
- reg
allOf:
- $ref: qcom,rpm-common.yaml#
- if:
properties:
compatible:
const: qcom,sm6115-cnoc
then:
properties:
clocks:
items:
- description: USB-NoC AXI clock
clock-names:
items:
- const: usb_axi
- if:
properties:
compatible:
const: qcom,sm6115-snoc
then:
properties:
clocks:
items:
- description: CPU-NoC AXI clock.
- description: UFS-NoC AXI clock.
- description: USB-NoC AXI clock.
- description: IPA clock.
clock-names:
items:
- const: cpu_axi
- const: ufs_axi
- const: usb_axi
- const: ipa
- if:
properties:
compatible:
enum:
- qcom,sm6115-bimc
- qcom,sm6115-clk-virt
- qcom,sm6115-mmrt-virt
- qcom,sm6115-mmnrt-virt
then:
properties:
clocks: false
clock-names: false
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,gcc-sm6115.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
snoc: interconnect@1880000 {
compatible = "qcom,sm6115-snoc";
reg = <0x01880000 0x60200>;
clocks = <&gcc GCC_SYS_NOC_CPUSS_AHB_CLK>,
<&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>,
<&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>,
<&rpmcc RPM_SMD_IPA_CLK>;
clock-names = "cpu_axi",
"ufs_axi",
"usb_axi",
"ipa";
#interconnect-cells = <1>;
qup_virt: interconnect-clk {
compatible = "qcom,sm6115-clk-virt";
#interconnect-cells = <1>;
};
mmnrt_virt: interconnect-mmnrt {
compatible = "qcom,sm6115-mmnrt-virt";
#interconnect-cells = <1>;
};
mmrt_virt: interconnect-mmrt {
compatible = "qcom,sm6115-mmrt-virt";
#interconnect-cells = <1>;
};
};
cnoc: interconnect@1900000 {
compatible = "qcom,sm6115-cnoc";
reg = <0x01900000 0x8200>;
#interconnect-cells = <1>;
};

136
Documentation/devicetree/bindings/interconnect/qcom,sm8650-rpmh.yaml Normal file
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@ -0,0 +1,136 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interconnect/qcom,sm8650-rpmh.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm RPMh Network-On-Chip Interconnect on SM8650
maintainers:
- Abel Vesa <abel.vesa@linaro.org>
- Neil Armstrong <neil.armstrong@linaro.org>
description: |
RPMh interconnect providers support system bandwidth requirements through
RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
able to communicate with the BCM through the Resource State Coordinator (RSC)
associated with each execution environment. Provider nodes must point to at
least one RPMh device child node pertaining to their RSC and each provider
can map to multiple RPMh resources.
See also:: include/dt-bindings/interconnect/qcom,sm8650-rpmh.h
properties:
compatible:
enum:
- qcom,sm8650-aggre1-noc
- qcom,sm8650-aggre2-noc
- qcom,sm8650-clk-virt
- qcom,sm8650-cnoc-main
- qcom,sm8650-config-noc
- qcom,sm8650-gem-noc
- qcom,sm8650-lpass-ag-noc
- qcom,sm8650-lpass-lpiaon-noc
- qcom,sm8650-lpass-lpicx-noc
- qcom,sm8650-mc-virt
- qcom,sm8650-mmss-noc
- qcom,sm8650-nsp-noc
- qcom,sm8650-pcie-anoc
- qcom,sm8650-system-noc
reg:
maxItems: 1
clocks:
minItems: 1
maxItems: 2
required:
- compatible
allOf:
- $ref: qcom,rpmh-common.yaml#
- if:
properties:
compatible:
contains:
enum:
- qcom,sm8650-clk-virt
- qcom,sm8650-mc-virt
then:
properties:
reg: false
else:
required:
- reg
- if:
properties:
compatible:
contains:
enum:
- qcom,sm8650-pcie-anoc
then:
properties:
clocks:
items:
- description: aggre-NOC PCIe AXI clock
- description: cfg-NOC PCIe a-NOC AHB clock
- if:
properties:
compatible:
contains:
enum:
- qcom,sm8650-aggre1-noc
then:
properties:
clocks:
items:
- description: aggre UFS PHY AXI clock
- description: aggre USB3 PRIM AXI clock
- if:
properties:
compatible:
contains:
enum:
- qcom,sm8650-aggre2-noc
then:
properties:
clocks:
items:
- description: RPMH CC IPA clock
- if:
properties:
compatible:
contains:
enum:
- qcom,sm8650-aggre1-noc
- qcom,sm8650-aggre2-noc
- qcom,sm8650-pcie-anoc
then:
required:
- clocks
else:
properties:
clocks: false
unevaluatedProperties: false
examples:
- |
clk_virt: interconnect-0 {
compatible = "qcom,sm8650-clk-virt";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
aggre1_noc: interconnect@16e0000 {
compatible = "qcom,sm8650-aggre1-noc";
reg = <0x016e0000 0x14400>;
#interconnect-cells = <2>;
clocks = <&gcc_phy_axi_clk>, <&gcc_prim_axi_clk>;
qcom,bcm-voters = <&apps_bcm_voter>;
};

83
Documentation/devicetree/bindings/interconnect/qcom,x1e80100-rpmh.yaml Normal file
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@ -0,0 +1,83 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interconnect/qcom,x1e80100-rpmh.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm RPMh Network-On-Chip Interconnect on X1E80100
maintainers:
- Rajendra Nayak <quic_rjendra@quicinc.com>
- Abel Vesa <abel.vesa@linaro.org>
description: |
RPMh interconnect providers support system bandwidth requirements through
RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
able to communicate with the BCM through the Resource State Coordinator (RSC)
associated with each execution environment. Provider nodes must point to at
least one RPMh device child node pertaining to their RSC and each provider
can map to multiple RPMh resources.
See also:: include/dt-bindings/interconnect/qcom,x1e80100-rpmh.h
properties:
compatible:
enum:
- qcom,x1e80100-aggre1-noc
- qcom,x1e80100-aggre2-noc
- qcom,x1e80100-clk-virt
- qcom,x1e80100-cnoc-cfg
- qcom,x1e80100-cnoc-main
- qcom,x1e80100-gem-noc
- qcom,x1e80100-lpass-ag-noc
- qcom,x1e80100-lpass-lpiaon-noc
- qcom,x1e80100-lpass-lpicx-noc
- qcom,x1e80100-mc-virt
- qcom,x1e80100-mmss-noc
- qcom,x1e80100-nsp-noc
- qcom,x1e80100-pcie-center-anoc
- qcom,x1e80100-pcie-north-anoc
- qcom,x1e80100-pcie-south-anoc
- qcom,x1e80100-system-noc
- qcom,x1e80100-usb-center-anoc
- qcom,x1e80100-usb-north-anoc
- qcom,x1e80100-usb-south-anoc
reg:
maxItems: 1
required:
- compatible
allOf:
- $ref: qcom,rpmh-common.yaml#
- if:
properties:
compatible:
contains:
enum:
- qcom,x1e80100-clk-virt
- qcom,x1e80100-mc-virt
then:
properties:
reg: false
else:
required:
- reg
unevaluatedProperties: false
examples:
- |
clk_virt: interconnect-0 {
compatible = "qcom,x1e80100-clk-virt";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
aggre1_noc: interconnect@16e0000 {
compatible = "qcom,x1e80100-aggre1-noc";
reg = <0x016e0000 0x14400>;
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};

2
Documentation/devicetree/bindings/vendor-prefixes.yaml
View File

@ -599,6 +599,8 @@ patternProperties:
description: Hewlett Packard Enterprise
"^hsg,.*":
description: HannStar Display Co.
"^htc,.*":
description: HTC Corporation
"^huawei,.*":
description: Huawei Technologies Co., Ltd.
"^hugsun,.*":

8
arch/arm64/boot/dts/qcom/Makefile
View File

@ -45,6 +45,7 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8916-thwc-uf896.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-thwc-ufi001c.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-wingtech-wt88047.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-yiming-uz801v3.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8939-huawei-kiwi.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8939-longcheer-l9100.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8939-samsung-a7.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8939-sony-xperia-kanuti-tulip.dtb
@ -87,8 +88,10 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8998-sony-xperia-yoshino-maple.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8998-sony-xperia-yoshino-poplar.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8998-xiaomi-sagit.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcm6490-fairphone-fp5.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcm6490-idp.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2.dtb
dtb-$(CONFIG_ARCH_QCOM) += qdu1000-idp.dtb
dtb-$(CONFIG_ARCH_QCOM) += qrb2210-rb1.dtb
dtb-$(CONFIG_ARCH_QCOM) += qrb4210-rb2.dtb
@ -220,6 +223,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8250-sony-xperia-edo-pdx203.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8250-sony-xperia-edo-pdx206.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8250-xiaomi-elish-boe.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8250-xiaomi-elish-csot.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8250-xiaomi-pipa.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8350-hdk.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8350-microsoft-surface-duo2.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8350-mtp.dtb
@ -231,3 +235,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8450-sony-xperia-nagara-pdx223.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8450-sony-xperia-nagara-pdx224.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8550-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8550-qrd.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8650-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8650-qrd.dtb
dtb-$(CONFIG_ARCH_QCOM) += x1e80100-crd.dtb
dtb-$(CONFIG_ARCH_QCOM) += x1e80100-qcp.dtb

12
arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts
View File

@ -67,6 +67,18 @@
};
};
&usb {
status = "okay";
};
&usb_dwc {
dr_mode = "host";
};
&usbphy0 {
status = "okay";
};
&xo_board_clk {
clock-frequency = <24000000>;
};

142
arch/arm64/boot/dts/qcom/ipq5018.dtsi
View File

@ -5,6 +5,7 @@
* Copyright (c) 2023 The Linux Foundation. All rights reserved.
*/
#include <dt-bindings/clock/qcom,apss-ipq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-ipq5018.h>
#include <dt-bindings/reset/qcom,gcc-ipq5018.h>
@ -36,6 +37,8 @@
reg = <0x0>;
enable-method = "psci";
next-level-cache = <&L2_0>;
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
operating-points-v2 = <&cpu_opp_table>;
};
CPU1: cpu@1 {
@ -44,6 +47,8 @@
reg = <0x1>;
enable-method = "psci";
next-level-cache = <&L2_0>;
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
operating-points-v2 = <&cpu_opp_table>;
};
L2_0: l2-cache {
@ -54,6 +59,23 @@
};
};
cpu_opp_table: opp-table-cpu {
compatible = "operating-points-v2";
opp-shared;
opp-800000000 {
opp-hz = /bits/ 64 <800000000>;
opp-microvolt = <1100000>;
clock-latency-ns = <200000>;
};
opp-1008000000 {
opp-hz = /bits/ 64 <1008000000>;
opp-microvolt = <1100000>;
clock-latency-ns = <200000>;
};
};
firmware {
scm {
compatible = "qcom,scm-ipq5018", "qcom,scm";
@ -82,6 +104,24 @@
#size-cells = <2>;
ranges;
bootloader@4a800000 {
reg = <0x0 0x4a800000 0x0 0x200000>;
no-map;
};
sbl@4aa00000 {
reg = <0x0 0x4aa00000 0x0 0x100000>;
no-map;
};
smem@4ab00000 {
compatible = "qcom,smem";
reg = <0x0 0x4ab00000 0x0 0x100000>;
no-map;
hwlocks = <&tcsr_mutex 3>;
};
tz_region: tz@4ac00000 {
reg = <0x0 0x4ac00000 0x0 0x200000>;
no-map;
@ -94,6 +134,19 @@
#size-cells = <1>;
ranges = <0 0 0 0xffffffff>;
usbphy0: phy@5b000 {
compatible = "qcom,ipq5018-usb-hsphy";
reg = <0x0005b000 0x120>;
clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>;
resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
#phy-cells = <0>;
status = "disabled";
};
tlmm: pinctrl@1000000 {
compatible = "qcom,ipq5018-tlmm";
reg = <0x01000000 0x300000>;
@ -129,6 +182,12 @@
#power-domain-cells = <1>;
};
tcsr_mutex: hwlock@1905000 {
compatible = "qcom,tcsr-mutex";
reg = <0x01905000 0x20000>;
#hwlock-cells = <1>;
};
sdhc_1: mmc@7804000 {
compatible = "qcom,ipq5018-sdhci", "qcom,sdhci-msm-v5";
reg = <0x7804000 0x1000>;
@ -146,6 +205,16 @@
status = "disabled";
};
blsp_dma: dma-controller@7884000 {
compatible = "qcom,bam-v1.7.0";
reg = <0x07884000 0x1d000>;
interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "bam_clk";
#dma-cells = <1>;
qcom,ee = <0>;
};
blsp1_uart1: serial@78af000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x078af000 0x200>;
@ -156,6 +225,61 @@
status = "disabled";
};
blsp1_spi1: spi@78b5000 {
compatible = "qcom,spi-qup-v2.2.1";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x078b5000 0x600>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
dmas = <&blsp_dma 4>, <&blsp_dma 5>;
dma-names = "tx", "rx";
status = "disabled";
};
usb: usb@8af8800 {
compatible = "qcom,ipq5018-dwc3", "qcom,dwc3";
reg = <0x08af8800 0x400>;
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hs_phy_irq";
clocks = <&gcc GCC_USB0_MASTER_CLK>,
<&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
<&gcc GCC_USB0_SLEEP_CLK>,
<&gcc GCC_USB0_MOCK_UTMI_CLK>;
clock-names = "core",
"iface",
"sleep",
"mock_utmi";
resets = <&gcc GCC_USB0_BCR>;
qcom,select-utmi-as-pipe-clk;
#address-cells = <1>;
#size-cells = <1>;
ranges;
status = "disabled";
usb_dwc: usb@8a00000 {
compatible = "snps,dwc3";
reg = <0x08a00000 0xe000>;
clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>;
clock-names = "ref";
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
phy-names = "usb2-phy";
phys = <&usbphy0>;
tx-fifo-resize;
snps,is-utmi-l1-suspend;
snps,hird-threshold = /bits/ 8 <0x0>;
snps,dis_u2_susphy_quirk;
snps,dis_u3_susphy_quirk;
};
};
intc: interrupt-controller@b000000 {
compatible = "qcom,msm-qgic2";
reg = <0x0b000000 0x1000>, /* GICD */
@ -189,6 +313,24 @@
clocks = <&sleep_clk>;
};
apcs_glb: mailbox@b111000 {
compatible = "qcom,ipq5018-apcs-apps-global",
"qcom,ipq6018-apcs-apps-global";
reg = <0x0b111000 0x1000>;
#clock-cells = <1>;
clocks = <&a53pll>, <&xo_board_clk>, <&gcc GPLL0>;
clock-names = "pll", "xo", "gpll0";
#mbox-cells = <1>;
};
a53pll: clock@b116000 {
compatible = "qcom,ipq5018-a53pll";
reg = <0x0b116000 0x40>;
#clock-cells = <0>;
clocks = <&xo_board_clk>;
clock-names = "xo";
};
timer@b120000 {
compatible = "arm,armv7-timer-mem";
reg = <0x0b120000 0x1000>;

3
arch/arm64/boot/dts/qcom/ipq5332-rdp-common.dtsi
View File

@ -9,6 +9,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include "ipq5332.dtsi"
/ {
@ -39,6 +40,8 @@
pinctrl-names = "default";
led-0 {
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_WLAN;
gpios = <&tlmm 36 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "phy0tx";
default-state = "off";

2
arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts
View File

@ -15,7 +15,7 @@
};
&blsp1_i2c1 {
clock-frequency = <400000>;
clock-frequency = <400000>;
pinctrl-0 = <&i2c_1_pins>;
pinctrl-names = "default";
status = "okay";

2
arch/arm64/boot/dts/qcom/ipq5332-rdp442.dts
View File

@ -15,7 +15,7 @@
};
&blsp1_i2c1 {
clock-frequency = <400000>;
clock-frequency = <400000>;
pinctrl-0 = <&i2c_1_pins>;
pinctrl-names = "default";
status = "okay";

2
arch/arm64/boot/dts/qcom/ipq5332-rdp474.dts
View File

@ -15,7 +15,7 @@
};
&blsp1_i2c1 {
clock-frequency = <400000>;
clock-frequency = <400000>;
pinctrl-0 = <&i2c_1_pins>;
pinctrl-names = "default";
status = "okay";

23
arch/arm64/boot/dts/qcom/ipq5332.dtsi
View File

@ -91,11 +91,19 @@
};
cpu_opp_table: opp-table-cpu {
compatible = "operating-points-v2";
compatible = "operating-points-v2-kryo-cpu";
opp-shared;
nvmem-cells = <&cpu_speed_bin>;
opp-1488000000 {
opp-hz = /bits/ 64 <1488000000>;
opp-1100000000 {
opp-hz = /bits/ 64 <1100000000>;
opp-supported-hw = <0x7>;
clock-latency-ns = <200000>;
};
opp-1500000000 {
opp-hz = /bits/ 64 <1500000000>;
opp-supported-hw = <0x3>;
clock-latency-ns = <200000>;
};
};
@ -163,6 +171,11 @@
reg = <0x000a4000 0x721>;
#address-cells = <1>;
#size-cells = <1>;
cpu_speed_bin: cpu-speed-bin@1d {
reg = <0x1d 0x2>;
bits = <7 2>;
};
};
rng: rng@e3000 {
@ -390,8 +403,8 @@
"qcom,ipq6018-apcs-apps-global";
reg = <0x0b111000 0x1000>;
#clock-cells = <1>;
clocks = <&a53pll>, <&xo_board>;
clock-names = "pll", "xo";
clocks = <&a53pll>, <&xo_board>, <&gcc GPLL0>;
clock-names = "pll", "xo", "gpll0";
#mbox-cells = <1>;
};

119
arch/arm64/boot/dts/qcom/ipq6018.dtsi
View File

@ -96,42 +96,49 @@
};
cpu_opp_table: opp-table-cpu {
compatible = "operating-points-v2";
compatible = "operating-points-v2-kryo-cpu";
nvmem-cells = <&cpu_speed_bin>;
opp-shared;
opp-864000000 {
opp-hz = /bits/ 64 <864000000>;
opp-microvolt = <725000>;
opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
};
opp-1056000000 {
opp-hz = /bits/ 64 <1056000000>;
opp-microvolt = <787500>;
opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
};
opp-1320000000 {
opp-hz = /bits/ 64 <1320000000>;
opp-microvolt = <862500>;
opp-supported-hw = <0x3>;
clock-latency-ns = <200000>;
};
opp-1440000000 {
opp-hz = /bits/ 64 <1440000000>;
opp-microvolt = <925000>;
opp-supported-hw = <0x3>;
clock-latency-ns = <200000>;
};
opp-1608000000 {
opp-hz = /bits/ 64 <1608000000>;
opp-microvolt = <987500>;
opp-supported-hw = <0x1>;
clock-latency-ns = <200000>;
};
opp-1800000000 {
opp-hz = /bits/ 64 <1800000000>;
opp-microvolt = <1062500>;
opp-supported-hw = <0x1>;
clock-latency-ns = <200000>;
};
};
@ -236,31 +243,26 @@
ssphy_0: ssphy@78000 {
compatible = "qcom,ipq6018-qmp-usb3-phy";
reg = <0x0 0x00078000 0x0 0x1c4>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
reg = <0x0 0x00078000 0x0 0x1000>;
clocks = <&gcc GCC_USB0_AUX_CLK>,
<&gcc GCC_USB0_PHY_CFG_AHB_CLK>, <&xo>;
clock-names = "aux", "cfg_ahb", "ref";
<&xo>,
<&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
<&gcc GCC_USB0_PIPE_CLK>;
clock-names = "aux",
"ref",
"cfg_ahb",
"pipe";
clock-output-names = "gcc_usb0_pipe_clk_src";
#clock-cells = <0>;
#phy-cells = <0>;
resets = <&gcc GCC_USB0_PHY_BCR>,
<&gcc GCC_USB3PHY_0_PHY_BCR>;
reset-names = "phy","common";
status = "disabled";
reset-names = "phy",
"phy_phy";
usb0_ssphy: phy@78200 {
reg = <0x0 0x00078200 0x0 0x130>, /* Tx */
<0x0 0x00078400 0x0 0x200>, /* Rx */
<0x0 0x00078800 0x0 0x1f8>, /* PCS */
<0x0 0x00078600 0x0 0x044>; /* PCS misc */
#phy-cells = <0>;
#clock-cells = <0>;
clocks = <&gcc GCC_USB0_PIPE_CLK>;
clock-names = "pipe0";
clock-output-names = "gcc_usb0_pipe_clk_src";
};
status = "disabled";
};
qusb_phy_0: qusb@79000 {
@ -314,6 +316,11 @@
reg = <0x0 0x000a4000 0x0 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
cpu_speed_bin: cpu-speed-bin@135 {
reg = <0x135 0x1>;
bits = <7 1>;
};
};
prng: qrng@e3000 {
@ -439,6 +446,26 @@
qcom,ee = <0>;
};
blsp1_uart1: serial@78af000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x0 0x78af000 0x0 0x200>;
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
status = "disabled";
};
blsp1_uart2: serial@78b0000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x0 0x78b0000 0x0 0x200>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
status = "disabled";
};
blsp1_uart3: serial@78b1000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x0 0x078b1000 0x0 0x200>;
@ -449,6 +476,36 @@
status = "disabled";
};
blsp1_uart4: serial@78b2000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x0 0x078b2000 0x0 0x200>;
interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_UART4_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
status = "disabled";
};
blsp1_uart5: serial@78b3000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x0 0x78b3000 0x0 0x200>;
interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
status = "disabled";
};
blsp1_uart6: serial@78b4000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x0 0x078b4000 0x0 0x200>;
interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_UART6_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
status = "disabled";
};
blsp1_spi1: spi@78b5000 {
compatible = "qcom,spi-qup-v2.2.1";
#address-cells = <1>;
@ -477,6 +534,20 @@
status = "disabled";
};
blsp1_spi5: spi@78b9000 {
compatible = "qcom,spi-qup-v2.2.1";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x078b9000 0x0 0x600>;
interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
dmas = <&blsp_dma 20>, <&blsp_dma 21>;
dma-names = "tx", "rx";
status = "disabled";
};
blsp1_i2c2: i2c@78b6000 {
compatible = "qcom,i2c-qup-v2.2.1";
#address-cells = <1>;
@ -566,7 +637,7 @@
compatible = "snps,dwc3";
reg = <0x0 0x08a00000 0x0 0xcd00>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
phys = <&qusb_phy_0>, <&usb0_ssphy>;
phys = <&qusb_phy_0>, <&ssphy_0>;
phy-names = "usb2-phy", "usb3-phy";
clocks = <&xo>;
clock-names = "ref";
@ -611,8 +682,8 @@
compatible = "qcom,ipq6018-apcs-apps-global";
reg = <0x0 0x0b111000 0x0 0x1000>;
#clock-cells = <1>;
clocks = <&a53pll>, <&xo>;
clock-names = "pll", "xo";
clocks = <&a53pll>, <&xo>, <&gcc GPLL0>;
clock-names = "pll", "xo", "gpll0";
#mbox-cells = <1>;
};
@ -731,7 +802,7 @@
};
};
pcie0: pci@20000000 {
pcie0: pcie@20000000 {
compatible = "qcom,pcie-ipq6018";
reg = <0x0 0x20000000 0x0 0xf1d>,
<0x0 0x20000f20 0x0 0xa8>,

110
arch/arm64/boot/dts/qcom/ipq8074.dtsi
View File

@ -125,32 +125,26 @@
ssphy_1: phy@58000 {
compatible = "qcom,ipq8074-qmp-usb3-phy";
reg = <0x00058000 0x1c4>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
reg = <0x00058000 0x1000>;
clocks = <&gcc GCC_USB1_AUX_CLK>,
<&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
<&xo>;
clock-names = "aux", "cfg_ahb", "ref";
<&xo>,
<&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
<&gcc GCC_USB1_PIPE_CLK>;
clock-names = "aux",
"ref",
"cfg_ahb",
"pipe";
clock-output-names = "usb3phy_1_cc_pipe_clk";
#clock-cells = <0>;
#phy-cells = <0>;
resets = <&gcc GCC_USB1_PHY_BCR>,
<&gcc GCC_USB3PHY_1_PHY_BCR>;
reset-names = "phy","common";
status = "disabled";
<&gcc GCC_USB3PHY_1_PHY_BCR>;
reset-names = "phy",
"phy_phy";
usb1_ssphy: phy@58200 {
reg = <0x00058200 0x130>, /* Tx */
<0x00058400 0x200>, /* Rx */
<0x00058800 0x1f8>, /* PCS */
<0x00058600 0x044>; /* PCS misc */
#phy-cells = <0>;
#clock-cells = <0>;
clocks = <&gcc GCC_USB1_PIPE_CLK>;
clock-names = "pipe0";
clock-output-names = "usb3phy_1_cc_pipe_clk";
};
status = "disabled";
};
qusb_phy_1: phy@59000 {
@ -168,32 +162,26 @@
ssphy_0: phy@78000 {
compatible = "qcom,ipq8074-qmp-usb3-phy";
reg = <0x00078000 0x1c4>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
reg = <0x00078000 0x1000>;
clocks = <&gcc GCC_USB0_AUX_CLK>,
<&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
<&xo>;
clock-names = "aux", "cfg_ahb", "ref";
<&xo>,
<&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
<&gcc GCC_USB0_PIPE_CLK>;
clock-names = "aux",
"ref",
"cfg_ahb",
"pipe";
clock-output-names = "usb3phy_0_cc_pipe_clk";
#clock-cells = <0>;
#phy-cells = <0>;
resets = <&gcc GCC_USB0_PHY_BCR>,
<&gcc GCC_USB3PHY_0_PHY_BCR>;
reset-names = "phy","common";
status = "disabled";
<&gcc GCC_USB3PHY_0_PHY_BCR>;
reset-names = "phy",
"phy_phy";
usb0_ssphy: phy@78200 {
reg = <0x00078200 0x130>, /* Tx */
<0x00078400 0x200>, /* Rx */
<0x00078800 0x1f8>, /* PCS */
<0x00078600 0x044>; /* PCS misc */
#phy-cells = <0>;
#clock-cells = <0>;
clocks = <&gcc GCC_USB0_PIPE_CLK>;
clock-names = "pipe0";
clock-output-names = "usb3phy_0_cc_pipe_clk";
};
status = "disabled";
};
qusb_phy_0: phy@79000 {
@ -369,8 +357,14 @@
gcc: gcc@1800000 {
compatible = "qcom,gcc-ipq8074";
reg = <0x01800000 0x80000>;
clocks = <&xo>, <&sleep_clk>;
clock-names = "xo", "sleep_clk";
clocks = <&xo>,
<&sleep_clk>,
<&pcie_qmp0>,
<&pcie_qmp1>;
clock-names = "xo",
"sleep_clk",
"pcie0_pipe",
"pcie1_pipe";
#clock-cells = <1>;
#power-domain-cells = <1>;
#reset-cells = <1>;
@ -406,7 +400,7 @@
};
sdhc_1: mmc@7824900 {
compatible = "qcom,sdhci-msm-v4";
compatible = "qcom,ipq8074-sdhci", "qcom,sdhci-msm-v4";
reg = <0x7824900 0x500>, <0x7824000 0x800>;
reg-names = "hc", "core";
@ -523,6 +517,20 @@
status = "disabled";
};
blsp1_spi4: spi@78b8000 {
compatible = "qcom,spi-qup-v2.2.1";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x78b8000 0x600>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
dmas = <&blsp_dma 18>, <&blsp_dma 19>;
dma-names = "tx", "rx";
status = "disabled";
};
blsp1_i2c5: i2c@78b9000 {
compatible = "qcom,i2c-qup-v2.2.1";
#address-cells = <1>;
@ -628,7 +636,7 @@
compatible = "snps,dwc3";
reg = <0x8a00000 0xcd00>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
phys = <&qusb_phy_0>, <&usb0_ssphy>;
phys = <&qusb_phy_0>, <&ssphy_0>;
phy-names = "usb2-phy", "usb3-phy";
snps,is-utmi-l1-suspend;
snps,hird-threshold = /bits/ 8 <0x0>;
@ -670,7 +678,7 @@
compatible = "snps,dwc3";
reg = <0x8c00000 0xcd00>;
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
phys = <&qusb_phy_1>, <&usb1_ssphy>;
phys = <&qusb_phy_1>, <&ssphy_1>;
phy-names = "usb2-phy", "usb3-phy";
snps,is-utmi-l1-suspend;
snps,hird-threshold = /bits/ 8 <0x0>;
@ -708,8 +716,8 @@
compatible = "qcom,ipq8074-apcs-apps-global",
"qcom,ipq6018-apcs-apps-global";
reg = <0x0b111000 0x1000>;
clocks = <&a53pll>, <&xo>;
clock-names = "pll", "xo";
clocks = <&a53pll>, <&xo>, <&gcc GPLL0>;
clock-names = "pll", "xo", "gpll0";
#clock-cells = <1>;
#mbox-cells = <1>;
@ -781,7 +789,7 @@
};
};
pcie1: pci@10000000 {
pcie1: pcie@10000000 {
compatible = "qcom,pcie-ipq8074";
reg = <0x10000000 0xf1d>,
<0x10000f20 0xa8>,
@ -842,7 +850,7 @@
status = "disabled";
};
pcie0: pci@20000000 {
pcie0: pcie@20000000 {
compatible = "qcom,pcie-ipq8074-gen3";
reg = <0x20000000 0xf1d>,
<0x20000f20 0xa8>,

169
arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi Normal file
View File

@ -0,0 +1,169 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* IPQ9574 RDP board common device tree source
*
* Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include "ipq9574.dtsi"
/ {
aliases {
serial0 = &blsp1_uart2;
};
chosen {
stdout-path = "serial0:115200n8";
};
regulator_fixed_3p3: s3300 {
compatible = "regulator-fixed";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
regulator-name = "fixed_3p3";
};
regulator_fixed_0p925: s0925 {
compatible = "regulator-fixed";
regulator-min-microvolt = <925000>;
regulator-max-microvolt = <925000>;
regulator-boot-on;
regulator-always-on;
regulator-name = "fixed_0p925";
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-0 = <&gpio_keys_default>;
pinctrl-names = "default";
button-wps {
label = "wps";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
debounce-interval = <60>;
};
};
leds {
compatible = "gpio-leds";
pinctrl-0 = <&gpio_leds_default>;
pinctrl-names = "default";
led-0 {
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_WLAN;
gpios = <&tlmm 64 GPIO_ACTIVE_LOW>;
linux,default-trigger = "phy0tx";
default-state = "off";
};
};
};
&blsp1_spi0 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
flash@0 {
compatible = "micron,n25q128a11", "jedec,spi-nor";
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <50000000>;
};
};
&blsp1_uart2 {
pinctrl-0 = <&uart2_pins>;
pinctrl-names = "default";
status = "okay";
};
&rpm_requests {
regulators {
compatible = "qcom,rpm-mp5496-regulators";
ipq9574_s1: s1 {
/*
* During kernel bootup, the SoC runs at 800MHz with 875mV set by the bootloaders.
* During regulator registration, kernel not knowing the initial voltage,
* considers it as zero and brings up the regulators with minimum supported voltage.
* Update the regulator-min-microvolt with SVS voltage of 725mV so that
* the regulators are brought up with 725mV which is sufficient for all the
* corner parts to operate at 800MHz
*/
regulator-min-microvolt = <725000>;
regulator-max-microvolt = <1075000>;
};
mp5496_l2: l2 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
};
};
&sleep_clk {
clock-frequency = <32000>;
};
&tlmm {
spi_0_pins: spi-0-state {
pins = "gpio11", "gpio12", "gpio13", "gpio14";
function = "blsp0_spi";
drive-strength = <8>;
bias-disable;
};
gpio_keys_default: gpio-keys-default-state {
pins = "gpio37";
function = "gpio";
drive-strength = <8>;
bias-pull-up;
};
gpio_leds_default: gpio-leds-default-state {
pins = "gpio64";
function = "gpio";
drive-strength = <8>;
bias-pull-up;
};
};
&usb_0_dwc3 {
dr_mode = "host";
};
&usb_0_qmpphy {
vdda-pll-supply = <&mp5496_l2>;
vdda-phy-supply = <&regulator_fixed_0p925>;
status = "okay";
};
&usb_0_qusbphy {
vdd-supply = <&regulator_fixed_0p925>;
vdda-pll-supply = <&mp5496_l2>;
vdda-phy-dpdm-supply = <&regulator_fixed_3p3>;
status = "okay";
};
&usb3 {
status = "okay";
};
&xo_board_clk {
clock-frequency = <24000000>;
};

63
arch/arm64/boot/dts/qcom/ipq9574-rdp418.dts
View File

@ -8,58 +8,12 @@
/dts-v1/;
#include "ipq9574.dtsi"
#include "ipq9574-rdp-common.dtsi"
/ {
model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C2";
compatible = "qcom,ipq9574-ap-al02-c2", "qcom,ipq9574";
aliases {
serial0 = &blsp1_uart2;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&blsp1_spi0 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
flash@0 {
compatible = "micron,n25q128a11", "jedec,spi-nor";
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <50000000>;
};
};
&blsp1_uart2 {
pinctrl-0 = <&uart2_pins>;
pinctrl-names = "default";
status = "okay";
};
&rpm_requests {
regulators {
compatible = "qcom,rpm-mp5496-regulators";
ipq9574_s1: s1 {
/*
* During kernel bootup, the SoC runs at 800MHz with 875mV set by the bootloaders.
* During regulator registration, kernel not knowing the initial voltage,
* considers it as zero and brings up the regulators with minimum supported voltage.
* Update the regulator-min-microvolt with SVS voltage of 725mV so that
* the regulators are brought up with 725mV which is sufficient for all the
* corner parts to operate at 800MHz
*/
regulator-min-microvolt = <725000>;
regulator-max-microvolt = <1075000>;
};
};
};
&sdhc_1 {
@ -74,10 +28,6 @@
status = "okay";
};
&sleep_clk {
clock-frequency = <32000>;
};
&tlmm {
sdc_default_state: sdc-default-state {
clk-pins {
@ -110,15 +60,4 @@
bias-pull-down;
};
};
spi_0_pins: spi-0-state {
pins = "gpio11", "gpio12", "gpio13", "gpio14";
function = "blsp0_spi";
drive-strength = <8>;
bias-disable;
};
};
&xo_board_clk {
clock-frequency = <24000000>;
};

91
arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
View File

@ -8,69 +8,11 @@
/dts-v1/;
#include "ipq9574.dtsi"
#include "ipq9574-rdp-common.dtsi"
/ {
model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C7";
compatible = "qcom,ipq9574-ap-al02-c7", "qcom,ipq9574";
aliases {
serial0 = &blsp1_uart2;
};
chosen {
stdout-path = "serial0:115200n8";
};
regulator_fixed_3p3: s3300 {
compatible = "regulator-fixed";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
regulator-name = "fixed_3p3";
};
regulator_fixed_0p925: s0925 {
compatible = "regulator-fixed";
regulator-min-microvolt = <925000>;
regulator-max-microvolt = <925000>;
regulator-boot-on;
regulator-always-on;
regulator-name = "fixed_0p925";
};
};
&blsp1_uart2 {
pinctrl-0 = <&uart2_pins>;
pinctrl-names = "default";
status = "okay";
};
&rpm_requests {
regulators {
compatible = "qcom,rpm-mp5496-regulators";
ipq9574_s1: s1 {
/*
* During kernel bootup, the SoC runs at 800MHz with 875mV set by the bootloaders.
* During regulator registration, kernel not knowing the initial voltage,
* considers it as zero and brings up the regulators with minimum supported voltage.
* Update the regulator-min-microvolt with SVS voltage of 725mV so that
* the regulators are brought up with 725mV which is sufficient for all the
* corner parts to operate at 800MHz
*/
regulator-min-microvolt = <725000>;
regulator-max-microvolt = <1075000>;
};
mp5496_l2: l2 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
};
};
&sdhc_1 {
@ -85,10 +27,6 @@
status = "okay";
};
&sleep_clk {
clock-frequency = <32000>;
};
&tlmm {
sdc_default_state: sdc-default-state {
clk-pins {
@ -122,30 +60,3 @@
};
};
};
&usb_0_dwc3 {
dr_mode = "host";
};
&usb_0_qmpphy {
vdda-pll-supply = <&mp5496_l2>;
vdda-phy-supply = <&regulator_fixed_0p925>;
status = "okay";
};
&usb_0_qusbphy {
vdd-supply = <&regulator_fixed_0p925>;
vdda-pll-supply = <&mp5496_l2>;
vdda-phy-dpdm-supply = <&regulator_fixed_3p3>;
status = "okay";
};
&usb3 {
status = "okay";
};
&xo_board_clk {
clock-frequency = <24000000>;
};

65
arch/arm64/boot/dts/qcom/ipq9574-rdp449.dts
View File

@ -8,73 +8,10 @@
/dts-v1/;
#include "ipq9574.dtsi"
#include "ipq9574-rdp-common.dtsi"
/ {
model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C6";
compatible = "qcom,ipq9574-ap-al02-c6", "qcom,ipq9574";
aliases {
serial0 = &blsp1_uart2;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&blsp1_spi0 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
flash@0 {
compatible = "micron,n25q128a11", "jedec,spi-nor";
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <50000000>;
};
};
&blsp1_uart2 {
pinctrl-0 = <&uart2_pins>;
pinctrl-names = "default";
status = "okay";
};
&rpm_requests {
regulators {
compatible = "qcom,rpm-mp5496-regulators";
ipq9574_s1: s1 {
/*
* During kernel bootup, the SoC runs at 800MHz with 875mV set by the bootloaders.
* During regulator registration, kernel not knowing the initial voltage,
* considers it as zero and brings up the regulators with minimum supported voltage.
* Update the regulator-min-microvolt with SVS voltage of 725mV so that
* the regulators are brought up with 725mV which is sufficient for all the
* corner parts to operate at 800MHz
*/
regulator-min-microvolt = <725000>;
regulator-max-microvolt = <1075000>;
};
};
};
&sleep_clk {
clock-frequency = <32000>;
};
&tlmm {
spi_0_pins: spi-0-state {
pins = "gpio11", "gpio12", "gpio13", "gpio14";
function = "blsp0_spi";
drive-strength = <8>;
bias-disable;
};
};
&xo_board_clk {
clock-frequency = <24000000>;
};

65
arch/arm64/boot/dts/qcom/ipq9574-rdp453.dts
View File

@ -8,73 +8,10 @@
/dts-v1/;
#include "ipq9574.dtsi"
#include "ipq9574-rdp-common.dtsi"
/ {
model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C8";
compatible = "qcom,ipq9574-ap-al02-c8", "qcom,ipq9574";
aliases {
serial0 = &blsp1_uart2;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&blsp1_spi0 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
flash@0 {
compatible = "micron,n25q128a11", "jedec,spi-nor";
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <50000000>;
};
};
&blsp1_uart2 {
pinctrl-0 = <&uart2_pins>;
pinctrl-names = "default";
status = "okay";
};
&rpm_requests {
regulators {
compatible = "qcom,rpm-mp5496-regulators";
ipq9574_s1: s1 {
/*
* During kernel bootup, the SoC runs at 800MHz with 875mV set by the bootloaders.
* During regulator registration, kernel not knowing the initial voltage,
* considers it as zero and brings up the regulators with minimum supported voltage.
* Update the regulator-min-microvolt with SVS voltage of 725mV so that
* the regulators are brought up with 725mV which is sufficient for all the
* corner parts to operate at 800MHz
*/
regulator-min-microvolt = <725000>;
regulator-max-microvolt = <1075000>;
};
};
};
&sleep_clk {
clock-frequency = <32000>;
};
&tlmm {
spi_0_pins: spi-0-state {
pins = "gpio11", "gpio12", "gpio13", "gpio14";
function = "blsp0_spi";
drive-strength = <8>;
bias-disable;
};
};
&xo_board_clk {
clock-frequency = <24000000>;
};

66
arch/arm64/boot/dts/qcom/ipq9574-rdp454.dts
View File

@ -8,73 +8,9 @@
/dts-v1/;
#include "ipq9574.dtsi"
#include "ipq9574-rdp-common.dtsi"
/ {
model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C9";
compatible = "qcom,ipq9574-ap-al02-c9", "qcom,ipq9574";
aliases {
serial0 = &blsp1_uart2;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&blsp1_spi0 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
flash@0 {
compatible = "micron,n25q128a11", "jedec,spi-nor";
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <50000000>;
};
};
&blsp1_uart2 {
pinctrl-0 = <&uart2_pins>;
pinctrl-names = "default";
status = "okay";
};
&rpm_requests {
regulators {
compatible = "qcom,rpm-mp5496-regulators";
ipq9574_s1: s1 {
/*
* During kernel bootup, the SoC runs at 800MHz with 875mV set by the bootloaders.
* During regulator registration, kernel not knowing the initial voltage,
* considers it as zero and brings up the regulators with minimum supported voltage.
* Update the regulator-min-microvolt with SVS voltage of 725mV so that
* the regulators are brought up with 725mV which is sufficient for all the
* corner parts to operate at 800MHz
*/
regulator-min-microvolt = <725000>;
regulator-max-microvolt = <1075000>;
};
};
};
&sleep_clk {
clock-frequency = <32000>;
};
&tlmm {
spi_0_pins: spi-0-state {
pins = "gpio11", "gpio12", "gpio13", "gpio14";
function = "blsp0_spi";
drive-strength = <8>;
bias-disable;
};
};
&xo_board_clk {
clock-frequency = <24000000>;
};

25
arch/arm64/boot/dts/qcom/ipq9574.dtsi
View File

@ -106,42 +106,56 @@
};
cpu_opp_table: opp-table-cpu {
compatible = "operating-points-v2";
compatible = "operating-points-v2-kryo-cpu";
opp-shared;
nvmem-cells = <&cpu_speed_bin>;
opp-936000000 {
opp-hz = /bits/ 64 <936000000>;
opp-microvolt = <725000>;
opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
};
opp-1104000000 {
opp-hz = /bits/ 64 <1104000000>;
opp-microvolt = <787500>;
opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
};
opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <862500>;
opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
};
opp-1416000000 {
opp-hz = /bits/ 64 <1416000000>;
opp-microvolt = <862500>;
opp-supported-hw = <0x7>;
clock-latency-ns = <200000>;
};
opp-1488000000 {
opp-hz = /bits/ 64 <1488000000>;
opp-microvolt = <925000>;
opp-supported-hw = <0x7>;
clock-latency-ns = <200000>;
};
opp-1800000000 {
opp-hz = /bits/ 64 <1800000000>;
opp-microvolt = <987500>;
opp-supported-hw = <0x5>;
clock-latency-ns = <200000>;
};
opp-2208000000 {
opp-hz = /bits/ 64 <2208000000>;
opp-microvolt = <1062500>;
opp-supported-hw = <0x1>;
clock-latency-ns = <200000>;
};
};
@ -223,6 +237,11 @@
reg = <0x000a4000 0x5a1>;
#address-cells = <1>;
#size-cells = <1>;
cpu_speed_bin: cpu-speed-bin@15 {
reg = <0x15 0x2>;
bits = <7 2>;
};
};
cryptobam: dma-controller@704000 {
@ -652,8 +671,8 @@
"qcom,ipq6018-apcs-apps-global";
reg = <0x0b111000 0x1000>;
#clock-cells = <1>;
clocks = <&a73pll>, <&xo_board_clk>;
clock-names = "pll", "xo";
clocks = <&a73pll>, <&xo_board_clk>, <&gcc GPLL0>;
clock-names = "pll", "xo", "gpll0";
#mbox-cells = <1>;
};

24
arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts
View File

@ -7,6 +7,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/leds/common.h>
/*
* NOTE: The original firmware from Acer can only boot 32-bit kernels.
@ -83,6 +84,29 @@
};
};
&blsp_i2c4 {
status = "okay";
led-controller@30 {
compatible = "kinetic,ktd2026";
reg = <0x30>;
#address-cells = <1>;
#size-cells = <0>;
led@0 {
reg = <0>;
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_RED>;
};
led@1 {
reg = <1>;
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_GREEN>;
};
};
};
&blsp_i2c5 {
status = "okay";

173
arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts
View File

@ -3,6 +3,8 @@
/dts-v1/;
#include "msm8916-pm8916.dtsi"
#include "msm8916-modem-qdsp6.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
@ -22,6 +24,19 @@
stdout-path = "serial0";
};
reserved-memory {
/delete-node/ reserved@86680000;
/delete-node/ rmtfs@86700000;
rmtfs: rmtfs@86680000 {
compatible = "qcom,rmtfs-mem";
reg = <0x0 0x86680000 0x0 0x160000>;
no-map;
qcom,client-id = <1>;
};
};
gpio-keys {
compatible = "gpio-keys";
@ -50,6 +65,17 @@
};
};
reg_headphones_avdd: regulator-headphones-avdd {
compatible = "regulator-fixed";
regulator-name = "headphones_avdd";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
gpio = <&tlmm 121 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-0 = <&headphones_avdd_default>;
pinctrl-names = "default";
};
usb_id: usb-id {
compatible = "linux,extcon-usb-gpio";
id-gpios = <&tlmm 69 GPIO_ACTIVE_HIGH>;
@ -58,8 +84,41 @@
};
};
&blsp_uart2 {
&blsp_i2c3 {
status = "okay";
headphones: audio-codec@10 {
compatible = "asahi-kasei,ak4375";
reg = <0x10>;
avdd-supply = <&reg_headphones_avdd>;
tvdd-supply = <&pm8916_l6>;
pdn-gpios = <&tlmm 114 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&headphones_pdn_default>;
pinctrl-names = "default";
#sound-dai-cells = <0>;
};
speaker_codec_top: audio-codec@34 {
compatible = "nxp,tfa9897";
reg = <0x34>;
vddd-supply = <&pm8916_l6>;
rcv-gpios = <&tlmm 50 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&speaker_top_default>;
pinctrl-names = "default";
sound-name-prefix = "Speaker Top";
#sound-dai-cells = <0>;
};
speaker_codec_bottom: audio-codec@36 {
compatible = "nxp,tfa9897";
reg = <0x36>;
vddd-supply = <&pm8916_l6>;
rcv-gpios = <&tlmm 111 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&speaker_bottom_default>;
pinctrl-names = "default";
sound-name-prefix = "Speaker Bottom";
#sound-dai-cells = <0>;
};
};
&blsp_i2c4 {
@ -153,6 +212,22 @@
};
};
&blsp_uart2 {
status = "okay";
};
&mpss_mem {
reg = <0x0 0x86800000 0x0 0x5000000>;
};
&pm8916_codec {
qcom,micbias1-ext-cap;
qcom,micbias-lvl = <2800>;
qcom,mbhc-vthreshold-low = <75 100 120 180 500>;
qcom,mbhc-vthreshold-high = <75 100 120 180 500>;
qcom,hphl-jack-type-normally-open;
};
&pm8916_resin {
status = "okay";
linux,code = <KEY_VOLUMEDOWN>;
@ -169,6 +244,17 @@
status = "okay";
};
&q6afedai {
dai@18 {
reg = <SECONDARY_MI2S_RX>;
qcom,sd-lines = <0>;
};
dai@22 {
reg = <QUATERNARY_MI2S_RX>;
qcom,sd-lines = <0>;
};
};
&sdhc_1 {
status = "okay";
};
@ -183,6 +269,54 @@
cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
};
&sound {
/* Add pin switches for speakers to allow disabling them individually */
model = "alcatel-idol3";
widgets =
"Speaker", "Speaker Top",
"Speaker", "Speaker Bottom";
pin-switches = "Speaker Top", "Speaker Bottom";
audio-routing =
"Speaker Top", "Speaker Top OUT",
"Speaker Bottom", "Speaker Bottom OUT",
"AMIC1", "MIC BIAS External1",
"AMIC2", "MIC BIAS Internal2",
"AMIC3", "MIC BIAS External1";
pinctrl-0 = <&cdc_pdm_default &pri_mi2s_default &pri_mi2s_ws_default &sec_mi2s_default>;
pinctrl-1 = <&cdc_pdm_sleep &pri_mi2s_sleep &pri_mi2s_ws_sleep &sec_mi2s_sleep>;
pinctrl-names = "default", "sleep";
sound_link_backend2: backend2-dai-link {
link-name = "Quaternary MI2S";
cpu {
sound-dai = <&q6afedai QUATERNARY_MI2S_RX>;
};
platform {
sound-dai = <&q6routing>;
};
codec {
sound-dai = <&speaker_codec_top>, <&speaker_codec_bottom>;
};
};
};
&sound_link_backend0 {
/* Primary MI2S is not used, replace with Secondary MI2S for headphones */
link-name = "Secondary MI2S";
cpu {
sound-dai = <&q6afedai SECONDARY_MI2S_RX>;
};
platform {
sound-dai = <&q6routing>;
};
codec {
sound-dai = <&headphones>;
};
};
&usb {
status = "okay";
extcon = <&usb_id>, <&usb_id>;
@ -212,6 +346,15 @@
status = "okay";
};
/* Only some of the pins are used */
&pri_mi2s_default {
pins = "gpio113", "gpio115";
};
&pri_mi2s_sleep {
pins = "gpio113", "gpio115";
};
&tlmm {
accel_int_default: accel-int-default-state {
pins = "gpio31";
@ -245,6 +388,20 @@
bias-disable;
};
headphones_avdd_default: headphones-avdd-default-state {
pins = "gpio121";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
headphones_pdn_default: headphones-pdn-default-state {
pins = "gpio114";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
/*
* The OEM wired an additional GPIO to be asserted so that
* the si-en,sn3190 LED IC works. Since this GPIO is not
@ -291,6 +448,20 @@
bias-disable;
};
speaker_bottom_default: speaker-bottom-default-state {
pins = "gpio111";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
speaker_top_default: speaker-top-default-state {
pins = "gpio50";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
ts_int_reset_default: ts-int-reset-default-state {
pins = "gpio13", "gpio100";
function = "gpio";

21
arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts
View File

@ -3,6 +3,8 @@
/dts-v1/;
#include "msm8916-pm8916.dtsi"
#include "msm8916-modem-qdsp6.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
@ -130,6 +132,18 @@
status = "okay";
};
&mpss_mem {
reg = <0x0 0x86800000 0x0 0x5500000>;
};
&pm8916_codec {
qcom,micbias-lvl = <2800>;
qcom,mbhc-vthreshold-low = <75 150 237 450 500>;
qcom,mbhc-vthreshold-high = <75 150 237 450 500>;
qcom,micbias1-ext-cap;
qcom,hphl-jack-type-normally-open;
};
&pm8916_rpm_regulators {
pm8916_l17: l17 {
regulator-min-microvolt = <2850000>;
@ -151,6 +165,13 @@
cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
};
&sound {
audio-routing =
"AMIC1", "MIC BIAS External1",
"AMIC2", "MIC BIAS Internal2",
"AMIC3", "MIC BIAS External1";
};
&usb {
status = "okay";
extcon = <&usb_id>, <&usb_id>;

75
arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts
View File

@ -3,6 +3,8 @@
/dts-v1/;
#include "msm8916-pm8916.dtsi"
#include "msm8916-modem-qdsp6.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
@ -25,17 +27,45 @@
/*
* For some reason, the signed wcnss firmware is not relocatable.
* It must be loaded at 0x8b600000. All other firmware is relocatable,
* so place wcnss at the fixed address and then all other firmware
* regions will be automatically allocated at a fitting place.
* It must be loaded at 0x8b600000. Unfortunately, this also means that
* mpss_mem does not fit when loaded to the typical address at 0x86800000.
*
* Load wcnss_mem to the fixed address and relocate mpss_mem to the next
* working higher address. For some reason the modem firmware does not
* boot when placed at 0x8a800000 to 0x8e800000.
*/
reserved-memory {
/delete-node/ mpss@86800000;
/delete-node/ wcnss;
wcnss_mem: wcnss@8b600000 {
reg = <0x0 0x8b600000 0x0 0x600000>;
no-map;
};
mpss_mem: mpss@8e800000 {
reg = <0x0 0x8e800000 0x0 0x5000000>;
no-map;
};
};
battery: battery {
compatible = "simple-battery";
voltage-min-design-microvolt = <3400000>;
voltage-max-design-microvolt = <4350000>;
energy-full-design-microwatt-hours = <9500000>;
charge-full-design-microamp-hours = <2500000>;
ocv-capacity-celsius = <25>;
ocv-capacity-table-0 = <4330000 100>, <4265000 95>,
<4208000 90>, <4153000 85>, <4100000 80>, <4049000 75>,
<4001000 70>, <3962000 65>, <3919000 60>, <3872000 55>,
<3839000 50>, <3817000 45>, <3798000 40>, <3783000 35>,
<3767000 30>, <3747000 25>, <3729000 20>, <3709000 16>,
<3688000 13>, <3681000 11>, <3680000 10>, <3679000 9>,
<3677000 8>, <3674000 7>, <3666000 6>, <3641000 5>,
<3597000 4>, <3537000 3>, <3457000 2>, <3336000 1>,
<3000000 0>;
};
gpio-keys {
@ -93,6 +123,7 @@
#size-cells = <0>;
vcc-supply = <&pm8916_l17>;
vio-supply = <&pm8916_l6>;
led@0 {
reg = <0>;
@ -225,6 +256,29 @@
status = "okay";
};
&pm8916_bms {
status = "okay";
monitored-battery = <&battery>;
power-supplies = <&pm8916_charger>;
};
&pm8916_charger {
status = "okay";
monitored-battery = <&battery>;
qcom,fast-charge-safe-current = <900000>;
qcom,fast-charge-safe-voltage = <4300000>;
};
&pm8916_codec {
qcom,micbias-lvl = <2800>;
qcom,mbhc-vthreshold-low = <75 150 237 450 500>;
qcom,mbhc-vthreshold-high = <75 150 237 450 500>;
qcom,hphl-jack-type-normally-open;
};
&pm8916_resin {
status = "okay";
linux,code = <KEY_VOLUMEDOWN>;
@ -237,10 +291,6 @@
};
};
&pm8916_usbin {
status = "okay";
};
&pm8916_vib {
status = "okay";
};
@ -254,14 +304,21 @@
non-removable;
};
&sound {
audio-routing =
"AMIC1", "MIC BIAS Internal1",
"AMIC2", "MIC BIAS Internal2",
"AMIC3", "MIC BIAS Internal3";
};
&usb {
status = "okay";
dr_mode = "peripheral";
extcon = <&pm8916_usbin>;
extcon = <&pm8916_charger>;
};
&usb_hs_phy {
extcon = <&pm8916_usbin>;
extcon = <&pm8916_charger>;
};
&venus {

103
arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts
View File

@ -3,9 +3,12 @@
/dts-v1/;
#include "msm8916-pm8916.dtsi"
#include "msm8916-modem-qdsp6.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
/ {
model = "BQ Aquaris X5 (Longcheer L8910)";
@ -22,6 +25,16 @@
stdout-path = "serial0";
};
speaker_amp: audio-amplifier {
compatible = "awinic,aw8738";
mode-gpios = <&tlmm 114 GPIO_ACTIVE_HIGH>;
awinic,mode = <5>;
sound-name-prefix = "Speaker Amp";
pinctrl-0 = <&spk_ext_pa_default>;
pinctrl-names = "default";
};
flash-led-controller {
compatible = "ocs,ocp8110";
enable-gpios = <&tlmm 49 GPIO_ACTIVE_HIGH>;
@ -74,6 +87,46 @@
};
};
&blsp_i2c2 {
status = "okay";
led-controller@30 {
compatible = "kinetic,ktd2026";
reg = <0x30>;
#address-cells = <1>;
#size-cells = <0>;
vin-supply = <&pm8916_l17>;
vio-supply = <&pm8916_l6>;
pinctrl-0 = <&status_led_default>;
pinctrl-names = "default";
multi-led {
color = <LED_COLOR_ID_RGB>;
function = LED_FUNCTION_STATUS;
#address-cells = <1>;
#size-cells = <0>;
led@0 {
reg = <0>;
color = <LED_COLOR_ID_RED>;
};
led@1 {
reg = <1>;
color = <LED_COLOR_ID_GREEN>;
};
led@2 {
reg = <2>;
color = <LED_COLOR_ID_BLUE>;
};
};
};
};
&blsp_i2c3 {
status = "okay";
@ -107,6 +160,27 @@
status = "okay";
};
&mpss_mem {
reg = <0x0 0x86800000 0x0 0x5000000>;
};
&pm8916_codec {
qcom,micbias-lvl = <2800>;
qcom,mbhc-vthreshold-low = <75 100 120 180 500>;
qcom,mbhc-vthreshold-high = <75 100 120 180 500>;
qcom,hphl-jack-type-normally-open;
};
&pm8916_gpios {
status_led_default: status-led-default-state {
pins = "gpio3";
function = PMIC_GPIO_FUNC_NORMAL;
power-source = <PM8916_GPIO_VPH>;
bias-disable;
output-high;
};
};
&pm8916_resin {
status = "okay";
linux,code = <KEY_VOLUMEDOWN>;
@ -137,6 +211,28 @@
cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
};
&sound {
/*
* Provide widgets/pin-switches to allow enabling speaker separately.
* The hardware does not provide a way to disable the output via the
* headphone jack when the speaker is enabled.
*/
model = "bq-paella";
widgets =
"Speaker", "Speaker",
"Headphone", "Headphones";
pin-switches = "Speaker";
audio-routing =
"Speaker", "Speaker Amp OUT",
"Speaker Amp IN", "HPH_R",
"Headphones", "HPH_L",
"Headphones", "HPH_R",
"AMIC1", "MIC BIAS External1",
"AMIC2", "MIC BIAS Internal2",
"AMIC3", "MIC BIAS External1";
aux-devs = <&speaker_amp>;
};
&usb {
status = "okay";
extcon = <&usb_id>, <&usb_id>;
@ -205,6 +301,13 @@
bias-disable;
};
spk_ext_pa_default: spk-ext-pa-default-state {
pins = "gpio114";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
usb_id_default: usb-id-default-state {
pins = "gpio110";
function = "gpio";

148
arch/arm64/boot/dts/qcom/msm8916-modem-qdsp6.dtsi Normal file
View File

@ -0,0 +1,148 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
/*
* msm8916-modem-qdsp6.dtsi describes the typical modem setup on MSM8916 devices
* (or similar SoCs) with audio routed via the QDSP6 services provided by the
* modem firmware. The digital/analog codec in the SoC/PMIC is used by default,
* but boards can define additional codecs by adding additional backend DAI links.
*/
#include <dt-bindings/sound/qcom,q6afe.h>
#include <dt-bindings/sound/qcom,q6asm.h>
&apr {
status = "okay";
};
&bam_dmux {
status = "okay";
};
&bam_dmux_dma {
status = "okay";
};
&lpass {
status = "reserved"; /* Controlled by QDSP6 */
};
&lpass_codec {
status = "okay";
};
&mba_mem {
status = "okay";
};
&mpss {
status = "okay";
};
&mpss_mem {
status = "okay";
};
&pm8916_codec {
status = "okay";
};
&q6afedai {
dai@16 {
reg = <PRIMARY_MI2S_RX>;
qcom,sd-lines = <0 1>;
};
dai@20 {
reg = <TERTIARY_MI2S_TX>;
qcom,sd-lines = <0 1>;
};
};
&q6asmdai {
dai@0 {
reg = <0>;
direction = <Q6ASM_DAI_RX>;
};
dai@1 {
reg = <1>;
direction = <Q6ASM_DAI_TX>;
};
dai@2 {
reg = <2>;
direction = <Q6ASM_DAI_RX>;
};
dai@3 {
reg = <3>;
direction = <Q6ASM_DAI_RX>;
is-compress-dai;
};
};
&sound {
compatible = "qcom,msm8916-qdsp6-sndcard";
model = "msm8916";
pinctrl-0 = <&cdc_pdm_default>;
pinctrl-1 = <&cdc_pdm_sleep>;
pinctrl-names = "default", "sleep";
status = "okay";
frontend0-dai-link {
link-name = "MultiMedia1";
cpu {
sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>;
};
};
frontend1-dai-link {
link-name = "MultiMedia2";
cpu {
sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA2>;
};
};
frontend2-dai-link {
link-name = "MultiMedia3";
cpu {
sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA3>;
};
};
frontend3-dai-link {
link-name = "MultiMedia4";
cpu {
sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA4>;
};
};
sound_link_backend0: backend0-dai-link {
link-name = "Primary MI2S";
cpu {
sound-dai = <&q6afedai PRIMARY_MI2S_RX>;
};
platform {
sound-dai = <&q6routing>;
};
codec {
sound-dai = <&lpass_codec 0>, <&pm8916_codec 0>;
};
};
sound_link_backend1: backend1-dai-link {
link-name = "Tertiary MI2S";
cpu {
sound-dai = <&q6afedai TERTIARY_MI2S_TX>;
};
platform {
sound-dai = <&q6routing>;
};
codec {
sound-dai = <&lpass_codec 1>, <&pm8916_codec 1>;
};
};
};

71
arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi
View File

@ -1,10 +1,13 @@
// SPDX-License-Identifier: GPL-2.0-only
#include "msm8916-pm8916.dtsi"
#include "msm8916-modem-qdsp6.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
#include <dt-bindings/sound/apq8016-lpass.h>
/ {
aliases {
@ -196,6 +199,18 @@
};
};
&blsp_i2c1 {
status = "okay";
speaker_codec: audio-codec@34 {
compatible = "nxp,tfa9895";
reg = <0x34>;
vddd-supply = <&pm8916_l5>;
sound-name-prefix = "Speaker";
#sound-dai-cells = <0>;
};
};
&blsp_i2c2 {
status = "okay";
@ -243,6 +258,25 @@
status = "okay";
};
/*
* For some reason the speaker amplifier is connected to the second SD line
* (MI2S_2_D1) instead of the first (MI2S_2_D0). This must be configured in the
* device tree, otherwise audio will seemingly play fine on the wrong SD line
* but the speaker stays silent.
*
* When routing audio via QDSP6 (the default) the &lpass node is reserved and
* the definitions from &q6afedai are used. When the modem is disabled audio can
* be alternatively routed directly to the LPASS hardware with reduced latency.
* The definitions for &lpass are here for completeness to simplify changing the
* setup with minor changes to the DT (either manually or with DT overlays).
*/
&lpass {
dai-link@3 {
reg = <MI2S_QUATERNARY>;
qcom,playback-sd-lines = <1>;
};
};
&mdss {
status = "okay";
};
@ -253,6 +287,10 @@
pinctrl-1 = <&mdss_sleep>;
};
&mpss_mem {
reg = <0x0 0x86800000 0x0 0x5400000>;
};
&pm8916_resin {
status = "okay";
linux,code = <KEY_VOLUMEDOWN>;
@ -265,6 +303,13 @@
};
};
&q6afedai {
dai@22 {
reg = <QUATERNARY_MI2S_RX>;
qcom,sd-lines = <1>;
};
};
&sdhc_1 {
status = "okay";
};
@ -279,6 +324,32 @@
cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
};
&sound {
model = "samsung-a2015";
audio-routing =
"AMIC1", "MIC BIAS External1",
"AMIC2", "MIC BIAS Internal2",
"AMIC3", "MIC BIAS External1";
pinctrl-0 = <&cdc_pdm_default &sec_mi2s_default>;
pinctrl-1 = <&cdc_pdm_sleep &sec_mi2s_sleep>;
pinctrl-names = "default", "sleep";
sound_link_backend2: backend2-dai-link {
link-name = "Quaternary MI2S";
cpu {
sound-dai = <&q6afedai QUATERNARY_MI2S_RX>;
};
platform {
sound-dai = <&q6routing>;
};
codec {
sound-dai = <&speaker_codec>;
};
};
};
&usb {
status = "okay";
extcon = <&muic>, <&muic>;

10
arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts
View File

@ -49,11 +49,6 @@
};
};
&touchkey {
vcc-supply = <&reg_touch_key>;
vdd-supply = <&reg_key_led>;
};
&accelerometer {
mount-matrix = "0", "1", "0",
"1", "0", "0",
@ -108,6 +103,11 @@
remote-endpoint = <&panel_in>;
};
&touchkey {
vcc-supply = <&reg_touch_key>;
vdd-supply = <&reg_key_led>;
};
&vibrator {
status = "okay";
};

4
arch/arm64/boot/dts/qcom/msm8916-samsung-e2015-common.dtsi
View File

@ -65,6 +65,10 @@
};
};
&mpss_mem {
reg = <0x0 0x86800000 0x0 0x5a00000>;
};
&reg_motor_vdd {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;

4
arch/arm64/boot/dts/qcom/msm8916-samsung-grandmax.dts
View File

@ -49,6 +49,10 @@
status = "disabled";
};
&sound {
model = "samsung-gmax"; /* No secondary microphone */
};
&tlmm {
gpio_leds_default: gpio-led-default-state {
pins = "gpio60";

92
arch/arm64/boot/dts/qcom/msm8916-samsung-gt5-common.dtsi
View File

@ -3,9 +3,12 @@
/dts-v1/;
#include "msm8916-pm8916.dtsi"
#include "msm8916-modem-qdsp6.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/sound/apq8016-lpass.h>
/ {
aliases {
@ -65,25 +68,6 @@
};
};
&blsp_i2c4 {
status = "okay";
fuelgauge@36 {
compatible = "maxim,max77849-battery";
reg = <0x36>;
maxim,rsns-microohm = <10000>;
maxim,over-heat-temp = <600>;
maxim,over-volt = <4400>;
interrupt-parent = <&tlmm>;
interrupts = <121 IRQ_TYPE_EDGE_FALLING>;
pinctrl-0 = <&fuelgauge_int_default>;
pinctrl-names = "default";
};
};
&blsp_i2c2 {
status = "okay";
@ -112,10 +96,52 @@
};
};
&blsp_i2c4 {
status = "okay";
fuelgauge@36 {
compatible = "maxim,max77849-battery";
reg = <0x36>;
maxim,rsns-microohm = <10000>;
maxim,over-heat-temp = <600>;
maxim,over-volt = <4400>;
interrupt-parent = <&tlmm>;
interrupts = <121 IRQ_TYPE_EDGE_FALLING>;
pinctrl-0 = <&fuelgauge_int_default>;
pinctrl-names = "default";
};
};
&blsp_uart2 {
status = "okay";
};
/*
* For some reason the speaker amplifier is connected to the second SD line
* (MI2S_2_D1) instead of the first (MI2S_2_D0). This must be configured in the
* device tree, otherwise audio will seemingly play fine on the wrong SD line
* but the speaker stays silent.
*
* When routing audio via QDSP6 (the default) the &lpass node is reserved and
* the definitions from &q6afedai are used. When the modem is disabled audio can
* be alternatively routed directly to the LPASS hardware with reduced latency.
* The definitions for &lpass are here for completeness to simplify changing the
* setup with minor changes to the DT (either manually or with DT overlays).
*/
&lpass {
dai-link@3 {
reg = <MI2S_QUATERNARY>;
qcom,playback-sd-lines = <1>;
};
};
&mpss_mem {
reg = <0x0 0x86800000 0x0 0x5400000>;
};
&pm8916_resin {
linux,code = <KEY_VOLUMEDOWN>;
status = "okay";
@ -133,6 +159,13 @@
status = "okay";
};
&q6afedai {
dai@22 {
reg = <QUATERNARY_MI2S_RX>;
qcom,sd-lines = <1>;
};
};
&sdhc_1 {
status = "okay";
};
@ -147,6 +180,27 @@
status = "okay";
};
&sound {
audio-routing =
"AMIC1", "MIC BIAS External1",
"AMIC2", "MIC BIAS Internal2",
"AMIC3", "MIC BIAS External1";
sound_link_backend2: backend2-dai-link {
link-name = "Quaternary MI2S";
cpu {
sound-dai = <&q6afedai QUATERNARY_MI2S_RX>;
};
platform {
sound-dai = <&q6routing>;
};
codec {
sound-dai = <&speaker_codec>;
};
};
};
&usb {
dr_mode = "peripheral";
extcon = <&pm8916_usbin>;

26
arch/arm64/boot/dts/qcom/msm8916-samsung-gt510.dts
View File

@ -9,6 +9,14 @@
compatible = "samsung,gt510", "qcom,msm8916";
chassis-type = "tablet";
speaker_codec: audio-codec {
compatible = "maxim,max98357a";
sdmode-gpios = <&tlmm 55 GPIO_ACTIVE_HIGH>;
#sound-dai-cells = <0>;
pinctrl-0 = <&audio_sdmode_default>;
pinctrl-names = "default";
};
clk_pwm: pwm {
compatible = "clk-pwm";
#pwm-cells = <2>;
@ -112,6 +120,10 @@
};
};
&gpu {
status = "okay";
};
&mdss {
status = "okay";
};
@ -142,7 +154,21 @@
remote-endpoint = <&panel_in>;
};
&sound {
model = "samsung-gt510";
pinctrl-0 = <&cdc_pdm_default &sec_mi2s_default>;
pinctrl-1 = <&cdc_pdm_sleep &sec_mi2s_sleep>;
pinctrl-names = "default", "sleep";
};
&tlmm {
audio_sdmode_default: audio-sdmode-default-state {
pins = "gpio55";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
buckbooster_en_default: buckbooster-en-default-state {
pins = "gpio51";
function = "gpio";

46
arch/arm64/boot/dts/qcom/msm8916-samsung-gt58.dts
View File

@ -35,6 +35,26 @@
pinctrl-names = "default";
};
i2c-amplifier {
compatible = "i2c-gpio";
sda-gpios = <&tlmm 55 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
scl-gpios = <&tlmm 56 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
pinctrl-0 = <&amp_i2c_default>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
speaker_codec: audio-codec@34 {
compatible = "nxp,tfa9895";
reg = <0x34>;
vddd-supply = <&pm8916_l5>;
sound-name-prefix = "Speaker";
#sound-dai-cells = <0>;
};
};
vibrator {
compatible = "gpio-vibrator";
enable-gpios = <&tlmm 76 GPIO_ACTIVE_HIGH>;
@ -64,6 +84,10 @@
};
};
&gpu {
status = "okay";
};
&mdss {
status = "okay";
};
@ -94,7 +118,21 @@
remote-endpoint = <&panel_in>;
};
&sound {
model = "samsung-a2015";
pinctrl-0 = <&cdc_pdm_default &sec_mi2s_default &secondary_mic_default>;
pinctrl-1 = <&cdc_pdm_sleep &sec_mi2s_sleep &secondary_mic_default>;
pinctrl-names = "default", "sleep";
};
&tlmm {
amp_i2c_default: amp-i2c-default-state {
pins = "gpio55", "gpio56";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
buckbooster_en_default: buckbooster-en-default-state {
pins = "gpio8";
function = "gpio";
@ -123,6 +161,14 @@
bias-disable;
};
secondary_mic_default: secondary-mic-default-state {
pins = "gpio98";
function = "gpio";
drive-strength = <2>;
bias-disable;
output-high;
};
tsp_int_default: tsp-int-default-state {
pins = "gpio13";
function = "gpio";

14
arch/arm64/boot/dts/qcom/msm8916-samsung-j5-common.dtsi
View File

@ -1,6 +1,8 @@
// SPDX-License-Identifier: GPL-2.0-only
#include "msm8916-pm8916.dtsi"
#include "msm8916-modem-qdsp6.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
@ -135,6 +137,10 @@
status = "okay";
};
&mpss_mem {
reg = <0x0 0x86800000 0x0 0x5800000>;
};
&pm8916_resin {
status = "okay";
linux,code = <KEY_VOLUMEDOWN>;
@ -154,6 +160,14 @@
cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
};
&sound {
model = "msm8916-1mic";
audio-routing =
"AMIC1", "MIC BIAS External1",
"AMIC2", "MIC BIAS Internal2",
"AMIC3", "MIC BIAS External1";
};
&usb {
extcon = <&muic>, <&muic>;
status = "okay";

4
arch/arm64/boot/dts/qcom/msm8916-samsung-j5.dts
View File

@ -19,6 +19,10 @@
status = "disabled";
};
&pm8916_codec {
qcom,micbias1-ext-cap;
};
&touchscreen {
/* FIXME: Missing sm5703-mfd driver to power up vdd-supply */
};

13
arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts
View File

@ -6,6 +6,8 @@
/dts-v1/;
#include "msm8916-pm8916.dtsi"
#include "msm8916-modem-qdsp6.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
@ -319,6 +321,10 @@
status = "okay";
};
&mpss_mem {
reg = <0x0 0x86800000 0x0 0x5a00000>;
};
&pm8916_resin {
status = "okay";
linux,code = <KEY_VOLUMEDOWN>;
@ -350,6 +356,13 @@
no-1-8-v;
};
&sound {
audio-routing =
"AMIC1", "MIC BIAS External1",
"AMIC2", "MIC BIAS Internal2",
"AMIC3", "MIC BIAS External1";
};
&usb {
status = "okay";
extcon = <&muic>, <&muic>;

8
arch/arm64/boot/dts/qcom/msm8916-thwc-uf896.dts
View File

@ -13,16 +13,16 @@
gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
};
&led_r {
gpios = <&tlmm 82 GPIO_ACTIVE_HIGH>;
&led_b {
gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>;
};
&led_g {
gpios = <&tlmm 83 GPIO_ACTIVE_HIGH>;
};
&led_b {
gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>;
&led_r {
gpios = <&tlmm 82 GPIO_ACTIVE_HIGH>;
};
&button_default {

8
arch/arm64/boot/dts/qcom/msm8916-thwc-ufi001c.dts
View File

@ -13,16 +13,16 @@
gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>;
};
&led_r {
gpios = <&tlmm 22 GPIO_ACTIVE_HIGH>;
&led_b {
gpios = <&tlmm 20 GPIO_ACTIVE_HIGH>;
};
&led_g {
gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>;
};
&led_b {
gpios = <&tlmm 20 GPIO_ACTIVE_HIGH>;
&led_r {
gpios = <&tlmm 22 GPIO_ACTIVE_HIGH>;
};
&mpss {

75
arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts
View File

@ -6,6 +6,8 @@
/dts-v1/;
#include "msm8916-pm8916.dtsi"
#include "msm8916-modem-qdsp6.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
@ -25,6 +27,28 @@
stdout-path = "serial0";
};
speaker_amp: audio-amplifier {
compatible = "simple-audio-amplifier";
enable-gpios = <&tlmm 117 GPIO_ACTIVE_HIGH>;
sound-name-prefix = "Speaker Amp";
pinctrl-0 = <&speaker_amp_default>;
pinctrl-names = "default";
};
/*
* This seems to be actually an analog switch that either routes audio
* to the headphone jack or nowhere. Given that we need to enable a GPIO
* to get sound on headphones, modelling it as simple-audio-amplifier
* works just fine.
*/
headphones_switch: audio-switch {
compatible = "simple-audio-amplifier";
enable-gpios = <&tlmm 8 GPIO_ACTIVE_HIGH>;
sound-name-prefix = "Headphones Switch";
pinctrl-0 = <&headphones_switch_default>;
pinctrl-names = "default";
};
flash-led-controller {
compatible = "ocs,ocp8110";
enable-gpios = <&tlmm 31 GPIO_ACTIVE_HIGH>;
@ -118,6 +142,7 @@
#size-cells = <0>;
vcc-supply = <&pm8916_l16>;
vio-supply = <&pm8916_l5>;
led@0 {
reg = <0>;
@ -146,6 +171,18 @@
status = "okay";
};
&mpss_mem {
reg = <0x0 0x86800000 0x0 0x5100000>;
};
&pm8916_codec {
qcom,micbias1-ext-cap;
qcom,micbias-lvl = <2800>;
qcom,mbhc-vthreshold-low = <75 100 120 180 500>;
qcom,mbhc-vthreshold-high = <75 100 120 180 500>;
qcom,hphl-jack-type-normally-open;
};
&pm8916_resin {
status = "okay";
linux,code = <KEY_VOLUMEDOWN>;
@ -180,6 +217,30 @@
non-removable;
};
&sound {
/*
* Provide widgets/pin-switches to allow enabling speaker and headphones
* separately. Both are routed via the HPH_L/HPH_R pins of the codec.
*/
model = "wt88047";
widgets =
"Speaker", "Speaker",
"Headphone", "Headphones";
pin-switches = "Speaker", "Headphones";
audio-routing =
"Speaker", "Speaker Amp OUTL",
"Speaker", "Speaker Amp OUTR",
"Speaker Amp INL", "HPH_R",
"Speaker Amp INR", "HPH_R",
"Headphones", "Headphones Switch OUTL",
"Headphones", "Headphones Switch OUTR",
"Headphones Switch INL", "HPH_L",
"Headphones Switch INR", "HPH_R",
"AMIC1", "MIC BIAS External1",
"AMIC2", "MIC BIAS Internal2";
aux-devs = <&speaker_amp>, <&headphones_switch>;
};
&usb {
status = "okay";
extcon = <&usb_id>, <&usb_id>;
@ -226,6 +287,13 @@
bias-pull-up;
};
headphones_switch_default: headphones-switch-default-state {
pins = "gpio8";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
imu_default: imu-default-state {
pins = "gpio115";
function = "gpio";
@ -234,6 +302,13 @@
bias-disable;
};
speaker_amp_default: speaker-amp-default-state {
pins = "gpio117";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
touchscreen_default: touchscreen-default-state {
touchscreen-pins {
pins = "gpio13";

8
arch/arm64/boot/dts/qcom/msm8916-yiming-uz801v3.dts
View File

@ -13,16 +13,16 @@
gpios = <&tlmm 23 GPIO_ACTIVE_LOW>;
};
&led_r {
gpios = <&tlmm 7 GPIO_ACTIVE_HIGH>;
&led_b {
gpios = <&tlmm 6 GPIO_ACTIVE_HIGH>;
};
&led_g {
gpios = <&tlmm 8 GPIO_ACTIVE_HIGH>;
};
&led_b {
gpios = <&tlmm 6 GPIO_ACTIVE_HIGH>;
&led_r {
gpios = <&tlmm 7 GPIO_ACTIVE_HIGH>;
};
&button_default {

50
arch/arm64/boot/dts/qcom/msm8916.dtsi
View File

@ -10,6 +10,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/reset/qcom,gcc-msm8916.h>
#include <dt-bindings/soc/qcom,apr.h>
#include <dt-bindings/thermal/thermal.h>
/ {
@ -1989,6 +1990,54 @@
label = "hexagon";
apr: apr {
compatible = "qcom,apr-v2";
qcom,smd-channels = "apr_audio_svc";
qcom,domain = <APR_DOMAIN_ADSP>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
q6core: service@3 {
compatible = "qcom,q6core";
reg = <APR_SVC_ADSP_CORE>;
};
q6afe: service@4 {
compatible = "qcom,q6afe";
reg = <APR_SVC_AFE>;
q6afedai: dais {
compatible = "qcom,q6afe-dais";
#address-cells = <1>;
#size-cells = <0>;
#sound-dai-cells = <1>;
};
};
q6asm: service@7 {
compatible = "qcom,q6asm";
reg = <APR_SVC_ASM>;
q6asmdai: dais {
compatible = "qcom,q6asm-dais";
#address-cells = <1>;
#size-cells = <0>;
#sound-dai-cells = <1>;
};
};
q6adm: service@8 {
compatible = "qcom,q6adm";
reg = <APR_SVC_ADM>;
q6routing: routing {
compatible = "qcom,q6adm-routing";
#sound-dai-cells = <0>;
};
};
};
fastrpc {
compatible = "qcom,fastrpc";
qcom,smd-channels = "fastrpcsmd-apps-dsp";
@ -2106,6 +2155,7 @@
clock-names = "bam_clk";
#dma-cells = <1>;
qcom,ee = <0>;
qcom,controlled-remotely;
};
blsp_uart1: serial@78af000 {

242
arch/arm64/boot/dts/qcom/msm8939-huawei-kiwi.dts Normal file
View File

@ -0,0 +1,242 @@
// SPDX-License-Identifier: GPL-2.0-only
/dts-v1/;
#include "msm8939-pm8916.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Huawei Honor 5X / GR5 (2016)";
compatible = "huawei,kiwi", "qcom,msm8939";
chassis-type = "handset";
aliases {
mmc0 = &sdhc_1; /* SDC1 eMMC slot */
mmc1 = &sdhc_2; /* SDC2 SD card slot */
serial0 = &blsp_uart2;
};
chosen {
stdout-path = "serial0";
};
reserved-memory {
qseecom_mem: qseecom@84a00000 {
reg = <0x0 0x84a00000 0x0 0x1600000>;
no-map;
};
};
gpio-hall-sensor {
compatible = "gpio-keys";
pinctrl-0 = <&gpio_hall_sensor_default>;
pinctrl-names = "default";
label = "GPIO Hall Effect Sensor";
event-hall-sensor {
label = "Hall Effect Sensor";
gpios = <&tlmm 69 GPIO_ACTIVE_LOW>;
linux,input-type = <EV_SW>;
linux,code = <SW_LID>;
linux,can-disable;
};
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-0 = <&gpio_keys_default>;
pinctrl-names = "default";
label = "GPIO Buttons";
button-volume-up {
label = "Volume Up";
gpios = <&tlmm 107 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEUP>;
};
};
usb_id: usb-id {
compatible = "linux,extcon-usb-gpio";
id-gpios = <&tlmm 110 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&usb_id_default>;
pinctrl-names = "default";
};
};
&blsp_i2c2 {
status = "okay";
accelerometer@1e {
compatible = "kionix,kx023-1025";
reg = <0x1e>;
vdd-supply = <&pm8916_l17>;
vddio-supply = <&pm8916_l6>;
pinctrl-0 = <&accel_int_default>;
pinctrl-names = "default";
mount-matrix = "-1", "0", "0",
"0", "1", "0",
"0", "0", "1";
};
proximity@39 {
compatible = "avago,apds9930";
reg = <0x39>;
interrupt-parent = <&tlmm>;
interrupts = <113 IRQ_TYPE_EDGE_FALLING>;
vdd-supply = <&pm8916_l17>;
vddio-supply = <&pm8916_l6>;
led-max-microamp = <25000>;
amstaos,proximity-diodes = <0>;
pinctrl-0 = <&prox_irq_default>;
pinctrl-names = "default";
};
};
&blsp_i2c5 {
status = "okay";
touchscreen@1c {
compatible = "cypress,tt21000";
reg = <0x1c>;
interrupt-parent = <&tlmm>;
interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
reset-gpios = <&tlmm 12 GPIO_ACTIVE_LOW>;
/*
* NOTE: vdd is not directly supplied by pm8916_l16, it seems to be a
* fixed regulator that is automatically enabled by pm8916_l16.
*/
vdd-supply = <&pm8916_l16>;
vddio-supply = <&pm8916_l16>;
pinctrl-0 = <&touchscreen_default>;
pinctrl-names = "default";
};
};
&blsp_uart2 {
status = "okay";
};
&pm8916_l8 {
regulator-min-microvolt = <2950000>;
regulator-max-microvolt = <2950000>;
};
&pm8916_resin {
linux,code = <KEY_VOLUMEDOWN>;
status = "okay";
};
&pm8916_rpm_regulators {
pm8916_l16: l16 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
pm8916_l17: l17 {
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <2850000>;
};
};
&pm8916_vib {
status = "okay";
};
&sdhc_1 {
status = "okay";
};
&sdhc_2 {
pinctrl-0 = <&sdc2_default &sdc2_cd_default>;
pinctrl-1 = <&sdc2_sleep &sdc2_cd_default>;
pinctrl-names = "default", "sleep";
cd-gpios = <&tlmm 38 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&usb {
extcon = <&usb_id>, <&usb_id>;
status = "okay";
};
&usb_hs_phy {
extcon = <&usb_id>;
};
&wcnss {
status = "okay";
};
&wcnss_iris {
compatible = "qcom,wcn3620";
};
&wcnss_mem {
status = "okay";
};
&tlmm {
accel_int_default: accel-int-default-state {
pins = "gpio115";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
gpio_hall_sensor_default: gpio-hall-sensor-default-state {
pins = "gpio69";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
gpio_keys_default: gpio-keys-default-state {
pins = "gpio107";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
prox_irq_default: prox-irq-default-state {
pins = "gpio113";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
sdc2_cd_default: sdc2-cd-default-state {
pins = "gpio38";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
touchscreen_default: touchscreen-default-state {
pins = "gpio12", "gpio13";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
usb_id_default: usb-id-default-state {
pins = "gpio110";
function = "gpio";
drive-strength = <8>;
bias-pull-up;
};
};

56
arch/arm64/boot/dts/qcom/msm8939-longcheer-l9100.dts
View File

@ -8,6 +8,7 @@
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
#include <dt-bindings/pinctrl/qcom,pmic-mpp.h>
/ {
@ -120,6 +121,46 @@
};
&blsp_i2c2 {
status = "okay";
led-controller@30 {
compatible = "kinetic,ktd2026";
reg = <0x30>;
#address-cells = <1>;
#size-cells = <0>;
vin-supply = <&pm8916_l17>;
vio-supply = <&pm8916_l6>;
pinctrl-0 = <&status_led_default>;
pinctrl-names = "default";
multi-led {
color = <LED_COLOR_ID_RGB>;
function = LED_FUNCTION_STATUS;
#address-cells = <1>;
#size-cells = <0>;
led@0 {
reg = <0>;
color = <LED_COLOR_ID_RED>;
};
led@1 {
reg = <1>;
color = <LED_COLOR_ID_GREEN>;
};
led@2 {
reg = <2>;
color = <LED_COLOR_ID_BLUE>;
};
};
};
};
&blsp_i2c3 {
status = "okay";
@ -139,6 +180,7 @@
light-sensor@23 {
compatible = "liteon,ltr559";
reg = <0x23>;
proximity-near-level = <75>;
vdd-supply = <&pm8916_l17>;
vddio-supply = <&pm8916_l5>;
@ -184,6 +226,16 @@
status = "okay";
};
&pm8916_gpios {
status_led_default: status-led-default-state {
pins = "gpio3";
function = PMIC_GPIO_FUNC_NORMAL;
power-source = <PM8916_GPIO_VPH>;
bias-disable;
output-high;
};
};
&pm8916_mpps {
pwm_out: mpp4-state {
pins = "mpp4";
@ -247,6 +299,10 @@
compatible = "qcom,wcn3620";
};
&wcnss_mem {
status = "okay";
};
&tlmm {
button_backlight_default: button-backlight-default-state {
pins = "gpio17";

70
arch/arm64/boot/dts/qcom/msm8939-samsung-a7.dts
View File

@ -3,10 +3,12 @@
/dts-v1/;
#include "msm8939-pm8916.dtsi"
#include "msm8916-modem-qdsp6.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/sound/apq8016-lpass.h>
/ {
model = "Samsung Galaxy A7 (2015)";
@ -287,6 +289,18 @@
};
};
&blsp_i2c2 {
status = "okay";
speaker_codec: audio-codec@34 {
compatible = "nxp,tfa9895";
reg = <0x34>;
vddd-supply = <&pm8916_l5>;
sound-name-prefix = "Speaker";
#sound-dai-cells = <0>;
};
};
&blsp_i2c5 {
status = "okay";
@ -309,6 +323,29 @@
status = "okay";
};
/*
* For some reason the speaker amplifier is connected to the second SD line
* (MI2S_2_D1) instead of the first (MI2S_2_D0). This must be configured in the
* device tree, otherwise audio will seemingly play fine on the wrong SD line
* but the speaker stays silent.
*
* When routing audio via QDSP6 (the default) the &lpass node is reserved and
* the definitions from &q6afedai are used. When the modem is disabled audio can
* be alternatively routed directly to the LPASS hardware with reduced latency.
* The definitions for &lpass are here for completeness to simplify changing the
* setup with minor changes to the DT (either manually or with DT overlays).
*/
&lpass {
dai-link@3 {
reg = <MI2S_QUATERNARY>;
qcom,playback-sd-lines = <1>;
};
};
&mpss_mem {
reg = <0x0 0x86800000 0x0 0x5800000>;
};
&pm8916_resin {
linux,code = <KEY_VOLUMEDOWN>;
status = "okay";
@ -321,6 +358,13 @@
};
};
&q6afedai {
dai@22 {
reg = <QUATERNARY_MI2S_RX>;
qcom,sd-lines = <1>;
};
};
&sdhc_1 {
status = "okay";
};
@ -335,6 +379,32 @@
status = "okay";
};
&sound {
model = "samsung-a2015";
audio-routing =
"AMIC1", "MIC BIAS External1",
"AMIC2", "MIC BIAS Internal2",
"AMIC3", "MIC BIAS External1";
pinctrl-0 = <&cdc_pdm_default &sec_mi2s_default>;
pinctrl-1 = <&cdc_pdm_sleep &sec_mi2s_sleep>;
pinctrl-names = "default", "sleep";
sound_link_backend2: backend2-dai-link {
link-name = "Quaternary MI2S";
cpu {
sound-dai = <&q6afedai QUATERNARY_MI2S_RX>;
};
platform {
sound-dai = <&q6routing>;
};
codec {
sound-dai = <&speaker_codec>;
};
};
};
&usb {
extcon = <&muic>, <&muic>;
status = "okay";

82
arch/arm64/boot/dts/qcom/msm8939.dtsi
View File

@ -10,6 +10,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/reset/qcom,gcc-msm8939.h>
#include <dt-bindings/soc/qcom,apr.h>
#include <dt-bindings/thermal/thermal.h>
/ {
@ -1537,6 +1538,20 @@
#interrupt-cells = <4>;
};
bam_dmux_dma: dma-controller@4044000 {
compatible = "qcom,bam-v1.7.0";
reg = <0x04044000 0x19000>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
qcom,ee = <0>;
num-channels = <6>;
qcom,num-ees = <1>;
qcom,powered-remotely;
status = "disabled";
};
mpss: remoteproc@4080000 {
compatible = "qcom,msm8916-mss-pil";
reg = <0x04080000 0x100>, <0x04020000 0x040>;
@ -1569,6 +1584,22 @@
qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>;
status = "disabled";
bam_dmux: bam-dmux {
compatible = "qcom,bam-dmux";
interrupt-parent = <&hexagon_smsm>;
interrupts = <1 IRQ_TYPE_EDGE_BOTH>, <11 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "pc", "pc-ack";
qcom,smem-states = <&apps_smsm 1>, <&apps_smsm 11>;
qcom,smem-state-names = "pc", "pc-ack";
dmas = <&bam_dmux_dma 4>, <&bam_dmux_dma 5>;
dma-names = "tx", "rx";
status = "disabled";
};
mba {
memory-region = <&mba_mem>;
};
@ -1585,6 +1616,54 @@
qcom,remote-pid = <1>;
label = "hexagon";
apr: apr {
compatible = "qcom,apr-v2";
qcom,smd-channels = "apr_audio_svc";
qcom,domain = <APR_DOMAIN_ADSP>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
q6core: service@3 {
compatible = "qcom,q6core";
reg = <APR_SVC_ADSP_CORE>;
};
q6afe: service@4 {
compatible = "qcom,q6afe";
reg = <APR_SVC_AFE>;
q6afedai: dais {
compatible = "qcom,q6afe-dais";
#address-cells = <1>;
#size-cells = <0>;
#sound-dai-cells = <1>;
};
};
q6asm: service@7 {
compatible = "qcom,q6asm";
reg = <APR_SVC_ASM>;
q6asmdai: dais {
compatible = "qcom,q6asm-dais";
#address-cells = <1>;
#size-cells = <0>;
#sound-dai-cells = <1>;
};
};
q6adm: service@8 {
compatible = "qcom,q6adm";
reg = <APR_SVC_ADM>;
q6routing: routing {
compatible = "qcom,q6adm-routing";
#sound-dai-cells = <0>;
};
};
};
};
};
@ -1682,6 +1761,7 @@
clock-names = "bam_clk";
#dma-cells = <1>;
qcom,ee = <0>;
qcom,controlled-remotely;
};
blsp_uart1: serial@78af000 {
@ -2116,6 +2196,8 @@
#address-cells = <1>;
#size-cells = <1>;
ranges;
/* Necessary because firmware does not configure this correctly */
clock-frequency = <19200000>;
frame@b121000 {
reg = <0x0b121000 0x1000>,

1
arch/arm64/boot/dts/qcom/msm8953-xiaomi-mido.dts
View File

@ -111,6 +111,7 @@
reg = <0x45>;
vcc-supply = <&pm8953_l10>;
vio-supply = <&pm8953_l5>;
#address-cells = <1>;
#size-cells = <0>;

1
arch/arm64/boot/dts/qcom/msm8953-xiaomi-tissot.dts
View File

@ -104,6 +104,7 @@
reg = <0x45>;
vcc-supply = <&pm8953_l10>;
vio-supply = <&pm8953_l5>;
#address-cells = <1>;
#size-cells = <0>;

1
arch/arm64/boot/dts/qcom/msm8953-xiaomi-vince.dts
View File

@ -113,6 +113,7 @@
reg = <0x45>;
vcc-supply = <&pm8953_l10>;
vio-supply = <&pm8953_l5>;
#address-cells = <1>;
#size-cells = <0>;

110
arch/arm64/boot/dts/qcom/msm8953.dtsi
View File

@ -174,10 +174,10 @@
};
};
memory {
memory@10000000 {
device_type = "memory";
/* We expect the bootloader to fill in the reg */
reg = <0 0 0 0>;
reg = <0 0x10000000 0 0>;
};
pmu {
@ -726,6 +726,48 @@
bias-disable;
};
spi_3_default: spi-3-default-state {
pins = "gpio10", "gpio11";
function = "blsp_spi3";
drive-strength = <2>;
bias-disable;
};
spi_3_sleep: spi-3-sleep-state {
pins = "gpio10", "gpio11";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
spi_5_default: spi-5-default-state {
pins = "gpio18", "gpio19";
function = "blsp_spi5";
drive-strength = <2>;
bias-disable;
};
spi_5_sleep: spi-5-sleep-state {
pins = "gpio18", "gpio19";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
spi_6_default: spi-6-default-state {
pins = "gpio22", "gpio23";
function = "blsp_spi6";
drive-strength = <2>;
bias-disable;
};
spi_6_sleep: spi-6-sleep-state {
pins = "gpio22", "gpio23";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
wcnss_pin_a: wcnss-active-state {
wcss-wlan2-pins {
@ -1004,7 +1046,7 @@
apps_iommu: iommu@1e20000 {
compatible = "qcom,msm8953-iommu", "qcom,msm-iommu-v1";
ranges = <0 0x01e20000 0x20000>;
ranges = <0 0x01e20000 0x20000>;
clocks = <&gcc GCC_SMMU_CFG_CLK>,
<&gcc GCC_APSS_TCU_ASYNC_CLK>;
@ -1360,6 +1402,26 @@
status = "disabled";
};
spi_3: spi@78b7000 {
compatible = "qcom,spi-qup-v2.2.1";
reg = <0x078b7000 0x600>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "core", "iface";
clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
dmas = <&blsp1_dma 8>, <&blsp1_dma 9>;
dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&spi_3_default>;
pinctrl-1 = <&spi_3_sleep>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c_4: i2c@78b8000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x078b8000 0x600>;
@ -1413,6 +1475,26 @@
status = "disabled";
};
spi_5: spi@7af5000 {
compatible = "qcom,spi-qup-v2.2.1";
reg = <0x07af5000 0x600>;
interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "core", "iface";
clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
<&gcc GCC_BLSP2_AHB_CLK>;
dmas = <&blsp2_dma 4>, <&blsp2_dma 5>;
dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&spi_5_default>;
pinctrl-1 = <&spi_5_sleep>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c_6: i2c@7af6000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x07af6000 0x600>;
@ -1433,6 +1515,26 @@
status = "disabled";
};
spi_6: spi@7af6000 {
compatible = "qcom,spi-qup-v2.2.1";
reg = <0x07af6000 0x600>;
interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "core", "iface";
clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
<&gcc GCC_BLSP2_AHB_CLK>;
dmas = <&blsp2_dma 6>, <&blsp2_dma 7>;
dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&spi_6_default>;
pinctrl-1 = <&spi_6_sleep>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c_7: i2c@7af7000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x07af7000 0x600>;
@ -1645,7 +1747,7 @@
apr {
compatible = "qcom,apr-v2";
qcom,smd-channels = "apr_audio_svc";
qcom,apr-domain = <APR_DOMAIN_ADSP>;
qcom,domain = <APR_DOMAIN_ADSP>;
#address-cells = <1>;
#size-cells = <0>;

125
arch/arm64/boot/dts/qcom/msm8996.dtsi
View File

@ -444,6 +444,38 @@
reg = <0x0 0x80000000 0x0 0x0>;
};
etm {
compatible = "qcom,coresight-remote-etm";
out-ports {
port {
modem_etm_out_funnel_in2: endpoint {
remote-endpoint =
<&funnel_in2_in_modem_etm>;
};
};
};
};
mpm: interrupt-controller {
compatible = "qcom,mpm";
qcom,rpm-msg-ram = <&apss_mpm>;
interrupts = <GIC_SPI 171 IRQ_TYPE_EDGE_RISING>;
mboxes = <&apcs_glb 1>;
interrupt-controller;
#interrupt-cells = <2>;
#power-domain-cells = <0>;
interrupt-parent = <&intc>;
qcom,mpm-pin-count = <96>;
qcom,mpm-pin-map = <2 184>, /* TSENS1 upper_lower_int */
<52 243>, /* DWC3_PRI ss_phy_irq */
<79 347>, /* DWC3_PRI hs_phy_irq */
<80 352>, /* DWC3_SEC hs_phy_irq */
<81 347>, /* QUSB2_PHY_PRI DP+DM */
<82 352>, /* QUSB2_PHY_SEC DP+DM */
<87 326>; /* SPMI */
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
@ -733,8 +765,15 @@
};
rpm_msg_ram: sram@68000 {
compatible = "qcom,rpm-msg-ram";
compatible = "qcom,rpm-msg-ram", "mmio-sram";
reg = <0x00068000 0x6000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x00068000 0x7000>;
apss_mpm: sram@1b8 {
reg = <0x1b8 0x48>;
};
};
qfprom@74000 {
@ -779,10 +818,10 @@
<&pciephy_0>,
<&pciephy_1>,
<&pciephy_2>,
<&ssusb_phy_0>,
<&ufsphy_lane 0>,
<&ufsphy_lane 1>,
<&ufsphy_lane 2>;
<&usb3phy>,
<&ufsphy 0>,
<&ufsphy 1>,
<&ufsphy 2>;
clock-names = "cxo",
"cxo2",
"sleep_clk",
@ -820,8 +859,8 @@
reg = <0x004ad000 0x1000>, /* TM */
<0x004ac000 0x1000>; /* SROT */
#qcom,sensors = <8>;
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
interrupts-extended = <&mpm 2 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "uplow", "critical";
#thermal-sensor-cells = <1>;
};
@ -1343,6 +1382,7 @@
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
gpio-ranges = <&tlmm 0 0 150>;
wakeup-parent = <&mpm>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
@ -1870,7 +1910,7 @@
<0x0400a000 0x002100>;
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
interrupt-names = "periph_irq";
interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
interrupts-extended = <&mpm 87 IRQ_TYPE_LEVEL_HIGH>;
qcom,ee = <0>;
qcom,channel = <0>;
#address-cells = <2>;
@ -2047,7 +2087,7 @@
reg = <0x00624000 0x2500>;
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
phys = <&ufsphy_lane>;
phys = <&ufsphy>;
phy-names = "ufsphy";
power-domains = <&gcc UFS_GDSC>;
@ -2100,25 +2140,18 @@
ufsphy: phy@627000 {
compatible = "qcom,msm8996-qmp-ufs-phy";
reg = <0x00627000 0x1c4>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
reg = <0x00627000 0x1000>;
clocks = <&gcc GCC_UFS_CLKREF_CLK>;
clock-names = "ref";
resets = <&ufshc 0>;
reset-names = "ufsphy";
status = "disabled";
ufsphy_lane: phy@627400 {
reg = <0x627400 0x12c>,
<0x627600 0x200>,
<0x627c00 0x1b4>;
#clock-cells = <1>;
#phy-cells = <0>;
};
#clock-cells = <1>;
#phy-cells = <0>;
status = "disabled";
};
camss: camss@a34000 {
@ -2644,6 +2677,14 @@
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
in-ports {
port {
funnel_in2_in_modem_etm: endpoint {
remote-endpoint =
<&modem_etm_out_funnel_in2>;
};
};
};
out-ports {
port {
@ -3026,8 +3067,8 @@
#size-cells = <1>;
ranges;
interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
interrupts-extended = <&mpm 79 IRQ_TYPE_LEVEL_HIGH>,
<&mpm 52 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hs_phy_irq", "ss_phy_irq";
clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
@ -3056,7 +3097,7 @@
compatible = "snps,dwc3";
reg = <0x06a00000 0xcc00>;
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
phys = <&hsusb_phy1>, <&ssusb_phy_0>;
phys = <&hsusb_phy1>, <&usb3phy>;
phy-names = "usb2-phy", "usb3-phy";
snps,hird-threshold = /bits/ 8 <0>;
snps,dis_u2_susphy_quirk;
@ -3068,32 +3109,26 @@
usb3phy: phy@7410000 {
compatible = "qcom,msm8996-qmp-usb3-phy";
reg = <0x07410000 0x1c4>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
reg = <0x07410000 0x1000>;
clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
<&gcc GCC_USB3_CLKREF_CLK>;
clock-names = "aux", "cfg_ahb", "ref";
<&gcc GCC_USB3_CLKREF_CLK>,
<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
<&gcc GCC_USB3_PHY_PIPE_CLK>;
clock-names = "aux",
"ref",
"cfg_ahb",
"pipe";
clock-output-names = "usb3_phy_pipe_clk_src";
#clock-cells = <0>;
#phy-cells = <0>;
resets = <&gcc GCC_USB3_PHY_BCR>,
<&gcc GCC_USB3PHY_PHY_BCR>;
reset-names = "phy", "common";
<&gcc GCC_USB3PHY_PHY_BCR>;
reset-names = "phy",
"phy_phy";
status = "disabled";
ssusb_phy_0: phy@7410200 {
reg = <0x07410200 0x200>,
<0x07410400 0x130>,
<0x07410600 0x1a8>;
#phy-cells = <0>;
#clock-cells = <0>;
clock-output-names = "usb3_phy_pipe_clk_src";
clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
clock-names = "pipe0";
};
};
hsusb_phy1: phy@7411000 {

87
arch/arm64/boot/dts/qcom/msm8998.dtsi
View File

@ -933,7 +933,7 @@
<GIC_SPI 465 IRQ_TYPE_EDGE_RISING>;
};
pcie0: pci@1c00000 {
pcie0: pcie@1c00000 {
compatible = "qcom,pcie-msm8998", "qcom,pcie-msm8996";
reg = <0x01c00000 0x2000>,
<0x1b000000 0xf1d>,
@ -1004,7 +1004,7 @@
compatible = "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
reg = <0x01da4000 0x2500>;
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
phys = <&ufsphy_lanes>;
phys = <&ufsphy>;
phy-names = "ufsphy";
lanes-per-direction = <2>;
power-domains = <&gcc UFS_GDSC>;
@ -1045,11 +1045,7 @@
ufsphy: phy@1da7000 {
compatible = "qcom,msm8998-qmp-ufs-phy";
reg = <0x01da7000 0x18c>;
#address-cells = <1>;
#size-cells = <1>;
status = "disabled";
ranges;
reg = <0x01da7000 0x1000>;
clock-names =
"ref",
@ -1061,14 +1057,8 @@
reset-names = "ufsphy";
resets = <&ufshc 0>;
ufsphy_lanes: phy@1da7400 {
reg = <0x01da7400 0x128>,
<0x01da7600 0x1fc>,
<0x01da7c00 0x1dc>,
<0x01da7800 0x128>,
<0x01da7a00 0x1fc>;
#phy-cells = <0>;
};
#phy-cells = <0>;
status = "disabled";
};
tcsr_mutex: hwlock@1f40000 {
@ -2031,9 +2021,11 @@
cpu = <&CPU4>;
port {
etm4_out: endpoint {
remote-endpoint = <&apss_funnel_in4>;
out-ports {
port {
etm4_out: endpoint {
remote-endpoint = <&apss_funnel_in4>;
};
};
};
};
@ -2048,9 +2040,11 @@
cpu = <&CPU5>;
port {
etm5_out: endpoint {
remote-endpoint = <&apss_funnel_in5>;
out-ports {
port {
etm5_out: endpoint {
remote-endpoint = <&apss_funnel_in5>;
};
};
};
};
@ -2065,9 +2059,11 @@
cpu = <&CPU6>;
port {
etm6_out: endpoint {
remote-endpoint = <&apss_funnel_in6>;
out-ports {
port {
etm6_out: endpoint {
remote-endpoint = <&apss_funnel_in6>;
};
};
};
};
@ -2082,9 +2078,11 @@
cpu = <&CPU7>;
port {
etm7_out: endpoint {
remote-endpoint = <&apss_funnel_in7>;
out-ports {
port {
etm7_out: endpoint {
remote-endpoint = <&apss_funnel_in7>;
};
};
};
};
@ -2149,7 +2147,7 @@
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
phys = <&qusb2phy>, <&usb1_ssphy>;
phys = <&qusb2phy>, <&usb3phy>;
phy-names = "usb2-phy", "usb3-phy";
snps,has-lpm-erratum;
snps,hird-threshold = /bits/ 8 <0x10>;
@ -2158,33 +2156,26 @@
usb3phy: phy@c010000 {
compatible = "qcom,msm8998-qmp-usb3-phy";
reg = <0x0c010000 0x18c>;
status = "disabled";
#address-cells = <1>;
#size-cells = <1>;
ranges;
reg = <0x0c010000 0x1000>;
clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
<&gcc GCC_USB3_CLKREF_CLK>,
<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
<&gcc GCC_USB3_CLKREF_CLK>;
clock-names = "aux", "cfg_ahb", "ref";
<&gcc GCC_USB3_PHY_PIPE_CLK>;
clock-names = "aux",
"ref",
"cfg_ahb",
"pipe";
clock-output-names = "usb3_phy_pipe_clk_src";
#clock-cells = <0>;
#phy-cells = <0>;
resets = <&gcc GCC_USB3_PHY_BCR>,
<&gcc GCC_USB3PHY_PHY_BCR>;
reset-names = "phy", "common";
reset-names = "phy",
"phy_phy";
usb1_ssphy: phy@c010200 {
reg = <0xc010200 0x128>,
<0xc010400 0x200>,
<0xc010c00 0x20c>,
<0xc010600 0x128>,
<0xc010800 0x200>;
#phy-cells = <0>;
#clock-cells = <0>;
clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
clock-names = "pipe0";
clock-output-names = "usb3_phy_pipe_clk_src";
};
status = "disabled";
};
qusb2phy: phy@c012000 {

2
arch/arm64/boot/dts/qcom/pm7250b.dtsi
View File

@ -148,7 +148,7 @@
status = "disabled";
};
pm7250b_gpios: pinctrl@c000 {
pm7250b_gpios: gpio@c000 {
compatible = "qcom,pm7250b-gpio", "qcom,spmi-gpio";
reg = <0xc000>;
gpio-controller;

3
arch/arm64/boot/dts/qcom/pm8550.dtsi
View File

@ -64,9 +64,6 @@
pm8550_pwm: pwm {
compatible = "qcom,pm8550-pwm", "qcom,pm8350c-pwm";
#address-cells = <1>;
#size-cells = <0>;
#pwm-cells = <2>;
status = "disabled";

6
arch/arm64/boot/dts/qcom/pm8550ve.dtsi
View File

@ -33,16 +33,16 @@
&spmi_bus {
pm8550ve: pmic@5 {
pm8550ve: pmic@PMK8550VE_SID {
compatible = "qcom,pm8550", "qcom,spmi-pmic";
reg = <0x5 SPMI_USID>;
reg = <PMK8550VE_SID SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pm8550ve_temp_alarm: temp-alarm@a00 {
compatible = "qcom,spmi-temp-alarm";
reg = <0xa00>;
interrupts = <0x5 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
interrupts = <PMK8550VE_SID 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
};

48
arch/arm64/boot/dts/qcom/pm8916.dtsi
View File

@ -41,6 +41,35 @@
};
};
pm8916_charger: charger@1000 {
compatible = "qcom,pm8916-lbc";
reg = <0x1000>, <0x1200>, <0x1300>, <0x1600>;
reg-names = "chgr", "bat_if", "usb", "misc";
interrupts = <0x0 0x10 0 IRQ_TYPE_EDGE_BOTH>,
<0x0 0x10 5 IRQ_TYPE_EDGE_BOTH>,
<0x0 0x10 6 IRQ_TYPE_EDGE_BOTH>,
<0x0 0x10 7 IRQ_TYPE_EDGE_BOTH>,
<0x0 0x12 0 IRQ_TYPE_EDGE_BOTH>,
<0x0 0x12 1 IRQ_TYPE_EDGE_BOTH>,
<0x0 0x13 0 IRQ_TYPE_EDGE_BOTH>,
<0x0 0x13 1 IRQ_TYPE_EDGE_BOTH>,
<0x0 0x13 2 IRQ_TYPE_EDGE_BOTH>,
<0x0 0x13 4 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "vbat_det",
"fast_chg",
"chg_fail",
"chg_done",
"bat_pres",
"temp_ok",
"coarse_det",
"usb_vbus",
"chg_gone",
"overtemp";
status = "disabled";
};
pm8916_usbin: usb-detect@1300 {
compatible = "qcom,pm8941-misc";
reg = <0x1300>;
@ -91,6 +120,25 @@
};
};
pm8916_bms: battery@4000 {
compatible = "qcom,pm8916-bms-vm";
reg = <0x4000>;
interrupts = <0x0 0x40 0 IRQ_TYPE_EDGE_RISING>,
<0x0 0x40 1 IRQ_TYPE_EDGE_RISING>,
<0x0 0x40 2 IRQ_TYPE_EDGE_RISING>,
<0x0 0x40 3 IRQ_TYPE_EDGE_RISING>,
<0x0 0x40 4 IRQ_TYPE_EDGE_RISING>,
<0x0 0x40 5 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "cv_leave",
"cv_enter",
"ocv_good",
"ocv_thr",
"fifo",
"state_chg";
status = "disabled";
};
rtc@6000 {
compatible = "qcom,pm8941-rtc";
reg = <0x6000>, <0x6100>;

2
arch/arm64/boot/dts/qcom/pmk8350.dtsi
View File

@ -22,7 +22,7 @@
mode-bootloader = <0x02>;
};
};
&spmi_bus {
pmk8350: pmic@PMK8350_SID {
compatible = "qcom,pmk8350", "qcom,spmi-pmic";

504
arch/arm64/boot/dts/qcom/qcm2290.dtsi
View File

@ -5,12 +5,15 @@
* Based on sm6115.dtsi and previous efforts by Shawn Guo & Loic Poulain.
*/
#include <dt-bindings/clock/qcom,dispcc-qcm2290.h>
#include <dt-bindings/clock/qcom,gcc-qcm2290.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/firmware/qcom,scm.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interconnect/qcom,qcm2290.h>
#include <dt-bindings/interconnect/qcom,rpm-icc.h>
#include <dt-bindings/power/qcom-rpmpd.h>
/ {
@ -150,6 +153,8 @@
clocks = <&rpmcc RPM_SMD_CE1_CLK>;
clock-names = "core";
#reset-cells = <1>;
interconnects = <&system_noc MASTER_CRYPTO_CORE0 RPM_ALWAYS_TAG
&bimc SLAVE_EBI1 RPM_ALWAYS_TAG>;
};
};
@ -194,6 +199,7 @@
CLUSTER_PD: power-domain-cpu-cluster {
#power-domain-cells = <0>;
power-domains = <&mpm>;
domain-idle-states = <&CLUSTER_SLEEP>;
};
};
@ -261,6 +267,24 @@
};
};
};
mpm: interrupt-controller {
compatible = "qcom,mpm";
qcom,rpm-msg-ram = <&apss_mpm>;
interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
mboxes = <&apcs_glb 1>;
interrupt-controller;
#interrupt-cells = <2>;
#power-domain-cells = <0>;
interrupt-parent = <&intc>;
qcom,mpm-pin-count = <96>;
qcom,mpm-pin-map = <2 275>, /* TSENS0 uplow */
<5 296>, /* Soundwire master_irq */
<12 422>, /* DWC3 ss_phy_irq */
<24 79>, /* Soundwire wake_irq */
<86 183>, /* MPM wake, SPMI */
<90 260>; /* QUSB2_PHY DP+DM */
};
};
reserved_memory: reserved-memory {
@ -424,6 +448,7 @@
interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
gpio-ranges = <&tlmm 0 0 127>;
wakeup-parent = <&mpm>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
@ -668,6 +693,33 @@
status = "disabled";
};
system_noc: interconnect@1880000 {
compatible = "qcom,qcm2290-snoc";
reg = <0x0 0x01880000 0x0 0x60200>;
#interconnect-cells = <2>;
qup_virt: interconnect-qup {
compatible = "qcom,qcm2290-qup-virt";
#interconnect-cells = <2>;
};
mmnrt_virt: interconnect-mmnrt {
compatible = "qcom,qcm2290-mmnrt-virt";
#interconnect-cells = <2>;
};
mmrt_virt: interconnect-mmrt {
compatible = "qcom,qcm2290-mmrt-virt";
#interconnect-cells = <2>;
};
};
config_noc: interconnect@1900000 {
compatible = "qcom,qcm2290-cnoc";
reg = <0x0 0x01900000 0x0 0x8200>;
#interconnect-cells = <2>;
};
qfprom@1b44000 {
compatible = "qcom,qcm2290-qfprom", "qcom,qfprom";
reg = <0x0 0x01b44000 0x0 0x3000>;
@ -680,6 +732,60 @@
};
};
pmu@1b8e300 {
compatible = "qcom,qcm2290-cpu-bwmon", "qcom,sdm845-bwmon";
reg = <0x0 0x01b8e300 0x0 0x600>;
interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
operating-points-v2 = <&cpu_bwmon_opp_table>;
interconnects = <&bimc MASTER_APPSS_PROC RPM_ACTIVE_TAG
&bimc SLAVE_EBI1 RPM_ACTIVE_TAG>;
cpu_bwmon_opp_table: opp-table {
compatible = "operating-points-v2";
opp-0 {
opp-peak-kBps = <(200 * 4 * 1000)>;
};
opp-1 {
opp-peak-kBps = <(300 * 4 * 1000)>;
};
opp-2 {
opp-peak-kBps = <(451 * 4 * 1000)>;
};
opp-3 {
opp-peak-kBps = <(547 * 4 * 1000)>;
};
opp-4 {
opp-peak-kBps = <(681 * 4 * 1000)>;
};
opp-5 {
opp-peak-kBps = <(768 * 4 * 1000)>;
};
opp-6 {
opp-peak-kBps = <(1017 * 4 * 1000)>;
};
opp-7 {
opp-peak-kBps = <(1353 * 4 * 1000)>;
};
opp-8 {
opp-peak-kBps = <(1555 * 4 * 1000)>;
};
opp-9 {
opp-peak-kBps = <(1804 * 4 * 1000)>;
};
};
};
spmi_bus: spmi@1c40000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0x0 0x01c40000 0x0 0x1100>,
@ -692,7 +798,7 @@
"obsrvr",
"intr",
"cnfg";
interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
interrupts-extended = <&mpm 86 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "periph_irq";
qcom,ee = <0>;
qcom,channel = <0>;
@ -707,8 +813,8 @@
reg = <0x0 0x04411000 0x0 0x1ff>,
<0x0 0x04410000 0x0 0x8>;
#qcom,sensors = <10>;
interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
interrupts-extended = <&mpm 2 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "uplow", "critical";
#thermal-sensor-cells = <1>;
};
@ -720,9 +826,22 @@
clock-names = "core";
};
bimc: interconnect@4480000 {
compatible = "qcom,qcm2290-bimc";
reg = <0x0 0x04480000 0x0 0x80000>;
#interconnect-cells = <2>;
};
rpm_msg_ram: sram@45f0000 {
compatible = "qcom,rpm-msg-ram";
compatible = "qcom,rpm-msg-ram", "mmio-sram";
reg = <0x0 0x045f0000 0x0 0x7000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x0 0x045f0000 0x7000>;
apss_mpm: sram@1b8 {
reg = <0x1b8 0x48>;
};
};
sram@4690000 {
@ -755,13 +874,45 @@
resets = <&gcc GCC_SDCC1_BCR>;
power-domains = <&rpmpd QCM2290_VDDCX>;
operating-points-v2 = <&sdhc1_opp_table>;
iommus = <&apps_smmu 0xc0 0x0>;
interconnects = <&system_noc MASTER_SDCC_1 RPM_ALWAYS_TAG
&bimc SLAVE_EBI1 RPM_ALWAYS_TAG>,
<&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
&config_noc SLAVE_SDCC_1 RPM_ALWAYS_TAG>;
interconnect-names = "sdhc-ddr",
"cpu-sdhc";
qcom,dll-config = <0x000f642c>;
qcom,ddr-config = <0x80040868>;
bus-width = <8>;
status = "disabled";
sdhc1_opp_table: opp-table {
compatible = "operating-points-v2";
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
required-opps = <&rpmpd_opp_low_svs>;
opp-peak-kBps = <250000 133320>;
opp-avg-kBps = <102400 65000>;
};
opp-192000000 {
opp-hz = /bits/ 64 <192000000>;
required-opps = <&rpmpd_opp_low_svs>;
opp-peak-kBps = <800000 300000>;
opp-avg-kBps = <204800 200000>;
};
opp-384000000 {
opp-hz = /bits/ 64 <384000000>;
required-opps = <&rpmpd_opp_svs_plus>;
opp-peak-kBps = <800000 300000>;
opp-avg-kBps = <204800 200000>;
};
};
};
sdhc_2: mmc@4784000 {
@ -785,6 +936,12 @@
power-domains = <&rpmpd QCM2290_VDDCX>;
operating-points-v2 = <&sdhc2_opp_table>;
iommus = <&apps_smmu 0xa0 0x0>;
interconnects = <&system_noc MASTER_SDCC_2 RPM_ALWAYS_TAG
&bimc SLAVE_EBI1 RPM_ALWAYS_TAG>,
<&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
&config_noc SLAVE_SDCC_2 RPM_ALWAYS_TAG>;
interconnect-names = "sdhc-ddr",
"cpu-sdhc";
qcom,dll-config = <0x0007642c>;
qcom,ddr-config = <0x80040868>;
@ -798,11 +955,15 @@
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
required-opps = <&rpmpd_opp_low_svs>;
opp-peak-kBps = <250000 133320>;
opp-avg-kBps = <261438 150000>;
};
opp-202000000 {
opp-hz = /bits/ 64 <202000000>;
required-opps = <&rpmpd_opp_svs_plus>;
opp-peak-kBps = <800000 300000>;
opp-avg-kBps = <261438 300000>;
};
};
};
@ -850,6 +1011,15 @@
dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
<&gpi_dma0 1 0 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
&qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
<&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
&config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
<&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
&bimc SLAVE_EBI1 RPM_ALWAYS_TAG>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@ -866,6 +1036,12 @@
dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
<&gpi_dma0 1 0 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
&qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
<&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
&config_noc MASTER_APPSS_PROC RPM_ALWAYS_TAG>;
interconnect-names = "qup-core",
"qup-config";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@ -879,6 +1055,12 @@
clock-names = "se";
pinctrl-0 = <&qup_uart0_default>;
pinctrl-names = "default";
interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
&qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
<&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
&config_noc MASTER_APPSS_PROC RPM_ALWAYS_TAG>;
interconnect-names = "qup-core",
"qup-config";
status = "disabled";
};
@ -893,6 +1075,15 @@
dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
<&gpi_dma0 1 1 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
&qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
<&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
&config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
<&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
&bimc SLAVE_EBI1 RPM_ALWAYS_TAG>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@ -909,6 +1100,12 @@
dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
<&gpi_dma0 1 1 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
&qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
<&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
&config_noc MASTER_APPSS_PROC RPM_ALWAYS_TAG>;
interconnect-names = "qup-core",
"qup-config";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@ -925,6 +1122,15 @@
dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
<&gpi_dma0 1 2 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
&qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
<&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
&config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
<&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
&bimc SLAVE_EBI1 RPM_ALWAYS_TAG>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@ -941,6 +1147,12 @@
dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
<&gpi_dma0 1 2 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
&qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
<&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
&config_noc MASTER_APPSS_PROC RPM_ALWAYS_TAG>;
interconnect-names = "qup-core",
"qup-config";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@ -957,6 +1169,15 @@
dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
<&gpi_dma0 1 3 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
&qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
<&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
&config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
<&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
&bimc SLAVE_EBI1 RPM_ALWAYS_TAG>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@ -973,6 +1194,12 @@
dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
<&gpi_dma0 1 3 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
&qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
<&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
&config_noc MASTER_APPSS_PROC RPM_ALWAYS_TAG>;
interconnect-names = "qup-core",
"qup-config";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@ -989,6 +1216,15 @@
dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
<&gpi_dma0 1 4 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
&qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
<&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
&config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
<&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
&bimc SLAVE_EBI1 RPM_ALWAYS_TAG>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@ -1005,6 +1241,12 @@
dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
<&gpi_dma0 1 4 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
&qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
<&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
&config_noc MASTER_APPSS_PROC RPM_ALWAYS_TAG>;
interconnect-names = "qup-core",
"qup-config";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@ -1018,6 +1260,12 @@
clock-names = "se";
pinctrl-0 = <&qup_uart4_default>;
pinctrl-names = "default";
interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
&qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
<&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
&config_noc MASTER_APPSS_PROC RPM_ALWAYS_TAG>;
interconnect-names = "qup-core",
"qup-config";
status = "disabled";
};
@ -1032,6 +1280,15 @@
dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
<&gpi_dma0 1 5 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
&qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
<&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
&config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
<&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
&bimc SLAVE_EBI1 RPM_ALWAYS_TAG>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@ -1048,6 +1305,12 @@
dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
<&gpi_dma0 1 5 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
&qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
<&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
&config_noc MASTER_APPSS_PROC RPM_ALWAYS_TAG>;
interconnect-names = "qup-core",
"qup-config";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@ -1057,9 +1320,10 @@
usb: usb@4ef8800 {
compatible = "qcom,qcm2290-dwc3", "qcom,dwc3";
reg = <0x0 0x04ef8800 0x0 0x400>;
interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hs_phy_irq", "ss_phy_irq";
interrupts-extended = <&intc GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
<&mpm 12 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hs_phy_irq",
"ss_phy_irq";
clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
<&gcc GCC_USB30_PRIM_MASTER_CLK>,
@ -1080,6 +1344,13 @@
resets = <&gcc GCC_USB30_PRIM_BCR>;
power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
/* TODO: USB<->IPA path */
interconnects = <&system_noc MASTER_USB3_0 RPM_ALWAYS_TAG
&bimc SLAVE_EBI1 RPM_ALWAYS_TAG>,
<&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
&config_noc SLAVE_USB3 RPM_ALWAYS_TAG>;
interconnect-names = "usb-ddr",
"apps-usb";
wakeup-source;
#address-cells = <2>;
@ -1105,6 +1376,225 @@
};
};
mdss: display-subsystem@5e00000 {
compatible = "qcom,qcm2290-mdss";
reg = <0x0 0x05e00000 0x0 0x1000>;
reg-names = "mdss";
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <1>;
clocks = <&gcc GCC_DISP_AHB_CLK>,
<&gcc GCC_DISP_HF_AXI_CLK>,
<&dispcc DISP_CC_MDSS_MDP_CLK>;
clock-names = "iface",
"bus",
"core";
resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
power-domains = <&dispcc MDSS_GDSC>;
iommus = <&apps_smmu 0x420 0x2>,
<&apps_smmu 0x421 0x0>;
interconnects = <&mmrt_virt MASTER_MDP0 RPM_ALWAYS_TAG
&bimc SLAVE_EBI1 RPM_ALWAYS_TAG>,
<&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
&config_noc SLAVE_DISPLAY_CFG RPM_ALWAYS_TAG>;
interconnect-names = "mdp0-mem",
"cpu-cfg";
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "disabled";
mdp: display-controller@5e01000 {
compatible = "qcom,qcm2290-dpu";
reg = <0x0 0x05e01000 0x0 0x8f000>,
<0x0 0x05eb0000 0x0 0x2008>;
reg-names = "mdp",
"vbif";
interrupt-parent = <&mdss>;
interrupts = <0>;
clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
<&dispcc DISP_CC_MDSS_AHB_CLK>,
<&dispcc DISP_CC_MDSS_MDP_CLK>,
<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
clock-names = "bus",
"iface",
"core",
"lut",
"vsync";
operating-points-v2 = <&mdp_opp_table>;
power-domains = <&rpmpd QCM2290_VDDCX>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dpu_intf1_out: endpoint {
remote-endpoint = <&mdss_dsi0_in>;
};
};
};
mdp_opp_table: opp-table {
compatible = "operating-points-v2";
opp-19200000 {
opp-hz = /bits/ 64 <19200000>;
required-opps = <&rpmpd_opp_min_svs>;
};
opp-192000000 {
opp-hz = /bits/ 64 <192000000>;
required-opps = <&rpmpd_opp_low_svs>;
};
opp-256000000 {
opp-hz = /bits/ 64 <256000000>;
required-opps = <&rpmpd_opp_svs>;
};
opp-307200000 {
opp-hz = /bits/ 64 <307200000>;
required-opps = <&rpmpd_opp_svs_plus>;
};
opp-384000000 {
opp-hz = /bits/ 64 <384000000>;
required-opps = <&rpmpd_opp_nom>;
};
};
};
mdss_dsi0: dsi@5e94000 {
compatible = "qcom,qcm2290-dsi-ctrl", "qcom,mdss-dsi-ctrl";
reg = <0x0 0x05e94000 0x0 0x400>;
reg-names = "dsi_ctrl";
interrupt-parent = <&mdss>;
interrupts = <4>;
clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
<&dispcc DISP_CC_MDSS_PCLK0_CLK>,
<&dispcc DISP_CC_MDSS_ESC0_CLK>,
<&dispcc DISP_CC_MDSS_AHB_CLK>,
<&gcc GCC_DISP_HF_AXI_CLK>;
clock-names = "byte",
"byte_intf",
"pixel",
"core",
"iface",
"bus";
assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
<&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
assigned-clock-parents = <&mdss_dsi0_phy 0>,
<&mdss_dsi0_phy 1>;
operating-points-v2 = <&dsi_opp_table>;
power-domains = <&rpmpd QCM2290_VDDCX>;
phys = <&mdss_dsi0_phy>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
dsi_opp_table: opp-table {
compatible = "operating-points-v2";
opp-19200000 {
opp-hz = /bits/ 64 <19200000>;
required-opps = <&rpmpd_opp_min_svs>;
};
opp-164000000 {
opp-hz = /bits/ 64 <164000000>;
required-opps = <&rpmpd_opp_low_svs>;
};
opp-187500000 {
opp-hz = /bits/ 64 <187500000>;
required-opps = <&rpmpd_opp_svs>;
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
mdss_dsi0_in: endpoint {
remote-endpoint = <&dpu_intf1_out>;
};
};
port@1 {
reg = <1>;
mdss_dsi0_out: endpoint {
};
};
};
};
mdss_dsi0_phy: phy@5e94400 {
compatible = "qcom,dsi-phy-14nm-2290";
reg = <0x0 0x05e94400 0x0 0x100>,
<0x0 0x05e94500 0x0 0x300>,
<0x0 0x05e94800 0x0 0x188>;
reg-names = "dsi_phy",
"dsi_phy_lane",
"dsi_pll";
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
<&rpmcc RPM_SMD_XO_CLK_SRC>;
clock-names = "iface",
"ref";
power-domains = <&rpmpd QCM2290_VDDMX>;
required-opps = <&rpmpd_opp_nom>;
#clock-cells = <1>;
#phy-cells = <0>;
status = "disabled";
};
};
dispcc: clock-controller@5f00000 {
compatible = "qcom,qcm2290-dispcc";
reg = <0x0 0x05f00000 0x0 0x20000>;
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
<&rpmcc RPM_SMD_XO_A_CLK_SRC>,
<&gcc GCC_DISP_GPLL0_CLK_SRC>,
<&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
<&mdss_dsi0_phy 0>,
<&mdss_dsi0_phy 1>;
clock-names = "bi_tcxo",
"bi_tcxo_ao",
"gcc_disp_gpll0_clk_src",
"gcc_disp_gpll0_div_clk_src",
"dsi0_phy_pll_out_byteclk",
"dsi0_phy_pll_out_dsiclk";
#power-domain-cells = <1>;
#clock-cells = <1>;
#reset-cells = <1>;
};
remoteproc_mpss: remoteproc@6080000 {
compatible = "qcom,qcm2290-mpss-pas", "qcom,sm6115-mpss-pas";
reg = <0x0 0x06080000 0x0 0x100>;

288
arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts
View File

@ -9,6 +9,8 @@
#define PM7250B_SID 8
#define PM7250B_SID1 9
#include <dt-bindings/iio/qcom,spmi-adc7-pm7325.h>
#include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
@ -75,26 +77,11 @@
no-map;
};
adsp_mem: adsp@86700000 {
reg = <0x0 0x86700000 0x0 0x2800000>;
no-map;
};
cdsp_mem: cdsp@88f00000 {
reg = <0x0 0x88f00000 0x0 0x1e00000>;
no-map;
};
mpss_mem: mpss@8b800000 {
reg = <0x0 0x8b800000 0x0 0xf600000>;
no-map;
};
wpss_mem: wpss@9ae00000 {
reg = <0x0 0x9ae00000 0x0 0x1900000>;
no-map;
};
rmtfs_mem: memory@f8500000 {
compatible = "qcom,rmtfs-mem";
reg = <0x0 0xf8500000 0x0 0x600000>;
@ -134,6 +121,106 @@
enable-active-high;
vin-supply = <&vreg_bob>;
};
thermal-zones {
camera-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pmk8350_adc_tm 2>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
chg-skin-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pm7250b_adc_tm 0>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
conn-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pm7250b_adc_tm 1>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
quiet-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pmk8350_adc_tm 1>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
rear-cam-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pmk8350_adc_tm 4>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
sdm-skin-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pmk8350_adc_tm 3>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
xo-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pmk8350_adc_tm 0>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
};
};
&apps_rsc {
@ -182,8 +269,9 @@
};
vreg_l7b: ldo7 {
regulator-min-microvolt = <2400000>;
regulator-max-microvolt = <3544000>;
/* Constrained for UFS VCC, at least until UFS driver scales voltage */
regulator-min-microvolt = <2952000>;
regulator-max-microvolt = <2952000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
@ -425,6 +513,42 @@
status = "okay";
};
&pm7250b_adc {
channel@4d {
reg = <ADC5_AMUX_THM1_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
label = "charger_skin_therm";
};
channel@4f {
reg = <ADC5_AMUX_THM3_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
label = "conn_therm";
};
};
&pm7250b_adc_tm {
status = "okay";
charger-skin-therm@0 {
reg = <0>;
io-channels = <&pm7250b_adc ADC5_AMUX_THM1_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time-us = <200>;
};
conn-therm@1 {
reg = <1>;
io-channels = <&pm7250b_adc ADC5_AMUX_THM3_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time-us = <200>;
};
};
&pm7325_gpios {
volume_down_default: volume-down-default-state {
pins = "gpio6";
@ -448,10 +572,93 @@
};
};
&pmk8350_adc_tm {
status = "okay";
xo-therm@0 {
reg = <0>;
io-channels = <&pmk8350_vadc PMK8350_ADC7_AMUX_THM1_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time-us = <200>;
};
quiet-therm@1 {
reg = <1>;
io-channels = <&pmk8350_vadc PM7325_ADC7_AMUX_THM1_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time-us = <200>;
};
cam-flash-therm@2 {
reg = <2>;
io-channels = <&pmk8350_vadc PM7325_ADC7_AMUX_THM2_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time-us = <200>;
};
sdm-skin-therm@3 {
reg = <3>;
io-channels = <&pmk8350_vadc PM7325_ADC7_AMUX_THM3_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time-us = <200>;
};
wide-rfc-therm@4 {
reg = <4>;
io-channels = <&pmk8350_vadc PM7325_ADC7_AMUX_THM4_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time-us = <200>;
};
};
&pmk8350_rtc {
status = "okay";
};
&pmk8350_vadc {
status = "okay";
channel@44 {
reg = <PMK8350_ADC7_AMUX_THM1_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
label = "pmk8350_xo_therm";
};
channel@144 {
reg = <PM7325_ADC7_AMUX_THM1_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
label = "pm7325_quiet_therm";
};
channel@145 {
reg = <PM7325_ADC7_AMUX_THM2_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
label = "pm7325_cam_flash_therm";
};
channel@146 {
reg = <PM7325_ADC7_AMUX_THM3_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
label = "pm7325_sdm_skin_therm";
};
channel@147 {
reg = <PM7325_ADC7_AMUX_THM4_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
label = "pm7325_wide_rfc_therm";
};
};
&pon_pwrkey {
status = "okay";
};
@ -489,6 +696,26 @@
status = "okay";
};
&remoteproc_adsp {
firmware-name = "qcom/qcm6490/fairphone5/adsp.mbn";
status = "okay";
};
&remoteproc_cdsp {
firmware-name = "qcom/qcm6490/fairphone5/cdsp.mbn";
status = "okay";
};
&remoteproc_mpss {
firmware-name = "qcom/qcm6490/fairphone5/modem.mbn";
status = "okay";
};
&remoteproc_wpss {
firmware-name = "qcom/qcm6490/fairphone5/wpss.mbn";
status = "okay";
};
&sdc2_clk {
drive-strength = <16>;
bias-disable;
@ -632,6 +859,28 @@
};
};
&ufs_mem_hc {
reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>;
vcc-supply = <&vreg_l7b>;
vcc-max-microamp = <800000>;
/*
* Technically l9b enables an eLDO (supplied by s1b) which then powers
* VCCQ2 of the UFS.
*/
vccq-supply = <&vreg_l9b>;
vccq-max-microamp = <900000>;
status = "okay";
};
&ufs_mem_phy {
vdda-phy-supply = <&vreg_l10c>;
vdda-pll-supply = <&vreg_l6b>;
status = "okay";
};
&usb_1 {
status = "okay";
};
@ -665,3 +914,8 @@
status = "okay";
};
&wifi {
qcom,ath11k-calibration-variant = "Fairphone_5";
status = "okay";
};

468
arch/arm64/boot/dts/qcom/qcm6490-idp.dts Normal file
View File

@ -0,0 +1,468 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include "sc7280.dtsi"
#include "pm7325.dtsi"
#include "pm8350c.dtsi"
#include "pmk8350.dtsi"
/delete-node/ &ipa_fw_mem;
/delete-node/ &rmtfs_mem;
/delete-node/ &adsp_mem;
/delete-node/ &cdsp_mem;
/delete-node/ &video_mem;
/delete-node/ &wlan_ce_mem;
/delete-node/ &wpss_mem;
/delete-node/ &xbl_mem;
/ {
model = "Qualcomm Technologies, Inc. QCM6490 IDP";
compatible = "qcom,qcm6490-idp", "qcom,qcm6490";
chassis-type = "embedded";
aliases {
serial0 = &uart5;
};
chosen {
stdout-path = "serial0:115200n8";
};
reserved-memory {
xbl_mem: xbl@80700000 {
reg = <0x0 0x80700000 0x0 0x100000>;
no-map;
};
cdsp_secure_heap_mem: cdsp-secure-heap@81800000 {
reg = <0x0 0x81800000 0x0 0x1e00000>;
no-map;
};
camera_mem: camera@84300000 {
reg = <0x0 0x84300000 0x0 0x500000>;
no-map;
};
wpss_mem: wpss@84800000 {
reg = <0x0 0x84800000 0x0 0x1900000>;
no-map;
};
adsp_mem: adsp@86100000 {
reg = <0x0 0x86100000 0x0 0x2800000>;
no-map;
};
cdsp_mem: cdsp@88900000 {
reg = <0x0 0x88900000 0x0 0x1e00000>;
no-map;
};
video_mem: video@8a700000 {
reg = <0x0 0x8a700000 0x0 0x700000>;
no-map;
};
cvp_mem: cvp@8ae00000 {
reg = <0x0 0x8ae00000 0x0 0x500000>;
no-map;
};
ipa_fw_mem: ipa-fw@8b300000 {
reg = <0x0 0x8b300000 0x0 0x10000>;
no-map;
};
ipa_gsi_mem: ipa-gsi@8b310000 {
reg = <0x0 0x8b310000 0x0 0xa000>;
no-map;
};
gpu_microcode_mem: gpu-microcode@8b31a000 {
reg = <0x0 0x8b31a000 0x0 0x2000>;
no-map;
};
mpss_mem: mpss@8b800000 {
reg = <0x0 0x8b800000 0x0 0xf600000>;
no-map;
};
tz_stat_mem: tz-stat@c0000000 {
reg = <0x0 0xc0000000 0x0 0x100000>;
no-map;
};
tags_mem: tags@c0100000 {
reg = <0x0 0xc0100000 0x0 0x1200000>;
no-map;
};
qtee_mem: qtee@c1300000 {
reg = <0x0 0xc1300000 0x0 0x500000>;
no-map;
};
trusted_apps_mem: trusted_apps@c1800000 {
reg = <0x0 0xc1800000 0x0 0x1c00000>;
no-map;
};
debug_vm_mem: debug-vm@d0600000 {
reg = <0x0 0xd0600000 0x0 0x100000>;
no-map;
};
};
vph_pwr: vph-pwr-regulator {
compatible = "regulator-fixed";
regulator-name = "vph_pwr";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <4350000>;
};
};
&apps_rsc {
regulators-0 {
compatible = "qcom,pm7325-rpmh-regulators";
qcom,pmic-id = "b";
vdd-s1-supply = <&vph_pwr>;
vdd-s2-supply = <&vph_pwr>;
vdd-s3-supply = <&vph_pwr>;
vdd-s4-supply = <&vph_pwr>;
vdd-s5-supply = <&vph_pwr>;
vdd-s6-supply = <&vph_pwr>;
vdd-s7-supply = <&vph_pwr>;
vdd-s8-supply = <&vph_pwr>;
vdd-l1-l4-l12-l15-supply = <&vreg_s7b_0p972>;
vdd-l2-l7-supply = <&vreg_bob_3p296>;
vdd-l3-supply = <&vreg_s2b_0p876>;
vdd-l5-supply = <&vreg_s2b_0p876>;
vdd-l6-l9-l10-supply = <&vreg_s8b_1p272>;
vdd-l8-supply = <&vreg_s7b_0p972>;
vdd-l11-l17-l18-l19-supply = <&vreg_s1b_1p872>;
vdd-l13-supply = <&vreg_s7b_0p972>;
vdd-l14-l16-supply = <&vreg_s8b_1p272>;
vreg_s1b_1p872: smps1 {
regulator-min-microvolt = <1840000>;
regulator-max-microvolt = <2040000>;
};
vreg_s2b_0p876: smps2 {
regulator-min-microvolt = <570070>;
regulator-max-microvolt = <1050000>;
};
vreg_s7b_0p972: smps7 {
regulator-min-microvolt = <535000>;
regulator-max-microvolt = <1120000>;
};
vreg_s8b_1p272: smps8 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1500000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_RET>;
};
vreg_l1b_0p912: ldo1 {
regulator-min-microvolt = <825000>;
regulator-max-microvolt = <925000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l2b_3p072: ldo2 {
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <3544000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l3b_0p504: ldo3 {
regulator-min-microvolt = <312000>;
regulator-max-microvolt = <910000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l4b_0p752: ldo4 {
regulator-min-microvolt = <752000>;
regulator-max-microvolt = <820000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
reg_l5b_0p752: ldo5 {
regulator-min-microvolt = <552000>;
regulator-max-microvolt = <832000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l6b_1p2: ldo6 {
regulator-min-microvolt = <1140000>;
regulator-max-microvolt = <1260000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l7b_2p952: ldo7 {
regulator-min-microvolt = <2400000>;
regulator-max-microvolt = <3544000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l8b_0p904: ldo8 {
regulator-min-microvolt = <870000>;
regulator-max-microvolt = <970000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l9b_1p2: ldo9 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1304000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l11b_1p504: ldo11 {
regulator-min-microvolt = <1504000>;
regulator-max-microvolt = <2000000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l12b_0p751: ldo12 {
regulator-min-microvolt = <751000>;
regulator-max-microvolt = <824000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l13b_0p53: ldo13 {
regulator-min-microvolt = <530000>;
regulator-max-microvolt = <824000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l14b_1p08: ldo14 {
regulator-min-microvolt = <1080000>;
regulator-max-microvolt = <1304000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l15b_0p765: ldo15 {
regulator-min-microvolt = <765000>;
regulator-max-microvolt = <1020000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l16b_1p1: ldo16 {
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1300000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l17b_1p7: ldo17 {
regulator-min-microvolt = <1700000>;
regulator-max-microvolt = <1900000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l18b_1p8: ldo18 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2000000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l19b_1p8: ldo19 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2000000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
};
regulators-1 {
compatible = "qcom,pm8350c-rpmh-regulators";
qcom,pmic-id = "c";
vdd-s1-supply = <&vph_pwr>;
vdd-s2-supply = <&vph_pwr>;
vdd-s3-supply = <&vph_pwr>;
vdd-s4-supply = <&vph_pwr>;
vdd-s5-supply = <&vph_pwr>;
vdd-s6-supply = <&vph_pwr>;
vdd-s7-supply = <&vph_pwr>;
vdd-s8-supply = <&vph_pwr>;
vdd-s9-supply = <&vph_pwr>;
vdd-s10-supply = <&vph_pwr>;
vdd-l1-l12-supply = <&vreg_s1b_1p872>;
vdd-l2-l8-supply = <&vreg_s1b_1p872>;
vdd-l3-l4-l5-l7-l13-supply = <&vreg_bob_3p296>;
vdd-l6-l9-l11-supply = <&vreg_bob_3p296>;
vdd-l10-supply = <&vreg_s7b_0p972>;
vdd-bob-supply = <&vph_pwr>;
vreg_s1c_2p19: smps1 {
regulator-min-microvolt = <2190000>;
regulator-max-microvolt = <2210000>;
};
vreg_s2c_0p752: smps2 {
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <800000>;
};
vreg_s5c_0p752: smps5 {
regulator-min-microvolt = <465000>;
regulator-max-microvolt = <1050000>;
};
vreg_s7c_0p752: smps7 {
regulator-min-microvolt = <465000>;
regulator-max-microvolt = <800000>;
};
vreg_s9c_1p084: smps9 {
regulator-min-microvolt = <1010000>;
regulator-max-microvolt = <1170000>;
};
vreg_l1c_1p8: ldo1 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1980000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l2c_1p62: ldo2 {
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <1980000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l3c_2p8: ldo3 {
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <3540000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l4c_1p62: ldo4 {
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <3300000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l5c_1p62: ldo5 {
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <3300000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l6c_2p96: ldo6 {
regulator-min-microvolt = <1650000>;
regulator-max-microvolt = <3544000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l7c_3p0: ldo7 {
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3544000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l8c_1p62: ldo8 {
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <2000000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l9c_2p96: ldo9 {
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <35440000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l10c_0p88: ldo10 {
regulator-min-microvolt = <720000>;
regulator-max-microvolt = <1050000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l11c_2p8: ldo11 {
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <3544000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l12c_1p65: ldo12 {
regulator-min-microvolt = <1650000>;
regulator-max-microvolt = <2000000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l13c_2p7: ldo13 {
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <3544000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_bob_3p296: bob {
regulator-min-microvolt = <3008000>;
regulator-max-microvolt = <3960000>;
};
};
};
&qupv3_id_0 {
status = "okay";
};
&sdhc_1 {
non-removable;
no-sd;
no-sdio;
vmmc-supply = <&vreg_l7b_2p952>;
vqmmc-supply = <&vreg_l19b_1p8>;
status = "okay";
};
&tlmm {
gpio-reserved-ranges = <32 2>, /* ADSP */
<48 4>; /* NFC */
};
&uart5 {
compatible = "qcom,geni-debug-uart";
status = "okay";
};
&usb_1 {
status = "okay";
};
&usb_1_dwc3 {
dr_mode = "peripheral";
};
&usb_1_hsphy {
vdda-pll-supply = <&vreg_l10c_0p88>;
vdda33-supply = <&vreg_l2b_3p072>;
vdda18-supply = <&vreg_l1c_1p8>;
status = "okay";
};
&usb_1_qmpphy {
vdda-phy-supply = <&vreg_l6b_1p2>;
vdda-pll-supply = <&vreg_l1b_0p912>;
status = "okay";
};
&wifi {
memory-region = <&wlan_fw_mem>;
};

2
arch/arm64/boot/dts/qcom/qcs404.dtsi
View File

@ -1461,7 +1461,7 @@
};
};
pcie: pci@10000000 {
pcie: pcie@10000000 {
compatible = "qcom,pcie-qcs404";
reg = <0x10000000 0xf1d>,
<0x10000f20 0xa8>,

455
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts Normal file
View File

@ -0,0 +1,455 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/* PM7250B is configured to use SID8/9 */
#define PM7250B_SID 8
#define PM7250B_SID1 9
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include "sc7280.dtsi"
#include "pm7250b.dtsi"
#include "pm7325.dtsi"
#include "pm8350c.dtsi"
#include "pmk8350.dtsi"
/delete-node/ &ipa_fw_mem;
/delete-node/ &remoteproc_mpss;
/delete-node/ &rmtfs_mem;
/delete-node/ &adsp_mem;
/delete-node/ &cdsp_mem;
/delete-node/ &video_mem;
/delete-node/ &wlan_ce_mem;
/delete-node/ &wpss_mem;
/delete-node/ &xbl_mem;
/ {
model = "Qualcomm Technologies, Inc. Robotics RB3gen2";
compatible = "qcom,qcs6490-rb3gen2", "qcom,qcm6490";
chassis-type = "embedded";
aliases {
serial0 = &uart5;
};
chosen {
stdout-path = "serial0:115200n8";
};
reserved-memory {
xbl_mem: xbl@80700000 {
reg = <0x0 0x80700000 0x0 0x100000>;
no-map;
};
cdsp_secure_heap_mem: cdsp-secure-heap@81800000 {
reg = <0x0 0x81800000 0x0 0x1e00000>;
no-map;
};
camera_mem: camera@84300000 {
reg = <0x0 0x84300000 0x0 0x500000>;
no-map;
};
wpss_mem: wpss@84800000 {
reg = <0x0 0x84800000 0x0 0x1900000>;
no-map;
};
adsp_mem: adsp@86100000 {
reg = <0x0 0x86100000 0x0 0x2800000>;
no-map;
};
cdsp_mem: cdsp@88900000 {
reg = <0x0 0x88900000 0x0 0x1e00000>;
no-map;
};
video_mem: video@8a700000 {
reg = <0x0 0x8a700000 0x0 0x700000>;
no-map;
};
cvp_mem: cvp@8ae00000 {
reg = <0x0 0x8ae00000 0x0 0x500000>;
no-map;
};
ipa_fw_mem: ipa-fw@8b300000 {
reg = <0x0 0x8b300000 0x0 0x10000>;
no-map;
};
ipa_gsi_mem: ipa-gsi@8b310000 {
reg = <0x0 0x8b310000 0x0 0xa000>;
no-map;
};
gpu_microcode_mem: gpu-microcode@8b31a000 {
reg = <0x0 0x8b31a000 0x0 0x2000>;
no-map;
};
tz_stat_mem: tz-stat@c0000000 {
reg = <0x0 0xc0000000 0x0 0x100000>;
no-map;
};
tags_mem: tags@c0100000 {
reg = <0x0 0xc0100000 0x0 0x1200000>;
no-map;
};
qtee_mem: qtee@c1300000 {
reg = <0x0 0xc1300000 0x0 0x500000>;
no-map;
};
trusted_apps_mem: trusted_apps@c1800000 {
reg = <0x0 0xc1800000 0x0 0x1c00000>;
no-map;
};
debug_vm_mem: debug-vm@d0600000 {
reg = <0x0 0xd0600000 0x0 0x100000>;
no-map;
};
};
vph_pwr: vph-pwr-regulator {
compatible = "regulator-fixed";
regulator-name = "vph_pwr";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <4350000>;
};
};
&apps_rsc {
regulators-0 {
compatible = "qcom,pm7325-rpmh-regulators";
qcom,pmic-id = "b";
vdd-s1-supply = <&vph_pwr>;
vdd-s2-supply = <&vph_pwr>;
vdd-s3-supply = <&vph_pwr>;
vdd-s4-supply = <&vph_pwr>;
vdd-s5-supply = <&vph_pwr>;
vdd-s6-supply = <&vph_pwr>;
vdd-s7-supply = <&vph_pwr>;
vdd-s8-supply = <&vph_pwr>;
vdd-l1-l4-l12-l15-supply = <&vreg_s7b_0p972>;
vdd-l2-l7-supply = <&vreg_bob_3p296>;
vdd-l3-supply = <&vreg_s2b_0p876>;
vdd-l5-supply = <&vreg_s2b_0p876>;
vdd-l6-l9-l10-supply = <&vreg_s8b_1p272>;
vdd-l8-supply = <&vreg_s7b_0p972>;
vdd-l11-l17-l18-l19-supply = <&vreg_s1b_1p872>;
vdd-l13-supply = <&vreg_s7b_0p972>;
vdd-l14-l16-supply = <&vreg_s8b_1p272>;
vreg_s1b_1p872: smps1 {
regulator-min-microvolt = <1840000>;
regulator-max-microvolt = <2040000>;
};
vreg_s2b_0p876: smps2 {
regulator-min-microvolt = <570070>;
regulator-max-microvolt = <1050000>;
};
vreg_s7b_0p972: smps7 {
regulator-min-microvolt = <535000>;
regulator-max-microvolt = <1120000>;
};
vreg_s8b_1p272: smps8 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1500000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_RET>;
};
vreg_l1b_0p912: ldo1 {
regulator-min-microvolt = <825000>;
regulator-max-microvolt = <925000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l2b_3p072: ldo2 {
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <3544000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l3b_0p504: ldo3 {
regulator-min-microvolt = <312000>;
regulator-max-microvolt = <910000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l4b_0p752: ldo4 {
regulator-min-microvolt = <752000>;
regulator-max-microvolt = <820000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
reg_l5b_0p752: ldo5 {
regulator-min-microvolt = <552000>;
regulator-max-microvolt = <832000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l6b_1p2: ldo6 {
regulator-min-microvolt = <1140000>;
regulator-max-microvolt = <1260000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l7b_2p952: ldo7 {
regulator-min-microvolt = <2400000>;
regulator-max-microvolt = <3544000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l8b_0p904: ldo8 {
regulator-min-microvolt = <870000>;
regulator-max-microvolt = <970000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l9b_1p2: ldo9 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1304000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l11b_1p504: ldo11 {
regulator-min-microvolt = <1504000>;
regulator-max-microvolt = <2000000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l12b_0p751: ldo12 {
regulator-min-microvolt = <751000>;
regulator-max-microvolt = <824000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l13b_0p53: ldo13 {
regulator-min-microvolt = <530000>;
regulator-max-microvolt = <824000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l14b_1p08: ldo14 {
regulator-min-microvolt = <1080000>;
regulator-max-microvolt = <1304000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l15b_0p765: ldo15 {
regulator-min-microvolt = <765000>;
regulator-max-microvolt = <1020000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l16b_1p1: ldo16 {
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1300000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l17b_1p7: ldo17 {
regulator-min-microvolt = <1700000>;
regulator-max-microvolt = <1900000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l18b_1p8: ldo18 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2000000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l19b_1p8: ldo19 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2000000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
regulators-1 {
compatible = "qcom,pm8350c-rpmh-regulators";
qcom,pmic-id = "c";
vdd-s1-supply = <&vph_pwr>;
vdd-s2-supply = <&vph_pwr>;
vdd-s3-supply = <&vph_pwr>;
vdd-s4-supply = <&vph_pwr>;
vdd-s5-supply = <&vph_pwr>;
vdd-s6-supply = <&vph_pwr>;
vdd-s7-supply = <&vph_pwr>;
vdd-s8-supply = <&vph_pwr>;
vdd-s9-supply = <&vph_pwr>;
vdd-s10-supply = <&vph_pwr>;
vdd-l1-l12-supply = <&vreg_s1b_1p872>;
vdd-l2-l8-supply = <&vreg_s1b_1p872>;
vdd-l3-l4-l5-l7-l13-supply = <&vreg_bob_3p296>;
vdd-l6-l9-l11-supply = <&vreg_bob_3p296>;
vdd-l10-supply = <&vreg_s7b_0p972>;
vdd-bob-supply = <&vph_pwr>;
vreg_s1c_2p19: smps1 {
regulator-min-microvolt = <2190000>;
regulator-max-microvolt = <2210000>;
};
vreg_s2c_0p752: smps2 {
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <800000>;
};
vreg_s5c_0p752: smps5 {
regulator-min-microvolt = <465000>;
regulator-max-microvolt = <1050000>;
};
vreg_s7c_0p752: smps7 {
regulator-min-microvolt = <465000>;
regulator-max-microvolt = <800000>;
};
vreg_s9c_1p084: smps9 {
regulator-min-microvolt = <1010000>;
regulator-max-microvolt = <1170000>;
};
vreg_l1c_1p8: ldo1 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1980000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l2c_1p62: ldo2 {
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <1980000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l3c_2p8: ldo3 {
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <3540000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l4c_1p62: ldo4 {
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <3300000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l5c_1p62: ldo5 {
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <3300000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l6c_2p96: ldo6 {
regulator-min-microvolt = <1650000>;
regulator-max-microvolt = <3544000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l7c_3p0: ldo7 {
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3544000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l8c_1p62: ldo8 {
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <2000000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l9c_2p96: ldo9 {
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <35440000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l10c_0p88: ldo10 {
regulator-min-microvolt = <720000>;
regulator-max-microvolt = <1050000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l11c_2p8: ldo11 {
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <3544000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l12c_1p65: ldo12 {
regulator-min-microvolt = <1650000>;
regulator-max-microvolt = <2000000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l13c_2p7: ldo13 {
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <3544000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_bob_3p296: bob {
regulator-min-microvolt = <3008000>;
regulator-max-microvolt = <3960000>;
};
};
};
&qupv3_id_0 {
status = "okay";
};
&tlmm {
gpio-reserved-ranges = <32 2>, /* ADSP */
<48 4>; /* NFC */
};
&uart5 {
compatible = "qcom,geni-debug-uart";
status = "okay";
};
&usb_1 {
status = "okay";
};
&usb_1_dwc3 {
dr_mode = "peripheral";
};
&usb_1_hsphy {
vdda-pll-supply = <&vreg_l10c_0p88>;
vdda33-supply = <&vreg_l2b_3p072>;
vdda18-supply = <&vreg_l1c_1p8>;
status = "okay";
};
&usb_1_qmpphy {
vdda-phy-supply = <&vreg_l6b_1p2>;
vdda-pll-supply = <&vreg_l1b_0p912>;
status = "okay";
};
&wifi {
memory-region = <&wlan_fw_mem>;
};

23
arch/arm64/boot/dts/qcom/qdu1000.dtsi
View File

@ -381,6 +381,20 @@
#power-domain-cells = <1>;
};
ecpricc: clock-controller@280000 {
compatible = "qcom,qdu1000-ecpricc";
reg = <0x0 0x00280000 0x0 0x31c00>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_ECPRI_CC_GPLL0_CLK_SRC>,
<&gcc GCC_ECPRI_CC_GPLL1_EVEN_CLK_SRC>,
<&gcc GCC_ECPRI_CC_GPLL2_EVEN_CLK_SRC>,
<&gcc GCC_ECPRI_CC_GPLL3_CLK_SRC>,
<&gcc GCC_ECPRI_CC_GPLL4_CLK_SRC>,
<&gcc GCC_ECPRI_CC_GPLL5_EVEN_CLK_SRC>;
#clock-cells = <1>;
#reset-cells = <1>;
};
gpi_dma0: dma-controller@900000 {
compatible = "qcom,qdu1000-gpi-dma", "qcom,sm6350-gpi-dma";
reg = <0x0 0x900000 0x0 0x60000>;
@ -1446,13 +1460,10 @@
system-cache-controller@19200000 {
compatible = "qcom,qdu1000-llcc";
reg = <0 0x19200000 0 0xd80000>,
<0 0x1a200000 0 0x80000>,
<0 0x221c8128 0 0x4>;
reg-names = "llcc_base",
"llcc_broadcast_base",
"multi_channel_register";
<0 0x1a200000 0 0x80000>;
reg-names = "llcc0_base",
"llcc_broadcast_base";
interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
multi-ch-bit-off = <24 2>;
};
};

113
arch/arm64/boot/dts/qcom/qrb2210-rb1.dts
View File

@ -23,6 +23,14 @@
stdout-path = "serial0:115200n8";
};
clocks {
clk40M: can-clk {
compatible = "fixed-clock";
clock-frequency = <40000000>;
#clock-cells = <0>;
};
};
gpio-keys {
compatible = "gpio-keys";
label = "gpio-keys";
@ -40,6 +48,17 @@
};
};
hdmi-connector {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con: endpoint {
remote-endpoint = <&lt9611_out>;
};
};
};
leds {
compatible = "gpio-leds";
@ -158,6 +177,68 @@
};
};
&gpi_dma0 {
status = "okay";
};
&i2c2 {
clock-frequency = <400000>;
status = "okay";
lt9611_codec: hdmi-bridge@2b {
compatible = "lontium,lt9611uxc";
reg = <0x2b>;
interrupts-extended = <&tlmm 46 IRQ_TYPE_EDGE_FALLING>;
reset-gpios = <&tlmm 41 GPIO_ACTIVE_HIGH>;
vdd-supply = <&vreg_hdmi_out_1p2>;
vcc-supply = <&lt9611_3v3>;
pinctrl-0 = <&lt9611_irq_pin &lt9611_rst_pin>;
pinctrl-names = "default";
#sound-dai-cells = <1>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
lt9611_a: endpoint {
remote-endpoint = <&mdss_dsi0_out>;
};
};
port@2 {
reg = <2>;
lt9611_out: endpoint {
remote-endpoint = <&hdmi_con>;
};
};
};
};
};
&mdss {
status = "okay";
};
&mdss_dsi0 {
vdda-supply = <&pm2250_l5>;
status = "okay";
};
&mdss_dsi0_out {
remote-endpoint = <&lt9611_a>;
data-lanes = <0 1 2 3>;
};
&mdss_dsi0_phy {
status = "okay";
};
&pm2250_resin {
linux,code = <KEY_VOLUMEDOWN>;
status = "okay";
@ -376,7 +457,34 @@
status = "okay";
};
&spi5 {
status = "okay";
can@0 {
compatible = "microchip,mcp2518fd";
reg = <0>;
interrupts-extended = <&tlmm 39 IRQ_TYPE_LEVEL_LOW>;
clocks = <&clk40M>;
spi-max-frequency = <10000000>;
vdd-supply = <&vdc_5v>;
xceiver-supply = <&vdc_5v>;
};
};
&tlmm {
lt9611_rst_pin: lt9611-rst-state {
pins = "gpio41";
function = "gpio";
input-disable;
output-high;
};
lt9611_irq_pin: lt9611-irq-state {
pins = "gpio46";
function = "gpio";
bias-disable;
};
sd_det_in_on: sd-det-in-on-state {
pins = "gpio88";
function = "gpio";
@ -415,6 +523,10 @@
status = "okay";
};
&usb_dwc3 {
dr_mode = "host";
};
&usb_hsphy {
vdd-supply = <&pm2250_l12>;
vdda-pll-supply = <&pm2250_l13>;
@ -427,6 +539,7 @@
vdd-1.8-xo-supply = <&pm2250_l13>;
vdd-1.3-rfa-supply = <&pm2250_l10>;
vdd-3.3-ch0-supply = <&pm2250_l22>;
qcom,ath10k-calibration-variant = "Thundercomm_RB1";
status = "okay";
};

112
arch/arm64/boot/dts/qcom/qrb4210-rb2.dts
View File

@ -15,6 +15,7 @@
aliases {
serial0 = &uart4;
serial1 = &uart3;
};
chosen {
@ -280,6 +281,12 @@
status = "okay";
};
&remoteproc_mpss {
firmware-name = "qcom/qrb4210/modem.mbn";
status = "okay";
};
&rpm_requests {
regulators {
compatible = "qcom,rpm-pm6125-regulators";
@ -346,13 +353,14 @@
};
vreg_l8a_0p664: l8 {
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <728000>;
regulator-min-microvolt = <640000>;
regulator-max-microvolt = <640000>;
};
vreg_l9a_1p8: l9 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2000000>;
regulator-max-microvolt = <1800000>;
regulator-allow-set-load;
};
vreg_l10a_1p8: l10 {
@ -389,11 +397,13 @@
vreg_l16a_1p3: l16 {
regulator-min-microvolt = <1704000>;
regulator-max-microvolt = <1904000>;
regulator-allow-set-load;
};
vreg_l17a_1p3: l17 {
regulator-min-microvolt = <1152000>;
regulator-max-microvolt = <1384000>;
regulator-allow-set-load;
};
vreg_l18a_1p232: l18 {
@ -424,8 +434,9 @@
};
vreg_l23a_3p3: l23 {
regulator-min-microvolt = <3200000>;
regulator-max-microvolt = <3400000>;
regulator-min-microvolt = <3312000>;
regulator-max-microvolt = <3312000>;
regulator-allow-set-load;
};
vreg_l24a_2p96: l24 {
@ -487,6 +498,66 @@
<56 3>, <61 2>, <64 1>,
<68 1>, <72 8>, <96 1>;
uart3_default: uart3-default-state {
cts-pins {
pins = "gpio8";
function = "qup3";
drive-strength = <2>;
bias-bus-hold;
};
rts-pins {
pins = "gpio9";
function = "qup3";
drive-strength = <2>;
bias-disable;
};
tx-pins {
pins = "gpio10";
function = "qup3";
drive-strength = <2>;
bias-disable;
};
rx-pins {
pins = "gpio11";
function = "qup3";
drive-strength = <2>;
bias-pull-up;
};
};
uart3_sleep: uart3-sleep-state {
cts-pins {
pins = "gpio8";
function = "gpio";
drive-strength = <2>;
bias-bus-hold;
};
rts-pins {
pins = "gpio9";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
tx-pins {
pins = "gpio10";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
rx-pins {
pins = "gpio11";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
lt9611_rst_pin: lt9611-rst-state {
pins = "gpio41";
function = "gpio";
@ -508,6 +579,26 @@
};
};
&uart3 {
interrupts-extended = <&intc GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
<&tlmm 11 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-0 = <&uart3_default>;
pinctrl-1 = <&uart3_sleep>;
pinctrl-names = "default", "sleep";
status = "okay";
bluetooth {
compatible = "qcom,wcn3988-bt";
vddio-supply = <&vreg_l9a_1p8>;
vddxo-supply = <&vreg_l16a_1p3>;
vddrf-supply = <&vreg_l17a_1p3>;
vddch0-supply = <&vreg_l23a_3p3>;
enable-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>;
max-speed = <3200000>;
};
};
&uart4 {
status = "okay";
};
@ -518,7 +609,6 @@
&usb_dwc3 {
maximum-speed = "super-speed";
dr_mode = "peripheral";
};
&usb_hsphy {
@ -536,6 +626,16 @@
status = "okay";
};
&wifi {
vdd-0.8-cx-mx-supply = <&vreg_l8a_0p664>;
vdd-1.8-xo-supply = <&vreg_l16a_1p3>;
vdd-1.3-rfa-supply = <&vreg_l17a_1p3>;
vdd-3.3-ch0-supply = <&vreg_l23a_3p3>;
qcom,ath10k-calibration-variant = "Thundercomm_RB2";
status = "okay";
};
&xo_board {
clock-frequency = <19200000>;
};

2
arch/arm64/boot/dts/qcom/qrb5165-rb5-vision-mezzanine.dts
View File

@ -46,7 +46,7 @@
assigned-clocks = <&camcc CAM_CC_MCLK2_CLK>;
assigned-clock-rates = <24000000>;
dovdd-supply = <&vreg_l7f_1p8>;
dovdd-supply = <&vreg_l7f_1p8>;
avdd-supply = <&vdc_5v>;
dvdd-supply = <&vdc_5v>;

31
arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
View File

@ -23,6 +23,7 @@
aliases {
serial0 = &uart12;
serial1 = &uart6;
sdhc2 = &sdhc_2;
};
@ -64,8 +65,8 @@
function = LED_FUNCTION_INDICATOR;
color = <LED_COLOR_ID_GREEN>;
gpios = <&pm8150_gpios 10 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "panic-indicator";
default-state = "off";
panic-indicator;
};
led-wlan {
@ -1263,6 +1264,14 @@
"HST_WLAN_UART_TX",
"HST_WLAN_UART_RX";
bt_en_state: bt-default-state {
pins = "gpio21";
function = "gpio";
drive-strength = <16>;
output-low;
bias-pull-up;
};
lt9611_irq_pin: lt9611-irq-state {
pins = "gpio63";
function = "gpio";
@ -1296,6 +1305,26 @@
};
};
&uart6 {
status = "okay";
bluetooth {
compatible = "qcom,qca6390-bt";
pinctrl-names = "default";
pinctrl-0 = <&bt_en_state>;
enable-gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>;
vddio-supply = <&vreg_s4a_1p8>;
vddpmu-supply = <&vreg_s2f_0p95>;
vddaon-supply = <&vreg_s6a_0p95>;
vddrfa0p9-supply = <&vreg_s2f_0p95>;
vddrfa1p3-supply = <&vreg_s8c_1p3>;
vddrfa1p9-supply = <&vreg_s5a_1p9>;
};
};
&uart12 {
status = "okay";
};

5
arch/arm64/boot/dts/qcom/sa8775p-ride.dts
View File

@ -461,6 +461,11 @@
"ANALOG_PON_OPT";
};
&pmm8654au_0_pon_resin {
linux,code = <KEY_VOLUMEDOWN>;
status = "okay";
};
&pmm8654au_1_gpios {
gpio-line-names = "PMIC_C_ID0",
"PMIC_C_ID1",

1124
arch/arm64/boot/dts/qcom/sa8775p.dtsi
View File

File diff suppressed because it is too large Load Diff

174
arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts
View File

@ -3,6 +3,7 @@
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/sound/qcom,q6asm.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include "sc7180.dtsi"
@ -129,6 +130,113 @@
pinctrl-names = "default";
};
sound: sound {
compatible = "qcom,sc7180-qdsp6-sndcard";
pinctrl-0 = <&pri_mi2s_active>, <&pri_mi2s_mclk_active>, <&ter_mi2s_active>;
pinctrl-names = "default";
model = "Acer-Aspire-1";
audio-routing =
"Headphone Jack", "HPOL",
"Headphone Jack", "HPOR";
multimedia1-dai-link {
link-name = "MultiMedia1";
cpu {
sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>;
};
};
multimedia2-dai-link {
link-name = "MultiMedia2";
cpu {
sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA2>;
};
};
multimedia3-dai-link {
link-name = "MultiMedia3";
cpu {
sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA3>;
};
};
multimedia4-dai-link {
link-name = "MultiMedia4";
cpu {
sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA4>;
};
};
primary-rx-dai-link {
link-name = "Primary MI2S Playback";
cpu {
sound-dai = <&q6afedai PRIMARY_MI2S_RX>;
};
platform {
sound-dai = <&q6routing>;
};
codec {
sound-dai = <&alc5682 0>;
};
};
primary-tx-dai-link {
link-name = "Primary MI2S Capture";
cpu {
sound-dai = <&q6afedai PRIMARY_MI2S_TX>;
};
platform {
sound-dai = <&q6routing>;
};
codec {
sound-dai = <&alc5682 0>;
};
};
tertiary-rx-dai-link {
link-name = "Tertiary MI2S Playback";
cpu {
sound-dai = <&q6afedai TERTIARY_MI2S_RX>;
};
platform {
sound-dai = <&q6routing>;
};
codec {
sound-dai = <&max98357a>;
};
};
displayport-rx-dai-link {
link-name = "DisplayPort Playback";
cpu {
sound-dai = <&q6afedai DISPLAY_PORT_RX>;
};
platform {
sound-dai = <&q6routing>;
};
codec {
sound-dai = <&mdss_dp>;
};
};
};
reg_tp_3p3: touchpad-regulator {
compatible = "regulator-fixed";
regulator-name = "tp_3p3";
@ -209,9 +317,22 @@
AVDD-supply = <&vreg_l15a_1p8>;
MICVDD-supply = <&reg_codec_3p3>;
VBAT-supply = <&reg_codec_3p3>;
DBVDD-supply = <&vreg_l15a_1p8>;
LDO1-IN-supply = <&vreg_l15a_1p8>;
/*
* NOTE: The board has a path from this codec to the
* DMIC microphones in the lid, however some of the option
* resistors are absent and the microphones are connected
* to the SoC instead.
*
* If the resistors were to be changed by the user to
* connect the codec, the following could be used:
*
* realtek,dmic1-data-pin = <1>;
* realtek,dmic1-clk-pin = <1>;
*/
realtek,dmic1-data-pin = <1>;
realtek,dmic1-clk-pin = <1>;
realtek,jd-src = <1>;
};
};
@ -351,6 +472,49 @@
status = "disabled";
};
&pm6150_rtc {
status = "okay";
};
&q6afedai {
dai@16 {
reg = <PRIMARY_MI2S_RX>;
qcom,sd-lines = <1>;
};
dai@17 {
reg = <PRIMARY_MI2S_TX>;
qcom,sd-lines = <0>;
};
dai@20 {
reg = <TERTIARY_MI2S_RX>;
qcom,sd-lines = <0>;
};
dai@104 {
reg = <DISPLAY_PORT_RX>;
};
};
&q6asmdai {
dai@0 {
reg = <0>;
};
dai@1 {
reg = <1>;
};
dai@2 {
reg = <2>;
};
dai@3 {
reg = <3>;
};
};
&qupv3_id_0 {
status = "okay";
};
@ -359,6 +523,12 @@
status = "okay";
};
&remoteproc_adsp {
memory-region = <&adsp_mem>;
firmware-name = "qcom/sc7180/acer/aspire1/qcadsp7180.mbn";
status = "okay";
};
&remoteproc_mpss {
firmware-name = "qcom/sc7180/acer/aspire1/qcmpss7180_nm.mbn";
status = "okay";

2
arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi
View File

@ -141,7 +141,7 @@ ap_ts_pen_1v8: &i2c4 {
};
&panel {
compatible = "kingdisplay,kd116n21-30nv-a010";
compatible = "edp-panel";
};
&pen_insert {

14
arch/arm64/boot/dts/qcom/sc7180.dtsi
View File

@ -2966,8 +2966,8 @@
interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 8 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 9 IRQ_TYPE_LEVEL_HIGH>;
<&pdc 8 IRQ_TYPE_EDGE_BOTH>,
<&pdc 9 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "hs_phy_irq", "ss_phy_irq",
"dm_hs_phy_irq", "dp_hs_phy_irq";
@ -3100,8 +3100,12 @@
interrupt-controller;
#interrupt-cells = <1>;
interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "mdp0-mem";
interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "mdp0-mem",
"cpu-cfg";
iommus = <&apps_smmu 0x800 0x2>;
@ -3576,7 +3580,7 @@
compatible = "qcom,apss-wdt-sc7180", "qcom,kpss-wdt";
reg = <0 0x17c10000 0 0x1000>;
clocks = <&sleep_clk>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
};
timer@17c20000 {

37
arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi
View File

@ -17,6 +17,9 @@
* required by the setup for Chrome boards.
*/
/delete-node/ &cdsp_mem;
/delete-node/ &gpu_zap_mem;
/delete-node/ &gpu_zap_shader;
/delete-node/ &hyp_mem;
/delete-node/ &xbl_mem;
/delete-node/ &reserved_xbl_uefi_log;
@ -24,11 +27,6 @@
/ {
reserved-memory {
adsp_mem: memory@86700000 {
reg = <0x0 0x86700000 0x0 0x2800000>;
no-map;
};
camera_mem: memory@8ad00000 {
reg = <0x0 0x8ad00000 0x0 0x500000>;
no-map;
@ -38,11 +36,6 @@
reg = <0x0 0x8b200000 0x0 0x500000>;
no-map;
};
wpss_mem: memory@9ae00000 {
reg = <0x0 0x9ae00000 0x0 0x1900000>;
no-map;
};
};
};
@ -94,9 +87,31 @@
};
};
/* Currently not used */
&remoteproc_cdsp {
/delete-property/ memory-region;
};
&remoteproc_wpss {
status = "okay";
compatible = "qcom,sc7280-wpss-pil";
clocks = <&gcc GCC_WPSS_AHB_BDG_MST_CLK>,
<&gcc GCC_WPSS_AHB_CLK>,
<&gcc GCC_WPSS_RSCP_CLK>,
<&rpmhcc RPMH_CXO_CLK>;
clock-names = "ahb_bdg",
"ahb",
"rscp",
"xo";
resets = <&aoss_reset AOSS_CC_WCSS_RESTART>,
<&pdc_reset PDC_WPSS_SYNC_RESET>;
reset-names = "restart", "pdc_sync";
qcom,halt-regs = <&tcsr_1 0x17000>;
firmware-name = "ath11k/WCN6750/hw1.0/wpss.mdt";
status = "okay";
};
&scm {

7
arch/arm64/boot/dts/qcom/sc7280-herobrine-lte-sku.dtsi
View File

@ -8,11 +8,6 @@
/ {
reserved-memory {
mpss_mem: memory@8b800000 {
reg = <0x0 0x8b800000 0x0 0xf600000>;
no-map;
};
mba_mem: memory@9c700000 {
reg = <0x0 0x9c700000 0x0 0x200000>;
no-map;
@ -33,6 +28,8 @@
&remoteproc_mpss {
compatible = "qcom,sc7280-mss-pil";
reg = <0 0x04080000 0 0x10000>, <0 0x04180000 0 0x48>;
reg-names = "qdsp6", "rmb";
clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
<&gcc GCC_MSS_OFFLINE_AXI_CLK>,

1
arch/arm64/boot/dts/qcom/sc7280-herobrine-wifi-sku.dtsi
View File

@ -7,5 +7,6 @@
/* WIFI SKUs save 256M by not having modem/mba/rmtfs memory regions defined. */
/delete-node/ &mpss_mem;
/delete-node/ &remoteproc_mpss;
/delete-node/ &rmtfs_mem;

19
arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
View File

@ -499,6 +499,25 @@
status = "okay";
};
&ufs_mem_hc {
reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>;
vcc-supply = <&vreg_l7b_2p9>;
vcc-max-microamp = <800000>;
vccq-supply = <&vreg_l9b_1p2>;
vccq-max-microamp = <900000>;
vccq2-supply = <&vreg_l9b_1p2>;
vccq2-max-microamp = <900000>;
status = "okay";
};
&ufs_mem_phy {
vdda-phy-supply = <&vreg_l10c_0p8>;
vdda-pll-supply = <&vreg_l6b_1p2>;
status = "okay";
};
&usb_1 {
status = "okay";
};

579
arch/arm64/boot/dts/qcom/sc7280.dtsi
View File

@ -15,6 +15,7 @@
#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/firmware/qcom,scm.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/interconnect/qcom,sc7280.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
@ -91,68 +92,93 @@
#size-cells = <2>;
ranges;
wlan_ce_mem: memory@4cd000 {
wlan_ce_mem: wlan-ce@4cd000 {
no-map;
reg = <0x0 0x004cd000 0x0 0x1000>;
};
hyp_mem: memory@80000000 {
hyp_mem: hyp@80000000 {
reg = <0x0 0x80000000 0x0 0x600000>;
no-map;
};
xbl_mem: memory@80600000 {
xbl_mem: xbl@80600000 {
reg = <0x0 0x80600000 0x0 0x200000>;
no-map;
};
aop_mem: memory@80800000 {
aop_mem: aop@80800000 {
reg = <0x0 0x80800000 0x0 0x60000>;
no-map;
};
aop_cmd_db_mem: memory@80860000 {
aop_cmd_db_mem: aop-cmd-db@80860000 {
reg = <0x0 0x80860000 0x0 0x20000>;
compatible = "qcom,cmd-db";
no-map;
};
reserved_xbl_uefi_log: memory@80880000 {
reserved_xbl_uefi_log: xbl-uefi-res@80880000 {
reg = <0x0 0x80884000 0x0 0x10000>;
no-map;
};
sec_apps_mem: memory@808ff000 {
sec_apps_mem: sec-apps@808ff000 {
reg = <0x0 0x808ff000 0x0 0x1000>;
no-map;
};
smem_mem: memory@80900000 {
smem_mem: smem@80900000 {
reg = <0x0 0x80900000 0x0 0x200000>;
no-map;
};
cpucp_mem: memory@80b00000 {
cpucp_mem: cpucp@80b00000 {
no-map;
reg = <0x0 0x80b00000 0x0 0x100000>;
};
wlan_fw_mem: memory@80c00000 {
wlan_fw_mem: wlan-fw@80c00000 {
reg = <0x0 0x80c00000 0x0 0xc00000>;
no-map;
};
video_mem: memory@8b200000 {
adsp_mem: adsp@86700000 {
reg = <0x0 0x86700000 0x0 0x2800000>;
no-map;
};
video_mem: video@8b200000 {
reg = <0x0 0x8b200000 0x0 0x500000>;
no-map;
};
ipa_fw_mem: memory@8b700000 {
cdsp_mem: cdsp@88f00000 {
reg = <0x0 0x88f00000 0x0 0x1e00000>;
no-map;
};
ipa_fw_mem: ipa-fw@8b700000 {
reg = <0 0x8b700000 0 0x10000>;
no-map;
};
rmtfs_mem: memory@9c900000 {
gpu_zap_mem: zap@8b71a000 {
reg = <0 0x8b71a000 0 0x2000>;
no-map;
};
mpss_mem: mpss@8b800000 {
reg = <0x0 0x8b800000 0x0 0xf600000>;
no-map;
};
wpss_mem: wpss@9ae00000 {
reg = <0x0 0x9ae00000 0x0 0x1900000>;
no-map;
};
rmtfs_mem: rmtfs@9c900000 {
compatible = "qcom,rmtfs-mem";
reg = <0x0 0x9c900000 0x0 0x280000>;
no-map;
@ -906,7 +932,7 @@
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>,
<0>, <&pcie1_phy>,
<0>, <0>, <0>,
<&ufs_mem_phy 0>, <&ufs_mem_phy 1>, <&ufs_mem_phy 2>,
<&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
"pcie_0_pipe_clk", "pcie_1_pipe_clk",
@ -2034,6 +2060,11 @@
};
};
rng: rng@10d3000 {
compatible = "qcom,sc7280-trng", "qcom,trng";
reg = <0 0x010d3000 0 0x1000>;
};
cnoc2: interconnect@1500000 {
reg = <0 0x01500000 0 0x1000>;
compatible = "qcom,sc7280-cnoc2";
@ -2126,7 +2157,7 @@
qcom,smem-state-names = "wlan-smp2p-out";
};
pcie1: pci@1c08000 {
pcie1: pcie@1c08000 {
compatible = "qcom,pcie-sc7280";
reg = <0 0x01c08000 0 0x3000>,
<0 0x40000000 0 0xf1d>,
@ -2233,6 +2264,99 @@
status = "disabled";
};
ufs_mem_hc: ufs@1d84000 {
compatible = "qcom,sc7280-ufshc", "qcom,ufshc",
"jedec,ufs-2.0";
reg = <0x0 0x01d84000 0x0 0x3000>;
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
phys = <&ufs_mem_phy>;
phy-names = "ufsphy";
lanes-per-direction = <2>;
#reset-cells = <1>;
resets = <&gcc GCC_UFS_PHY_BCR>;
reset-names = "rst";
power-domains = <&gcc GCC_UFS_PHY_GDSC>;
required-opps = <&rpmhpd_opp_nom>;
iommus = <&apps_smmu 0x80 0x0>;
dma-coherent;
interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&cnoc2 SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "ufs-ddr", "cpu-ufs";
clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
<&gcc GCC_UFS_PHY_AHB_CLK>,
<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
<&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
clock-names = "core_clk",
"bus_aggr_clk",
"iface_clk",
"core_clk_unipro",
"ref_clk",
"tx_lane0_sync_clk",
"rx_lane0_sync_clk",
"rx_lane1_sync_clk";
freq-table-hz =
<75000000 300000000>,
<0 0>,
<0 0>,
<75000000 300000000>,
<0 0>,
<0 0>,
<0 0>,
<0 0>;
status = "disabled";
};
ufs_mem_phy: phy@1d87000 {
compatible = "qcom,sc7280-qmp-ufs-phy";
reg = <0x0 0x01d87000 0x0 0xe00>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
<&gcc GCC_UFS_1_CLKREF_EN>;
clock-names = "ref", "ref_aux", "qref";
power-domains = <&rpmhpd SC7280_MX>;
resets = <&ufs_mem_hc 0>;
reset-names = "ufsphy";
#clock-cells = <1>;
#phy-cells = <0>;
status = "disabled";
};
cryptobam: dma-controller@1dc4000 {
compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
reg = <0x0 0x01dc4000 0x0 0x28000>;
interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
iommus = <&apps_smmu 0x4e4 0x0011>,
<&apps_smmu 0x4e6 0x0011>;
qcom,ee = <0>;
qcom,controlled-remotely;
};
crypto: crypto@1dfa000 {
compatible = "qcom,sc7280-qce", "qcom,sm8150-qce", "qcom,qce";
reg = <0x0 0x01dfa000 0x0 0x6000>;
dmas = <&cryptobam 4>, <&cryptobam 5>;
dma-names = "rx", "tx";
iommus = <&apps_smmu 0x4e4 0x0011>,
<&apps_smmu 0x4e4 0x0011>;
interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "memory";
};
ipa: ipa@1e40000 {
compatible = "qcom,sc7280-ipa";
@ -2598,7 +2722,8 @@
"cx_mem",
"cx_dbgc";
interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
iommus = <&adreno_smmu 0 0x401>;
iommus = <&adreno_smmu 0 0x400>,
<&adreno_smmu 1 0x400>;
operating-points-v2 = <&gpu_opp_table>;
qcom,gmu = <&gmu>;
interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
@ -2608,6 +2733,10 @@
nvmem-cells = <&gpu_speed_bin>;
nvmem-cell-names = "speed_bin";
gpu_zap_shader: zap-shader {
memory-region = <&gpu_zap_mem>;
};
gpu_opp_table: opp-table {
compatible = "operating-points-v2";
@ -2615,14 +2744,14 @@
opp-hz = /bits/ 64 <315000000>;
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
opp-peak-kBps = <1804000>;
opp-supported-hw = <0x03>;
opp-supported-hw = <0x07>;
};
opp-450000000 {
opp-hz = /bits/ 64 <450000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
opp-peak-kBps = <4068000>;
opp-supported-hw = <0x03>;
opp-supported-hw = <0x07>;
};
/* Only applicable for SKUs which has 550Mhz as Fmax */
@ -2637,28 +2766,28 @@
opp-hz = /bits/ 64 <550000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
opp-peak-kBps = <6832000>;
opp-supported-hw = <0x02>;
opp-supported-hw = <0x06>;
};
opp-608000000 {
opp-hz = /bits/ 64 <608000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
opp-peak-kBps = <8368000>;
opp-supported-hw = <0x02>;
opp-supported-hw = <0x06>;
};
opp-700000000 {
opp-hz = /bits/ 64 <700000000>;
opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
opp-peak-kBps = <8532000>;
opp-supported-hw = <0x02>;
opp-supported-hw = <0x06>;
};
opp-812000000 {
opp-hz = /bits/ 64 <812000000>;
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
opp-peak-kBps = <8532000>;
opp-supported-hw = <0x02>;
opp-supported-hw = <0x06>;
};
opp-840000000 {
@ -2772,12 +2901,12 @@
"gpu_cc_hub_aon_clk";
power-domains = <&gpucc GPU_CC_CX_GDSC>;
dma-coherent;
};
remoteproc_mpss: remoteproc@4080000 {
compatible = "qcom,sc7280-mpss-pas";
reg = <0 0x04080000 0 0x10000>, <0 0x04180000 0 0x48>;
reg-names = "qdsp6", "rmb";
reg = <0 0x04080000 0 0x10000>;
interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
<&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
@ -3399,6 +3528,32 @@
#clock-cells = <1>;
#phy-cells = <1>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
usb_dp_qmpphy_out: endpoint {
};
};
port@1 {
reg = <1>;
usb_dp_qmpphy_usb_ss_in: endpoint {
};
};
port@2 {
reg = <2>;
usb_dp_qmpphy_dp_in: endpoint {
};
};
};
};
usb_2: usb@8cf8800 {
@ -3426,8 +3581,8 @@
assigned-clock-rates = <19200000>, <200000000>;
interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 12 IRQ_TYPE_EDGE_RISING>,
<&pdc 13 IRQ_TYPE_EDGE_RISING>;
<&pdc 12 IRQ_TYPE_EDGE_BOTH>,
<&pdc 13 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "hs_phy_irq",
"dp_hs_phy_irq",
"dm_hs_phy_irq";
@ -3479,8 +3634,77 @@
status = "disabled";
};
remoteproc_adsp: remoteproc@3700000 {
compatible = "qcom,sc7280-adsp-pas";
reg = <0 0x03700000 0 0x100>;
interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
<&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog", "fatal", "ready", "handover",
"stop-ack", "shutdown-ack";
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
power-domains = <&rpmhpd SC7280_LCX>,
<&rpmhpd SC7280_LMX>;
power-domain-names = "lcx", "lmx";
memory-region = <&adsp_mem>;
qcom,qmp = <&aoss_qmp>;
qcom,smem-states = <&adsp_smp2p_out 0>;
qcom,smem-state-names = "stop";
status = "disabled";
glink-edge {
interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc IPCC_CLIENT_LPASS
IPCC_MPROC_SIGNAL_GLINK_QMP>;
label = "lpass";
qcom,remote-pid = <2>;
fastrpc {
compatible = "qcom,fastrpc";
qcom,glink-channels = "fastrpcglink-apps-dsp";
label = "adsp";
qcom,non-secure-domain;
#address-cells = <1>;
#size-cells = <0>;
compute-cb@3 {
compatible = "qcom,fastrpc-compute-cb";
reg = <3>;
iommus = <&apps_smmu 0x1803 0x0>;
};
compute-cb@4 {
compatible = "qcom,fastrpc-compute-cb";
reg = <4>;
iommus = <&apps_smmu 0x1804 0x0>;
};
compute-cb@5 {
compatible = "qcom,fastrpc-compute-cb";
reg = <5>;
iommus = <&apps_smmu 0x1805 0x0>;
};
};
};
};
remoteproc_wpss: remoteproc@8a00000 {
compatible = "qcom,sc7280-wpss-pil";
compatible = "qcom,sc7280-wpss-pas";
reg = <0 0x08a00000 0 0x10000>;
interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>,
@ -3492,12 +3716,8 @@
interrupt-names = "wdog", "fatal", "ready", "handover",
"stop-ack", "shutdown-ack";
clocks = <&gcc GCC_WPSS_AHB_BDG_MST_CLK>,
<&gcc GCC_WPSS_AHB_CLK>,
<&gcc GCC_WPSS_RSCP_CLK>,
<&rpmhcc RPMH_CXO_CLK>;
clock-names = "ahb_bdg", "ahb",
"rscp", "xo";
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
power-domains = <&rpmhpd SC7280_CX>,
<&rpmhpd SC7280_MX>;
@ -3510,11 +3730,6 @@
qcom,smem-states = <&wpss_smp2p_out 0>;
qcom,smem-state-names = "stop";
resets = <&aoss_reset AOSS_CC_WCSS_RESTART>,
<&pdc_reset PDC_WPSS_SYNC_RESET>;
reset-names = "restart", "pdc_sync";
qcom,halt-regs = <&tcsr_1 0x17000>;
status = "disabled";
@ -3656,6 +3871,144 @@
qcom,bcm-voters = <&apps_bcm_voter>;
};
remoteproc_cdsp: remoteproc@a300000 {
compatible = "qcom,sc7280-cdsp-pas";
reg = <0 0x0a300000 0 0x10000>;
interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
<&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
<&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
<&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
<&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
<&cdsp_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog", "fatal", "ready", "handover",
"stop-ack", "shutdown-ack";
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
power-domains = <&rpmhpd SC7280_CX>,
<&rpmhpd SC7280_MX>;
power-domain-names = "cx", "mx";
interconnects = <&nsp_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>;
memory-region = <&cdsp_mem>;
qcom,qmp = <&aoss_qmp>;
qcom,smem-states = <&cdsp_smp2p_out 0>;
qcom,smem-state-names = "stop";
status = "disabled";
glink-edge {
interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc IPCC_CLIENT_CDSP
IPCC_MPROC_SIGNAL_GLINK_QMP>;
label = "cdsp";
qcom,remote-pid = <5>;
fastrpc {
compatible = "qcom,fastrpc";
qcom,glink-channels = "fastrpcglink-apps-dsp";
label = "cdsp";
qcom,non-secure-domain;
#address-cells = <1>;
#size-cells = <0>;
compute-cb@1 {
compatible = "qcom,fastrpc-compute-cb";
reg = <1>;
iommus = <&apps_smmu 0x11a1 0x0420>,
<&apps_smmu 0x1181 0x0420>;
};
compute-cb@2 {
compatible = "qcom,fastrpc-compute-cb";
reg = <2>;
iommus = <&apps_smmu 0x11a2 0x0420>,
<&apps_smmu 0x1182 0x0420>;
};
compute-cb@3 {
compatible = "qcom,fastrpc-compute-cb";
reg = <3>;
iommus = <&apps_smmu 0x11a3 0x0420>,
<&apps_smmu 0x1183 0x0420>;
};
compute-cb@4 {
compatible = "qcom,fastrpc-compute-cb";
reg = <4>;
iommus = <&apps_smmu 0x11a4 0x0420>,
<&apps_smmu 0x1184 0x0420>;
};
compute-cb@5 {
compatible = "qcom,fastrpc-compute-cb";
reg = <5>;
iommus = <&apps_smmu 0x11a5 0x0420>,
<&apps_smmu 0x1185 0x0420>;
};
compute-cb@6 {
compatible = "qcom,fastrpc-compute-cb";
reg = <6>;
iommus = <&apps_smmu 0x11a6 0x0420>,
<&apps_smmu 0x1186 0x0420>;
};
compute-cb@7 {
compatible = "qcom,fastrpc-compute-cb";
reg = <7>;
iommus = <&apps_smmu 0x11a7 0x0420>,
<&apps_smmu 0x1187 0x0420>;
};
compute-cb@8 {
compatible = "qcom,fastrpc-compute-cb";
reg = <8>;
iommus = <&apps_smmu 0x11a8 0x0420>,
<&apps_smmu 0x1188 0x0420>;
};
/* note: secure cb9 in downstream */
compute-cb@11 {
compatible = "qcom,fastrpc-compute-cb";
reg = <11>;
iommus = <&apps_smmu 0x11ab 0x0420>,
<&apps_smmu 0x118b 0x0420>;
};
compute-cb@12 {
compatible = "qcom,fastrpc-compute-cb";
reg = <12>;
iommus = <&apps_smmu 0x11ac 0x0420>,
<&apps_smmu 0x118c 0x0420>;
};
compute-cb@13 {
compatible = "qcom,fastrpc-compute-cb";
reg = <13>;
iommus = <&apps_smmu 0x11ad 0x0420>,
<&apps_smmu 0x118d 0x0420>;
};
compute-cb@14 {
compatible = "qcom,fastrpc-compute-cb";
reg = <14>;
iommus = <&apps_smmu 0x11ae 0x0420>,
<&apps_smmu 0x118e 0x0420>;
};
};
};
};
usb_1: usb@a6f8800 {
compatible = "qcom,sc7280-dwc3", "qcom,dwc3";
reg = <0 0x0a6f8800 0 0x400>;
@ -3681,9 +4034,9 @@
assigned-clock-rates = <19200000>, <200000000>;
interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 14 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 14 IRQ_TYPE_EDGE_BOTH>,
<&pdc 15 IRQ_TYPE_EDGE_BOTH>,
<&pdc 17 IRQ_TYPE_EDGE_BOTH>;
<&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hs_phy_irq",
"dp_hs_phy_irq",
"dm_hs_phy_irq",
@ -3793,6 +4146,86 @@
#power-domain-cells = <1>;
};
cci0: cci@ac4a000 {
compatible = "qcom,sc7280-cci", "qcom,msm8996-cci";
reg = <0 0x0ac4a000 0 0x1000>;
interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
<&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
<&camcc CAM_CC_CPAS_AHB_CLK>,
<&camcc CAM_CC_CCI_0_CLK>,
<&camcc CAM_CC_CCI_0_CLK_SRC>;
clock-names = "camnoc_axi",
"slow_ahb_src",
"cpas_ahb",
"cci",
"cci_src";
pinctrl-0 = <&cci0_default &cci1_default>;
pinctrl-1 = <&cci0_sleep &cci1_sleep>;
pinctrl-names = "default", "sleep";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
cci0_i2c0: i2c-bus@0 {
reg = <0>;
clock-frequency = <1000000>;
#address-cells = <1>;
#size-cells = <0>;
};
cci0_i2c1: i2c-bus@1 {
reg = <1>;
clock-frequency = <1000000>;
#address-cells = <1>;
#size-cells = <0>;
};
};
cci1: cci@ac4b000 {
compatible = "qcom,sc7280-cci", "qcom,msm8996-cci";
reg = <0 0x0ac4b000 0 0x1000>;
interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>;
power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
<&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
<&camcc CAM_CC_CPAS_AHB_CLK>,
<&camcc CAM_CC_CCI_1_CLK>,
<&camcc CAM_CC_CCI_1_CLK_SRC>;
clock-names = "camnoc_axi",
"slow_ahb_src",
"cpas_ahb",
"cci",
"cci_src";
pinctrl-0 = <&cci2_default &cci3_default>;
pinctrl-1 = <&cci2_sleep &cci3_sleep>;
pinctrl-names = "default", "sleep";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
cci1_i2c0: i2c-bus@0 {
reg = <0>;
clock-frequency = <1000000>;
#address-cells = <1>;
#size-cells = <0>;
};
cci1_i2c1: i2c-bus@1 {
reg = <1>;
clock-frequency = <1000000>;
#address-cells = <1>;
#size-cells = <0>;
};
};
camcc: clock-controller@ad00000 {
compatible = "qcom,sc7280-camcc";
reg = <0 0x0ad00000 0 0x10000>;
@ -3847,8 +4280,12 @@
interrupt-controller;
#interrupt-cells = <1>;
interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "mdp0-mem";
interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&cnoc2 SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "mdp0-mem",
"cpu-cfg";
iommus = <&apps_smmu 0x900 0x402>;
@ -4298,6 +4735,62 @@
gpio-ranges = <&tlmm 0 0 175>;
wakeup-parent = <&pdc>;
cci0_default: cci0-default-state {
pins = "gpio69", "gpio70";
function = "cci_i2c";
drive-strength = <2>;
bias-pull-up;
};
cci0_sleep: cci0-sleep-state {
pins = "gpio69", "gpio70";
function = "cci_i2c";
drive-strength = <2>;
bias-pull-down;
};
cci1_default: cci1-default-state {
pins = "gpio71", "gpio72";
function = "cci_i2c";
drive-strength = <2>;
bias-pull-up;
};
cci1_sleep: cci1-sleep-state {
pins = "gpio71", "gpio72";
function = "cci_i2c";
drive-strength = <2>;
bias-pull-down;
};
cci2_default: cci2-default-state {
pins = "gpio73", "gpio74";
function = "cci_i2c";
drive-strength = <2>;
bias-pull-up;
};
cci2_sleep: cci2-sleep-state {
pins = "gpio73", "gpio74";
function = "cci_i2c";
drive-strength = <2>;
bias-pull-down;
};
cci3_default: cci3-default-state {
pins = "gpio75", "gpio76";
function = "cci_i2c";
drive-strength = <2>;
bias-pull-up;
};
cci3_sleep: cci3-sleep-state {
pins = "gpio75", "gpio76";
function = "cci_i2c";
drive-strength = <2>;
bias-pull-down;
};
dp_hot_plug_det: dp-hot-plug-det-state {
pins = "gpio47";
function = "dp_hot";
@ -5222,7 +5715,7 @@
compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt";
reg = <0 0x17c10000 0 0x1000>;
clocks = <&sleep_clk>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
status = "reserved"; /* Owned by Gunyah hyp */
};

4
arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts
View File

@ -452,8 +452,8 @@
};
&pcie3 {
perst-gpio = <&tlmm 178 GPIO_ACTIVE_LOW>;
wake-gpio = <&tlmm 180 GPIO_ACTIVE_HIGH>;
perst-gpios = <&tlmm 178 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 180 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&pcie3_default_state>;
pinctrl-names = "default";

12
arch/arm64/boot/dts/qcom/sc8180x-primus.dts
View File

@ -43,7 +43,7 @@
pinctrl-0 = <&hall_int_active_state>;
lid-switch {
gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>;
gpios = <&tlmm 121 GPIO_ACTIVE_LOW>;
linux,input-type = <EV_SW>;
linux,code = <SW_LID>;
wakeup-source;
@ -386,12 +386,18 @@
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
};
vreg_l10e_2p9: ldo10 {
regulator-min-microvolt = <2904000>;
regulator-max-microvolt = <2904000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
};
vreg_l12e: ldo12 {
@ -531,8 +537,8 @@
};
&pcie1 {
perst-gpio = <&tlmm 175 GPIO_ACTIVE_LOW>;
wake-gpio = <&tlmm 177 GPIO_ACTIVE_HIGH>;
perst-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 177 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pcie2_default_state>;

51
arch/arm64/boot/dts/qcom/sc8180x.dtsi
View File

@ -8,6 +8,7 @@
#include <dt-bindings/clock/qcom,gcc-sc8180x.h>
#include <dt-bindings/clock/qcom,gpucc-sm8150.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/interconnect/qcom,sc8180x.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
@ -1684,7 +1685,7 @@
qcom,bcm-voters = <&apps_bcm_voter>;
};
pcie0: pci@1c00000 {
pcie0: pcie@1c00000 {
compatible = "qcom,pcie-sc8180x";
reg = <0 0x01c00000 0 0x3000>,
<0 0x60000000 0 0xf1d>,
@ -1736,7 +1737,6 @@
assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>;
assigned-clock-rates = <19200000>;
iommus = <&apps_smmu 0x1d80 0x7f>;
iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,
<0x100 &apps_smmu 0x1d81 0x1>;
@ -1781,7 +1781,7 @@
status = "disabled";
};
pcie3: pci@1c08000 {
pcie3: pcie@1c08000 {
compatible = "qcom,pcie-sc8180x";
reg = <0 0x01c08000 0 0x3000>,
<0 0x40000000 0 0xf1d>,
@ -1833,7 +1833,6 @@
assigned-clocks = <&gcc GCC_PCIE_3_AUX_CLK>;
assigned-clock-rates = <19200000>;
iommus = <&apps_smmu 0x1e00 0x7f>;
iommu-map = <0x0 &apps_smmu 0x1e00 0x1>,
<0x100 &apps_smmu 0x1e01 0x1>;
@ -1879,7 +1878,7 @@
status = "disabled";
};
pcie1: pci@1c10000 {
pcie1: pcie@1c10000 {
compatible = "qcom,pcie-sc8180x";
reg = <0 0x01c10000 0 0x3000>,
<0 0x68000000 0 0xf1d>,
@ -1931,7 +1930,6 @@
assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
assigned-clock-rates = <19200000>;
iommus = <&apps_smmu 0x1c80 0x7f>;
iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
<0x100 &apps_smmu 0x1c81 0x1>;
@ -1977,7 +1975,7 @@
status = "disabled";
};
pcie2: pci@1c18000 {
pcie2: pcie@1c18000 {
compatible = "qcom,pcie-sc8180x";
reg = <0 0x01c18000 0 0x3000>,
<0 0x70000000 0 0xf1d>,
@ -2029,7 +2027,6 @@
assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>;
assigned-clock-rates = <19200000>;
iommus = <&apps_smmu 0x1d00 0x7f>;
iommu-map = <0x0 &apps_smmu 0x1d00 0x1>,
<0x100 &apps_smmu 0x1d01 0x1>;
@ -2114,6 +2111,14 @@
<0 0>,
<0 0>;
power-domains = <&gcc UFS_PHY_GDSC>;
interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_UFS_MEM_0_CFG QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "ufs-ddr", "cpu-ufs";
status = "disabled";
};
@ -2548,10 +2553,10 @@
usb_prim: usb@a6f8800 {
compatible = "qcom,sc8180x-dwc3", "qcom,dwc3";
reg = <0 0x0a6f8800 0 0x400>;
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 8 IRQ_TYPE_EDGE_BOTH>,
<&pdc 9 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "hs_phy_irq",
"ss_phy_irq",
"dm_hs_phy_irq",
@ -2622,10 +2627,10 @@
"xo";
resets = <&gcc GCC_USB30_SEC_BCR>;
power-domains = <&gcc USB30_SEC_GDSC>;
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>;
interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 10 IRQ_TYPE_EDGE_BOTH>,
<&pdc 11 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "hs_phy_irq", "ss_phy_irq",
"dm_hs_phy_irq", "dp_hs_phy_irq";
@ -2704,11 +2709,15 @@
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
<&gcc GCC_DISP_HF_AXI_CLK>,
<&dispcc DISP_CC_MDSS_MDP_CLK>,
<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
<&dispcc DISP_CC_MDSS_VSYNC_CLK>,
<&dispcc DISP_CC_MDSS_ROT_CLK>,
<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>;
clock-names = "iface",
"bus",
"core",
"vsync";
"vsync",
"rot",
"lut";
assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
@ -3117,8 +3126,6 @@
phys = <&edp_phy>;
phy-names = "dp";
#sound-dai-cells = <0>;
operating-points-v2 = <&edp_opp_table>;
power-domains = <&rpmhpd SC8180X_MMCX>;
@ -3418,10 +3425,12 @@
reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
<0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
#redistributor-regions = <1>;
redistributor-stride = <0 0x20000>;
};
apss_shared: mailbox@17c00000 {
compatible = "qcom,sc8180x-apss-shared";
compatible = "qcom,sc8180x-apss-shared", "qcom,sdm845-apss-shared";
reg = <0x0 0x17c00000 0x0 0x1000>;
#mbox-cells = <1>;
};

2
arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
View File

@ -458,6 +458,8 @@
};
&mdss0_dp3_phy {
compatible = "qcom,sc8280xp-edp-phy";
vdda-phy-supply = <&vreg_l6b>;
vdda-pll-supply = <&vreg_l3b>;

12
arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
View File

@ -82,6 +82,9 @@
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&cam_indicator_en>;
led-camera-indicator {
label = "white:camera-indicator";
function = LED_FUNCTION_INDICATOR;
@ -570,6 +573,7 @@
&mdss0_dp3 {
compatible = "qcom,sc8280xp-edp";
/delete-property/ #sound-dai-cells;
data-lanes = <0 1 2 3>;
@ -601,6 +605,7 @@
};
&mdss0_dp3_phy {
compatible = "qcom,sc8280xp-edp-phy";
vdda-phy-supply = <&vreg_l6b>;
vdda-pll-supply = <&vreg_l3b>;
@ -1277,6 +1282,13 @@
};
};
cam_indicator_en: cam-indicator-en-state {
pins = "gpio28";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
edp_reg_en: edp-reg-en-state {
pins = "gpio25";
function = "gpio";

24
arch/arm64/boot/dts/qcom/sc8280xp.dtsi
View File

@ -8,6 +8,7 @@
#include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
#include <dt-bindings/clock/qcom,gpucc-sc8280xp.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,sc8280xp-camcc.h>
#include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h>
#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/interconnect/qcom,sc8280xp.h>
@ -2731,7 +2732,7 @@
status = "disabled";
};
swr1: soundwire-controller@3210000 {
swr1: soundwire@3210000 {
compatible = "qcom,soundwire-v1.6.0";
reg = <0 0x03210000 0 0x2000>;
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
@ -2807,7 +2808,7 @@
status = "disabled";
};
swr0: soundwire-controller@3250000 {
swr0: soundwire@3250000 {
reg = <0 0x03250000 0 0x2000>;
compatible = "qcom,soundwire-v1.6.0";
interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
@ -2844,7 +2845,7 @@
#reset-cells = <1>;
};
swr2: soundwire-controller@3330000 {
swr2: soundwire@3330000 {
compatible = "qcom,soundwire-v1.6.0";
reg = <0 0x03330000 0 0x2000>;
interrupts = <GIC_SPI 959 IRQ_TYPE_LEVEL_HIGH>,
@ -3450,6 +3451,20 @@
};
};
camcc: clock-controller@ad00000 {
compatible = "qcom,sc8280xp-camcc";
reg = <0 0x0ad00000 0 0x20000>;
clocks = <&gcc GCC_CAMERA_AHB_CLK>,
<&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&sleep_clk>;
power-domains = <&rpmhpd SC8280XP_MMCX>;
required-opps = <&rpmhpd_opp_low_svs>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
mdss0: display-subsystem@ae00000 {
compatible = "qcom,sc8280xp-mdss";
reg = <0 0x0ae00000 0 0x1000>;
@ -4030,6 +4045,7 @@
sram@c3f0000 {
compatible = "qcom,rpmh-stats";
reg = <0 0x0c3f0000 0 0x400>;
qcom,qmp = <&aoss_qmp>;
};
spmi_bus: spmi@c440000 {
@ -4225,7 +4241,7 @@
compatible = "qcom,apss-wdt-sc8280xp", "qcom,kpss-wdt";
reg = <0 0x17c10000 0 0x1000>;
clocks = <&sleep_clk>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
};
timer@17c20000 {

19
arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts
View File

@ -80,6 +80,10 @@
};
};
&lpass {
status = "okay";
};
&pm8953_resin {
status = "okay";
linux,code = <KEY_VOLUMEDOWN>;
@ -239,3 +243,18 @@
&usb3_dwc3 {
dr_mode = "peripheral";
};
&wcnss {
status = "okay";
vddpx-supply = <&pm8953_l5>;
};
&wcnss_iris {
compatible = "qcom,wcn3680";
vddxo-supply = <&pm8953_l7>;
vddrfa-supply = <&pm8953_l19>;
vddpa-supply = <&pm8953_l9>;
vdddig-supply = <&pm8953_l5>;
};

298
arch/arm64/boot/dts/qcom/sdm670.dtsi
View File

@ -6,6 +6,7 @@
* Copyright (c) 2022, Richard Acayan. All rights reserved.
*/
#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
#include <dt-bindings/clock/qcom,gcc-sdm845.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/dma/qcom-gpi.h>
@ -400,6 +401,30 @@
};
};
dsi_opp_table: opp-table-dsi {
compatible = "operating-points-v2";
opp-19200000 {
opp-hz = /bits/ 64 <19200000>;
required-opps = <&rpmhpd_opp_min_svs>;
};
opp-180000000 {
opp-hz = /bits/ 64 <180000000>;
required-opps = <&rpmhpd_opp_low_svs>;
};
opp-275000000 {
opp-hz = /bits/ 64 <275000000>;
required-opps = <&rpmhpd_opp_svs>;
};
opp-358000000 {
opp-hz = /bits/ 64 <358000000>;
required-opps = <&rpmhpd_opp_svs_l1>;
};
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
@ -1297,8 +1322,8 @@
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 488 IRQ_TYPE_EDGE_BOTH>,
<GIC_SPI 489 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "hs_phy_irq", "ss_phy_irq",
"dm_hs_phy_irq", "dp_hs_phy_irq";
@ -1353,6 +1378,273 @@
#interrupt-cells = <4>;
};
mdss: display-subsystem@ae00000 {
compatible = "qcom,sdm670-mdss";
reg = <0 0x0ae00000 0 0x1000>;
reg-names = "mdss";
power-domains = <&dispcc MDSS_GDSC>;
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
<&dispcc DISP_CC_MDSS_MDP_CLK>;
clock-names = "iface", "core";
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <1>;
interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mem_noc SLAVE_EBI_CH0 0>,
<&mmss_noc MASTER_MDP_PORT1 0 &mem_noc SLAVE_EBI_CH0 0>;
interconnect-names = "mdp0-mem", "mdp1-mem";
iommus = <&apps_smmu 0x880 0x8>,
<&apps_smmu 0xc80 0x8>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "disabled";
mdss_mdp: display-controller@ae01000 {
compatible = "qcom,sdm670-dpu";
reg = <0 0x0ae01000 0 0x8f000>,
<0 0x0aeb0000 0 0x2008>;
reg-names = "mdp", "vbif";
clocks = <&gcc GCC_DISP_AXI_CLK>,
<&dispcc DISP_CC_MDSS_AHB_CLK>,
<&dispcc DISP_CC_MDSS_AXI_CLK>,
<&dispcc DISP_CC_MDSS_MDP_CLK>,
<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
clock-names = "gcc-bus", "iface", "bus", "core", "vsync";
assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
assigned-clock-rates = <19200000>;
operating-points-v2 = <&mdp_opp_table>;
power-domains = <&rpmhpd SDM670_CX>;
interrupt-parent = <&mdss>;
interrupts = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dpu_intf0_out: endpoint {
remote-endpoint = <&mdss_dsi0_in>;
};
};
port@1 {
reg = <1>;
dpu_intf1_out: endpoint {
remote-endpoint = <&mdss_dsi1_in>;
};
};
};
mdp_opp_table: opp-table {
compatible = "operating-points-v2";
opp-19200000 {
opp-hz = /bits/ 64 <19200000>;
required-opps = <&rpmhpd_opp_min_svs>;
};
opp-171428571 {
opp-hz = /bits/ 64 <171428571>;
required-opps = <&rpmhpd_opp_low_svs>;
};
opp-358000000 {
opp-hz = /bits/ 64 <358000000>;
required-opps = <&rpmhpd_opp_svs_l1>;
};
opp-430000000 {
opp-hz = /bits/ 64 <430000000>;
required-opps = <&rpmhpd_opp_nom>;
};
};
};
mdss_dsi0: dsi@ae94000 {
compatible = "qcom,sdm670-dsi-ctrl",
"qcom,mdss-dsi-ctrl";
reg = <0 0x0ae94000 0 0x400>;
reg-names = "dsi_ctrl";
interrupt-parent = <&mdss>;
interrupts = <4>;
clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
<&dispcc DISP_CC_MDSS_PCLK0_CLK>,
<&dispcc DISP_CC_MDSS_ESC0_CLK>,
<&dispcc DISP_CC_MDSS_AHB_CLK>,
<&dispcc DISP_CC_MDSS_AXI_CLK>;
clock-names = "byte",
"byte_intf",
"pixel",
"core",
"iface",
"bus";
assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
<&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
assigned-clock-parents = <&mdss_dsi0_phy 0>,
<&mdss_dsi0_phy 1>;
operating-points-v2 = <&dsi_opp_table>;
power-domains = <&rpmhpd SDM670_CX>;
phys = <&mdss_dsi0_phy>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
mdss_dsi0_in: endpoint {
remote-endpoint = <&dpu_intf0_out>;
};
};
port@1 {
reg = <1>;
mdss_dsi0_out: endpoint {
};
};
};
};
mdss_dsi0_phy: phy@ae94400 {
compatible = "qcom,dsi-phy-10nm";
reg = <0 0x0ae94400 0 0x200>,
<0 0x0ae94600 0 0x280>,
<0 0x0ae94a00 0 0x1e0>;
reg-names = "dsi_phy",
"dsi_phy_lane",
"dsi_pll";
#clock-cells = <1>;
#phy-cells = <0>;
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
<&rpmhcc RPMH_CXO_CLK>;
clock-names = "iface", "ref";
status = "disabled";
};
mdss_dsi1: dsi@ae96000 {
compatible = "qcom,sdm670-dsi-ctrl",
"qcom,mdss-dsi-ctrl";
reg = <0 0x0ae96000 0 0x400>;
reg-names = "dsi_ctrl";
interrupt-parent = <&mdss>;
interrupts = <5>;
clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
<&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
<&dispcc DISP_CC_MDSS_PCLK1_CLK>,
<&dispcc DISP_CC_MDSS_ESC1_CLK>,
<&dispcc DISP_CC_MDSS_AHB_CLK>,
<&dispcc DISP_CC_MDSS_AXI_CLK>;
clock-names = "byte",
"byte_intf",
"pixel",
"core",
"iface",
"bus";
assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
<&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
operating-points-v2 = <&dsi_opp_table>;
power-domains = <&rpmhpd SDM670_CX>;
phys = <&mdss_dsi1_phy>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
mdss_dsi1_in: endpoint {
remote-endpoint = <&dpu_intf1_out>;
};
};
port@1 {
reg = <1>;
mdss_dsi1_out: endpoint {
};
};
};
};
mdss_dsi1_phy: phy@ae96400 {
compatible = "qcom,dsi-phy-10nm";
reg = <0 0x0ae96400 0 0x200>,
<0 0x0ae96600 0 0x280>,
<0 0x0ae96a00 0 0x10e>;
reg-names = "dsi_phy",
"dsi_phy_lane",
"dsi_pll";
#clock-cells = <1>;
#phy-cells = <0>;
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
<&rpmhcc RPMH_CXO_CLK>;
clock-names = "iface", "ref";
status = "disabled";
};
};
dispcc: clock-controller@af00000 {
compatible = "qcom,sdm845-dispcc";
reg = <0 0x0af00000 0 0x10000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_DISP_GPLL0_CLK_SRC>,
<&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
<&mdss_dsi0_phy 0>,
<&mdss_dsi0_phy 1>,
<&mdss_dsi1_phy 0>,
<&mdss_dsi1_phy 1>,
<0>,
<0>;
clock-names = "bi_tcxo",
"gcc_disp_gpll0_clk_src",
"gcc_disp_gpll0_div_clk_src",
"dsi0_phy_pll_out_byteclk",
"dsi0_phy_pll_out_dsiclk",
"dsi1_phy_pll_out_byteclk",
"dsi1_phy_pll_out_dsiclk",
"dp_link_clk_divsel_ten",
"dp_vco_divided_clk_src_mux";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
apps_smmu: iommu@15000000 {
compatible = "qcom,sdm670-smmu-500", "qcom,smmu-500", "arm,mmu-500";
reg = <0 0x15000000 0 0x80000>;
@ -1532,7 +1824,7 @@
};
cpufreq_hw: cpufreq@17d43000 {
compatible = "qcom,cpufreq-hw";
compatible = "qcom,sdm670-cpufreq-hw", "qcom,cpufreq-hw";
reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>;
reg-names = "freq-domain0", "freq-domain1";

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