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drm/i915/display: Add PSR interrupt error check function
In order to reuse code of PSR interrupt error check on other PSR functions, it adds psr_interrupt_error_check() function. Cc: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210519000625.3184321-13-lucas.demarchi@intel.com
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8aa2d2ef46
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1 changed files with 29 additions and 18 deletions
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@ -1030,27 +1030,11 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
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IGNORE_PSR2_HW_TRACKING : 0);
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IGNORE_PSR2_HW_TRACKING : 0);
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}
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}
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static void intel_psr_enable_locked(struct intel_dp *intel_dp,
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static bool psr_interrupt_error_check(struct intel_dp *intel_dp)
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const struct intel_crtc_state *crtc_state,
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const struct drm_connector_state *conn_state)
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{
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{
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struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
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struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
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struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
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struct intel_encoder *encoder = &dig_port->base;
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u32 val;
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u32 val;
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drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled);
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intel_dp->psr.psr2_enabled = crtc_state->has_psr2;
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intel_dp->psr.busy_frontbuffer_bits = 0;
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intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
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intel_dp->psr.transcoder = crtc_state->cpu_transcoder;
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/* DC5/DC6 requires at least 6 idle frames */
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val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6);
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intel_dp->psr.dc3co_exit_delay = val;
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intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline;
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intel_dp->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch;
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/*
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/*
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* If a PSR error happened and the driver is reloaded, the EDP_PSR_IIR
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* If a PSR error happened and the driver is reloaded, the EDP_PSR_IIR
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* will still keep the error set even after the reset done in the
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* will still keep the error set even after the reset done in the
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@ -1071,9 +1055,36 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp,
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intel_dp->psr.sink_not_reliable = true;
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intel_dp->psr.sink_not_reliable = true;
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drm_dbg_kms(&dev_priv->drm,
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drm_dbg_kms(&dev_priv->drm,
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"PSR interruption error set, not enabling PSR\n");
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"PSR interruption error set, not enabling PSR\n");
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return;
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return false;
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}
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}
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return true;
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}
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static void intel_psr_enable_locked(struct intel_dp *intel_dp,
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const struct intel_crtc_state *crtc_state,
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const struct drm_connector_state *conn_state)
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{
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struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
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struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
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struct intel_encoder *encoder = &dig_port->base;
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u32 val;
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drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled);
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intel_dp->psr.psr2_enabled = crtc_state->has_psr2;
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intel_dp->psr.busy_frontbuffer_bits = 0;
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intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
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intel_dp->psr.transcoder = crtc_state->cpu_transcoder;
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/* DC5/DC6 requires at least 6 idle frames */
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val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6);
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intel_dp->psr.dc3co_exit_delay = val;
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intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline;
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intel_dp->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch;
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if (!psr_interrupt_error_check(intel_dp))
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return;
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drm_dbg_kms(&dev_priv->drm, "Enabling PSR%s\n",
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drm_dbg_kms(&dev_priv->drm, "Enabling PSR%s\n",
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intel_dp->psr.psr2_enabled ? "2" : "1");
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intel_dp->psr.psr2_enabled ? "2" : "1");
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intel_dp_compute_psr_vsc_sdp(intel_dp, crtc_state, conn_state,
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intel_dp_compute_psr_vsc_sdp(intel_dp, crtc_state, conn_state,
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