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PCI: designware: Use iATU0 for cfg and IO, iATU1 for MEM
Most transactions' type are cfg0 and MEM, so the current iATU usage is not balanced: iATU0 is hot while iATU1 is rarely used. Refactor the iATU usage so we use iATU0 for cfg and IO and iATU1 for MEM. This allocation idea comes from Minghuan Lian <Minghuan.Lian@freescale.com>: [bhelgaas: use link with Message-ID] Link: http://lkml.kernel.org/r/1429091315-31891-3-git-send-email-Minghuan.Lian@freescale.com Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Pratyush Anand <pratyush.anand@gmail.com>
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63503c87f0
commit
2d91b491d5
1 changed files with 45 additions and 36 deletions
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@ -510,6 +510,11 @@ int dw_pcie_host_init(struct pcie_port *pp)
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if (pp->ops->host_init)
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pp->ops->host_init(pp);
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if (!pp->ops->rd_other_conf)
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dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1,
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PCIE_ATU_TYPE_MEM, pp->mem_mod_base,
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pp->mem_bus_addr, pp->mem_size);
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dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
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/* program correct class for RC */
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@ -535,66 +540,70 @@ int dw_pcie_host_init(struct pcie_port *pp)
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static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
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u32 devfn, int where, int size, u32 *val)
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{
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int ret = PCIBIOS_SUCCESSFUL;
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u32 address, busdev;
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int ret, type;
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u32 address, busdev, cfg_size;
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u64 cpu_addr;
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void __iomem *va_cfg_base;
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busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
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PCIE_ATU_FUNC(PCI_FUNC(devfn));
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address = where & ~0x3;
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if (bus->parent->number == pp->root_bus_nr) {
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dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
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PCIE_ATU_TYPE_CFG0, pp->cfg0_mod_base,
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busdev, pp->cfg0_size);
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ret = dw_pcie_cfg_read(pp->va_cfg0_base + address, where, size,
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val);
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dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
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PCIE_ATU_TYPE_MEM, pp->mem_mod_base,
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pp->mem_bus_addr, pp->mem_size);
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type = PCIE_ATU_TYPE_CFG0;
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cpu_addr = pp->cfg0_mod_base;
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cfg_size = pp->cfg0_size;
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va_cfg_base = pp->va_cfg0_base;
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} else {
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dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1,
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PCIE_ATU_TYPE_CFG1, pp->cfg1_mod_base,
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busdev, pp->cfg1_size);
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ret = dw_pcie_cfg_read(pp->va_cfg1_base + address, where, size,
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val);
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dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1,
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PCIE_ATU_TYPE_IO, pp->io_mod_base,
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pp->io_bus_addr, pp->io_size);
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type = PCIE_ATU_TYPE_CFG1;
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cpu_addr = pp->cfg1_mod_base;
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cfg_size = pp->cfg1_size;
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va_cfg_base = pp->va_cfg1_base;
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}
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dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
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type, cpu_addr,
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busdev, cfg_size);
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ret = dw_pcie_cfg_read(va_cfg_base + address, where, size, val);
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dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
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PCIE_ATU_TYPE_IO, pp->io_mod_base,
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pp->io_bus_addr, pp->io_size);
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return ret;
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}
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static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
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u32 devfn, int where, int size, u32 val)
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{
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int ret = PCIBIOS_SUCCESSFUL;
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u32 address, busdev;
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int ret, type;
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u32 address, busdev, cfg_size;
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u64 cpu_addr;
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void __iomem *va_cfg_base;
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busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
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PCIE_ATU_FUNC(PCI_FUNC(devfn));
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address = where & ~0x3;
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if (bus->parent->number == pp->root_bus_nr) {
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dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
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PCIE_ATU_TYPE_CFG0, pp->cfg0_mod_base,
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busdev, pp->cfg0_size);
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ret = dw_pcie_cfg_write(pp->va_cfg0_base + address, where, size,
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val);
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dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
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PCIE_ATU_TYPE_MEM, pp->mem_mod_base,
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pp->mem_bus_addr, pp->mem_size);
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type = PCIE_ATU_TYPE_CFG0;
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cpu_addr = pp->cfg0_mod_base;
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cfg_size = pp->cfg0_size;
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va_cfg_base = pp->va_cfg0_base;
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} else {
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dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1,
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PCIE_ATU_TYPE_CFG1, pp->cfg1_mod_base,
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busdev, pp->cfg1_size);
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ret = dw_pcie_cfg_write(pp->va_cfg1_base + address, where, size,
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val);
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dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1,
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PCIE_ATU_TYPE_IO, pp->io_mod_base,
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pp->io_bus_addr, pp->io_size);
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type = PCIE_ATU_TYPE_CFG1;
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cpu_addr = pp->cfg1_mod_base;
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cfg_size = pp->cfg1_size;
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va_cfg_base = pp->va_cfg1_base;
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}
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dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
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type, cpu_addr,
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busdev, cfg_size);
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ret = dw_pcie_cfg_write(va_cfg_base + address, where, size, val);
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dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
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PCIE_ATU_TYPE_IO, pp->io_mod_base,
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pp->io_bus_addr, pp->io_size);
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return ret;
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}
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