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IB/mlx5: Add ability to hash by IPSEC_SPI when creating a TIR
When a Raw Ethernet QP is created, we actually create a few objects. One of these objects is a TIR. Currently, a TIR could hash (and spread the traffic) by IP or port only. Adding a hashing by IPSec SPI to TIR creation with the required UAPI bit. Signed-off-by: Matan Barak <matanb@mellanox.com> Signed-off-by: Leon Romanovsky <leonro@mellanox.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
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parent
c03faa562d
commit
2d93fc8569
3 changed files with 17 additions and 4 deletions
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@ -856,6 +856,10 @@ static int mlx5_ib_query_device(struct ib_device *ibdev,
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MLX5_RX_HASH_SRC_PORT_UDP |
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MLX5_RX_HASH_SRC_PORT_UDP |
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MLX5_RX_HASH_DST_PORT_UDP |
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MLX5_RX_HASH_DST_PORT_UDP |
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MLX5_RX_HASH_INNER;
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MLX5_RX_HASH_INNER;
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if (mlx5_accel_ipsec_device_caps(dev->mdev) &
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MLX5_ACCEL_IPSEC_CAP_DEVICE)
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resp.rss_caps.rx_hash_fields_mask |=
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MLX5_RX_HASH_IPSEC_SPI;
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resp.response_length += sizeof(resp.rss_caps);
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resp.response_length += sizeof(resp.rss_caps);
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}
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}
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} else {
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} else {
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@ -1413,6 +1413,7 @@ static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
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void *tirc;
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void *tirc;
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void *hfso;
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void *hfso;
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u32 selected_fields = 0;
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u32 selected_fields = 0;
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u32 outer_l4;
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size_t min_resp_len;
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size_t min_resp_len;
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u32 tdn = mucontext->tdn;
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u32 tdn = mucontext->tdn;
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struct mlx5_ib_create_qp_rss ucmd = {};
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struct mlx5_ib_create_qp_rss ucmd = {};
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@ -1543,10 +1544,14 @@ static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
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MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
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MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
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MLX5_L3_PROT_TYPE_IPV6);
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MLX5_L3_PROT_TYPE_IPV6);
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if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
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outer_l4 = ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
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(ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) &&
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(ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) << 0 |
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((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
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((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
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(ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))) {
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(ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) << 1 |
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(ucmd.rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) << 2;
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/* Check that only one l4 protocol is set */
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if (outer_l4 & (outer_l4 - 1)) {
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err = -EINVAL;
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err = -EINVAL;
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goto err;
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goto err;
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}
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}
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@ -1577,6 +1582,9 @@ static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
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(ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
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(ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
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selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT;
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selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT;
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if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI)
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selected_fields |= MLX5_HASH_FIELD_SEL_IPSEC_SPI;
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MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields);
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MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields);
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create_tir:
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create_tir:
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@ -327,6 +327,7 @@ enum mlx5_rx_hash_fields {
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MLX5_RX_HASH_DST_PORT_TCP = 1 << 5,
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MLX5_RX_HASH_DST_PORT_TCP = 1 << 5,
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MLX5_RX_HASH_SRC_PORT_UDP = 1 << 6,
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MLX5_RX_HASH_SRC_PORT_UDP = 1 << 6,
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MLX5_RX_HASH_DST_PORT_UDP = 1 << 7,
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MLX5_RX_HASH_DST_PORT_UDP = 1 << 7,
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MLX5_RX_HASH_IPSEC_SPI = 1 << 8,
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/* Save bits for future fields */
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/* Save bits for future fields */
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MLX5_RX_HASH_INNER = (1UL << 31),
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MLX5_RX_HASH_INNER = (1UL << 31),
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};
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};
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