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can: sja1000: Add Quirk for RZ/N1 SJA1000 CAN controller
As per Chapter 6.5.16 of the RZ/N1 Peripheral Manual, The SJA1000 CAN controller does not support Clock Divider Register compared to the reference Philips SJA1000 device. This patch adds a device quirk to handle this difference. Link: https://lore.kernel.org/all/20220710115248.190280-4-biju.das.jz@bp.renesas.com Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
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2 changed files with 7 additions and 4 deletions
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@ -183,8 +183,9 @@ static void chipset_init(struct net_device *dev)
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{
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struct sja1000_priv *priv = netdev_priv(dev);
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/* set clock divider and output control register */
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priv->write_reg(priv, SJA1000_CDR, priv->cdr | CDR_PELICAN);
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if (!(priv->flags & SJA1000_QUIRK_NO_CDR_REG))
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/* set clock divider and output control register */
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priv->write_reg(priv, SJA1000_CDR, priv->cdr | CDR_PELICAN);
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/* set acceptance filter (accept all) */
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priv->write_reg(priv, SJA1000_ACCC0, 0x00);
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@ -209,7 +210,8 @@ static void sja1000_start(struct net_device *dev)
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set_reset_mode(dev);
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/* Initialize chip if uninitialized at this stage */
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if (!(priv->read_reg(priv, SJA1000_CDR) & CDR_PELICAN))
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if (!(priv->flags & SJA1000_QUIRK_NO_CDR_REG ||
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priv->read_reg(priv, SJA1000_CDR) & CDR_PELICAN))
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chipset_init(dev);
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/* Clear error counters and error code capture */
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@ -145,7 +145,8 @@
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/*
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* Flags for sja1000priv.flags
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*/
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#define SJA1000_CUSTOM_IRQ_HANDLER 0x1
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#define SJA1000_CUSTOM_IRQ_HANDLER BIT(0)
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#define SJA1000_QUIRK_NO_CDR_REG BIT(1)
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/*
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* SJA1000 private data structure
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