powerpc/32: Fix objtool unannotated intra-function call warnings
Fix several annotations in assembly files on PPC32. [Sathvika Vasireddy: Changed subject line and removed Kconfig change to enable objtool, as it is a part of "objtool/powerpc: Enable objtool to be built on ppc" patch in this series.] Tested-by: Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com> Reviewed-by: Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com> Acked-by: Josh Poimboeuf <jpoimboe@kernel.org> Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Signed-off-by: Sathvika Vasireddy <sv@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20221114175754.1131267-7-sv@linux.ibm.com
This commit is contained in:
Christophe Leroy
Michael Ellerman
parent
1c137323e9
commit
2da3776167
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@ -4,6 +4,8 @@
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* Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org)
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*/
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#include <linux/linkage.h>
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#include <asm/processor.h>
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#include <asm/page.h>
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#include <asm/cputable.h>
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@ -81,7 +83,7 @@ _GLOBAL(__setup_cpu_745x)
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blr
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/* Enable caches for 603's, 604, 750 & 7400 */
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setup_common_caches:
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SYM_FUNC_START_LOCAL(setup_common_caches)
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mfspr r11,SPRN_HID0
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andi. r0,r11,HID0_DCE
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ori r11,r11,HID0_ICE|HID0_DCE
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@ -95,11 +97,12 @@ setup_common_caches:
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sync
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isync
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blr
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SYM_FUNC_END(setup_common_caches)
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/* 604, 604e, 604ev, ...
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* Enable superscalar execution & branch history table
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*/
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setup_604_hid0:
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SYM_FUNC_START_LOCAL(setup_604_hid0)
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mfspr r11,SPRN_HID0
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ori r11,r11,HID0_SIED|HID0_BHTE
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ori r8,r11,HID0_BTCD
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@ -110,6 +113,7 @@ setup_604_hid0:
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sync
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isync
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blr
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SYM_FUNC_END(setup_604_hid0)
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/* 7400 <= rev 2.7 and 7410 rev = 1.0 suffer from some
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* erratas we work around here.
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@ -125,13 +129,14 @@ setup_604_hid0:
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* needed once we have applied workaround #5 (though it's
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* not set by Apple's firmware at least).
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*/
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setup_7400_workarounds:
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SYM_FUNC_START_LOCAL(setup_7400_workarounds)
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mfpvr r3
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rlwinm r3,r3,0,20,31
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cmpwi 0,r3,0x0207
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ble 1f
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blr
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setup_7410_workarounds:
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SYM_FUNC_END(setup_7400_workarounds)
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SYM_FUNC_START_LOCAL(setup_7410_workarounds)
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mfpvr r3
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rlwinm r3,r3,0,20,31
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cmpwi 0,r3,0x0100
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@ -151,6 +156,7 @@ setup_7410_workarounds:
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sync
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isync
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blr
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SYM_FUNC_END(setup_7410_workarounds)
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/* 740/750/7400/7410
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* Enable Store Gathering (SGE), Address Broadcast (ABE),
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@ -158,7 +164,7 @@ setup_7410_workarounds:
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* Dynamic Power Management (DPM), Speculative (SPD)
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* Clear Instruction cache throttling (ICTC)
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*/
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setup_750_7400_hid0:
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SYM_FUNC_START_LOCAL(setup_750_7400_hid0)
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mfspr r11,SPRN_HID0
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ori r11,r11,HID0_SGE | HID0_ABE | HID0_BHTE | HID0_BTIC
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oris r11,r11,HID0_DPM@h
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@ -177,12 +183,13 @@ END_FTR_SECTION_IFSET(CPU_FTR_NO_DPM)
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sync
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isync
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blr
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SYM_FUNC_END(setup_750_7400_hid0)
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/* 750cx specific
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* Looks like we have to disable NAP feature for some PLL settings...
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* (waiting for confirmation)
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*/
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setup_750cx:
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SYM_FUNC_START_LOCAL(setup_750cx)
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mfspr r10, SPRN_HID1
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rlwinm r10,r10,4,28,31
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cmpwi cr0,r10,7
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@ -196,11 +203,13 @@ setup_750cx:
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andc r6,r6,r7
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stw r6,CPU_SPEC_FEATURES(r4)
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blr
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SYM_FUNC_END(setup_750cx)
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/* 750fx specific
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*/
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setup_750fx:
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SYM_FUNC_START_LOCAL(setup_750fx)
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blr
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SYM_FUNC_END(setup_750fx)
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/* MPC 745x
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* Enable Store Gathering (SGE), Branch Folding (FOLD)
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@ -212,7 +221,7 @@ setup_750fx:
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* Clear Instruction cache throttling (ICTC)
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* Enable L2 HW prefetch
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*/
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setup_745x_specifics:
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SYM_FUNC_START_LOCAL(setup_745x_specifics)
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/* We check for the presence of an L3 cache setup by
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* the firmware. If any, we disable NAP capability as
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* it's known to be bogus on rev 2.1 and earlier
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@ -270,6 +279,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_NO_DPM)
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sync
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isync
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blr
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SYM_FUNC_END(setup_745x_specifics)
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/*
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* Initialize the FPU registers. This is needed to work around an errata
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@ -8,6 +8,8 @@
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* Benjamin Herrenschmidt <benh@kernel.crashing.org>
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*/
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#include <linux/linkage.h>
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#include <asm/page.h>
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#include <asm/processor.h>
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#include <asm/cputable.h>
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@ -274,7 +276,7 @@ _GLOBAL(flush_dcache_L1)
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blr
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has_L2_cache:
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SYM_FUNC_START_LOCAL(has_L2_cache)
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/* skip L2 cache on P2040/P2040E as they have no L2 cache */
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mfspr r3, SPRN_SVR
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/* shift right by 8 bits and clear E bit of SVR */
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@ -290,9 +292,10 @@ has_L2_cache:
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1:
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li r3, 0
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blr
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SYM_FUNC_END(has_L2_cache)
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/* flush backside L2 cache */
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flush_backside_L2_cache:
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SYM_FUNC_START_LOCAL(flush_backside_L2_cache)
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mflr r10
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bl has_L2_cache
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mtlr r10
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@ -313,6 +316,7 @@ flush_backside_L2_cache:
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bne 1b
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2:
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blr
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SYM_FUNC_END(flush_backside_L2_cache)
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_GLOBAL(cpu_down_flush_e500v2)
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mflr r0
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@ -18,6 +18,8 @@
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#include <linux/err.h>
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#include <linux/sys.h>
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#include <linux/threads.h>
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#include <linux/linkage.h>
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#include <asm/reg.h>
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#include <asm/page.h>
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#include <asm/mmu.h>
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@ -74,17 +76,18 @@ _ASM_NOKPROBE_SYMBOL(prepare_transfer_to_handler)
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#endif /* CONFIG_PPC_BOOK3S_32 || CONFIG_PPC_E500 */
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#if defined(CONFIG_PPC_KUEP) && defined(CONFIG_PPC_BOOK3S_32)
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.globl __kuep_lock
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__kuep_lock:
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SYM_FUNC_START(__kuep_lock)
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lwz r9, THREAD+THSR0(r2)
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update_user_segments_by_4 r9, r10, r11, r12
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blr
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SYM_FUNC_END(__kuep_lock)
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__kuep_unlock:
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SYM_FUNC_START_LOCAL(__kuep_unlock)
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lwz r9, THREAD+THSR0(r2)
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rlwinm r9,r9,0,~SR_NX
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update_user_segments_by_4 r9, r10, r11, r12
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blr
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SYM_FUNC_END(__kuep_unlock)
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.macro kuep_lock
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bl __kuep_lock
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@ -28,6 +28,8 @@
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#include <linux/init.h>
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#include <linux/pgtable.h>
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#include <linux/sizes.h>
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#include <linux/linkage.h>
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#include <asm/processor.h>
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#include <asm/page.h>
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#include <asm/mmu.h>
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@ -662,7 +664,7 @@ start_here:
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* kernel initialization. This maps the first 32 MBytes of memory 1:1
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* virtual to physical and more importantly sets the cache mode.
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*/
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initial_mmu:
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SYM_FUNC_START_LOCAL(initial_mmu)
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tlbia /* Invalidate all TLB entries */
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isync
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@ -711,6 +713,7 @@ initial_mmu:
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mtspr SPRN_EVPR,r0
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blr
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SYM_FUNC_END(initial_mmu)
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_GLOBAL(abort)
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mfspr r13,SPRN_DBCR0
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@ -29,6 +29,8 @@
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#include <linux/init.h>
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#include <linux/threads.h>
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#include <linux/pgtable.h>
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#include <linux/linkage.h>
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#include <asm/processor.h>
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#include <asm/page.h>
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#include <asm/mmu.h>
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@ -885,7 +887,7 @@ KernelSPE:
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* Translate the effec addr in r3 to phys addr. The phys addr will be put
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* into r3(higher 32bit) and r4(lower 32bit)
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*/
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get_phys_addr:
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SYM_FUNC_START_LOCAL(get_phys_addr)
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mfmsr r8
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mfspr r9,SPRN_PID
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rlwinm r9,r9,16,0x3fff0000 /* turn PID into MAS6[SPID] */
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@ -907,6 +909,7 @@ get_phys_addr:
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mfspr r3,SPRN_MAS7
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#endif
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blr
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SYM_FUNC_END(get_phys_addr)
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/*
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* Global functions
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@ -18,6 +18,8 @@
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#include <linux/magic.h>
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#include <linux/pgtable.h>
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#include <linux/sizes.h>
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#include <linux/linkage.h>
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#include <asm/processor.h>
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#include <asm/page.h>
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#include <asm/mmu.h>
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@ -625,7 +627,7 @@ start_here:
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* 24 Mbytes of data, and the 512k IMMR space. Anything not covered by
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* these mappings is mapped by page tables.
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*/
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initial_mmu:
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SYM_FUNC_START_LOCAL(initial_mmu)
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li r8, 0
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mtspr SPRN_MI_CTR, r8 /* remove PINNED ITLB entries */
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lis r10, MD_TWAM@h
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@ -686,6 +688,7 @@ initial_mmu:
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#endif
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mtspr SPRN_DER, r8
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blr
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SYM_FUNC_END(initial_mmu)
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_GLOBAL(mmu_pin_tlb)
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lis r9, (1f - PAGE_OFFSET)@h
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@ -18,6 +18,8 @@
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#include <linux/init.h>
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#include <linux/pgtable.h>
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#include <linux/linkage.h>
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#include <asm/reg.h>
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#include <asm/page.h>
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#include <asm/mmu.h>
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@ -877,7 +879,7 @@ END_MMU_FTR_SECTION_IFCLR(MMU_FTR_HPTE_TABLE)
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* Load stuff into the MMU. Intended to be called with
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* IR=0 and DR=0.
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*/
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early_hash_table:
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SYM_FUNC_START_LOCAL(early_hash_table)
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sync /* Force all PTE updates to finish */
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isync
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tlbia /* Clear all TLB entries */
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@ -888,8 +890,9 @@ early_hash_table:
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ori r6, r6, 3 /* 256kB table */
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mtspr SPRN_SDR1, r6
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blr
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SYM_FUNC_END(early_hash_table)
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load_up_mmu:
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SYM_FUNC_START_LOCAL(load_up_mmu)
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sync /* Force all PTE updates to finish */
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isync
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tlbia /* Clear all TLB entries */
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@ -918,6 +921,7 @@ BEGIN_MMU_FTR_SECTION
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LOAD_BAT(7,r3,r4,r5)
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END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
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blr
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SYM_FUNC_END(load_up_mmu)
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_GLOBAL(load_segment_registers)
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li r0, NUM_USER_SEGMENTS /* load up user segment register values */
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@ -1028,7 +1032,7 @@ END_MMU_FTR_SECTION_IFCLR(MMU_FTR_HPTE_TABLE)
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* this makes sure it's done.
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* -- Cort
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*/
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clear_bats:
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SYM_FUNC_START_LOCAL(clear_bats)
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li r10,0
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mtspr SPRN_DBAT0U,r10
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@ -1072,6 +1076,7 @@ BEGIN_MMU_FTR_SECTION
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mtspr SPRN_IBAT7L,r10
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END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
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blr
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SYM_FUNC_END(clear_bats)
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_GLOBAL(update_bats)
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lis r4, 1f@h
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@ -1108,15 +1113,16 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
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mtspr SPRN_SRR1, r6
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rfi
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flush_tlbs:
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SYM_FUNC_START_LOCAL(flush_tlbs)
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lis r10, 0x40
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1: addic. r10, r10, -0x1000
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tlbie r10
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bgt 1b
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sync
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blr
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SYM_FUNC_END(flush_tlbs)
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mmu_off:
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SYM_FUNC_START_LOCAL(mmu_off)
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addi r4, r3, __after_mmu_off - _start
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mfmsr r3
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andi. r0,r3,MSR_DR|MSR_IR /* MMU enabled? */
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@ -1128,9 +1134,10 @@ mmu_off:
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mtspr SPRN_SRR1,r3
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sync
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rfi
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SYM_FUNC_END(mmu_off)
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/* We use one BAT to map up to 256M of RAM at _PAGE_OFFSET */
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initial_bats:
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SYM_FUNC_START_LOCAL(initial_bats)
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lis r11,PAGE_OFFSET@h
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tophys(r8,r11)
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#ifdef CONFIG_SMP
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@ -1146,9 +1153,10 @@ initial_bats:
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mtspr SPRN_IBAT0U,r11
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isync
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blr
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SYM_FUNC_END(initial_bats)
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#ifdef CONFIG_BOOTX_TEXT
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setup_disp_bat:
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SYM_FUNC_START_LOCAL(setup_disp_bat)
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/*
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* setup the display bat prepared for us in prom.c
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*/
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@ -1164,10 +1172,11 @@ setup_disp_bat:
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mtspr SPRN_DBAT3L,r8
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mtspr SPRN_DBAT3U,r11
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blr
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SYM_FUNC_END(setup_disp_bat)
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#endif /* CONFIG_BOOTX_TEXT */
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#ifdef CONFIG_PPC_EARLY_DEBUG_CPM
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setup_cpm_bat:
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SYM_FUNC_START_LOCAL(setup_cpm_bat)
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lis r8, 0xf000
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ori r8, r8, 0x002a
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mtspr SPRN_DBAT1L, r8
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@ -1177,10 +1186,11 @@ setup_cpm_bat:
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mtspr SPRN_DBAT1U, r11
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blr
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SYM_FUNC_END(setup_cpm_bat)
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#endif
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#ifdef CONFIG_PPC_EARLY_DEBUG_USBGECKO
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setup_usbgecko_bat:
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SYM_FUNC_START_LOCAL(setup_usbgecko_bat)
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/* prepare a BAT for early io */
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#if defined(CONFIG_GAMECUBE)
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lis r8, 0x0c00
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@ -1199,6 +1209,7 @@ setup_usbgecko_bat:
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mtspr SPRN_DBAT1L, r8
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mtspr SPRN_DBAT1U, r11
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blr
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SYM_FUNC_END(setup_usbgecko_bat)
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#endif
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.data
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@ -1,5 +1,7 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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#include <linux/threads.h>
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#include <linux/linkage.h>
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#include <asm/processor.h>
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#include <asm/page.h>
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#include <asm/cputable.h>
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@ -400,7 +402,7 @@ _ASM_NOKPROBE_SYMBOL(swsusp_arch_resume)
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/* FIXME:This construct is actually not useful since we don't shut
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* down the instruction MMU, we could just flip back MSR-DR on.
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*/
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turn_on_mmu:
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SYM_FUNC_START_LOCAL(turn_on_mmu)
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||||
mflr r4
|
||||
mtsrr0 r4
|
||||
mtsrr1 r3
|
||||
|
|
@ -408,4 +410,5 @@ turn_on_mmu:
|
|||
isync
|
||||
rfi
|
||||
_ASM_NOKPROBE_SYMBOL(turn_on_mmu)
|
||||
SYM_FUNC_END(turn_on_mmu)
|
||||
|
||||
|
|
|
|||
|
|
@ -6,6 +6,8 @@
|
|||
*/
|
||||
|
||||
#include <linux/pgtable.h>
|
||||
#include <linux/linkage.h>
|
||||
|
||||
#include <asm/reg.h>
|
||||
#include <asm/page.h>
|
||||
#include <asm/mmu.h>
|
||||
|
|
@ -110,18 +112,22 @@ FPS_THREE_IN(fsel)
|
|||
* R8 = (double*)¶m3 [load_three]
|
||||
* LR = instruction call function
|
||||
*/
|
||||
fpd_load_three:
|
||||
SYM_FUNC_START_LOCAL(fpd_load_three)
|
||||
lfd 2,0(r8) /* load param3 */
|
||||
fpd_load_two:
|
||||
SYM_FUNC_START_LOCAL(fpd_load_two)
|
||||
lfd 1,0(r7) /* load param2 */
|
||||
fpd_load_one:
|
||||
SYM_FUNC_START_LOCAL(fpd_load_one)
|
||||
lfd 0,0(r6) /* load param1 */
|
||||
fpd_load_none:
|
||||
SYM_FUNC_START_LOCAL(fpd_load_none)
|
||||
lfd 3,0(r3) /* load up fpscr value */
|
||||
MTFSF_L(3)
|
||||
lwz r6, 0(r4) /* load cr */
|
||||
mtcr r6
|
||||
blr
|
||||
SYM_FUNC_END(fpd_load_none)
|
||||
SYM_FUNC_END(fpd_load_one)
|
||||
SYM_FUNC_END(fpd_load_two)
|
||||
SYM_FUNC_END(fpd_load_three)
|
||||
|
||||
/*
|
||||
* End of double instruction processing
|
||||
|
|
@ -131,13 +137,14 @@ fpd_load_none:
|
|||
* R5 = (double*)&result
|
||||
* LR = caller of instruction call function
|
||||
*/
|
||||
fpd_return:
|
||||
SYM_FUNC_START_LOCAL(fpd_return)
|
||||
mfcr r6
|
||||
stfd 0,0(r5) /* save result */
|
||||
mffs 0
|
||||
stfd 0,0(r3) /* save new fpscr value */
|
||||
stw r6,0(r4) /* save new cr value */
|
||||
blr
|
||||
SYM_FUNC_END(fpd_return)
|
||||
|
||||
/*
|
||||
* Double operation with no input operand
|
||||
|
|
|
|||
|
|
@ -1,4 +1,6 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#include <linux/linkage.h>
|
||||
|
||||
#include <asm/reg.h>
|
||||
#include <asm/ppc_asm.h>
|
||||
#include <asm/processor.h>
|
||||
|
|
@ -178,7 +180,8 @@ sram_code:
|
|||
|
||||
|
||||
/* local udelay in sram is needed */
|
||||
udelay: /* r11 - tb_ticks_per_usec, r12 - usecs, overwrites r13 */
|
||||
SYM_FUNC_START_LOCAL(udelay)
|
||||
/* r11 - tb_ticks_per_usec, r12 - usecs, overwrites r13 */
|
||||
mullw r12, r12, r11
|
||||
mftb r13 /* start */
|
||||
add r12, r13, r12 /* end */
|
||||
|
|
@ -187,6 +190,7 @@ sram_code:
|
|||
cmp cr0, r13, r12
|
||||
blt 1b
|
||||
blr
|
||||
SYM_FUNC_END(udelay)
|
||||
|
||||
sram_code_end:
|
||||
|
||||
|
|
@ -271,7 +275,7 @@ _ASM_NOKPROBE_SYMBOL(lite5200_wakeup)
|
|||
SAVE_SR(n+2, addr+2); \
|
||||
SAVE_SR(n+3, addr+3);
|
||||
|
||||
save_regs:
|
||||
SYM_FUNC_START_LOCAL(save_regs)
|
||||
stw r0, 0(r4)
|
||||
stw r1, 0x4(r4)
|
||||
stw r2, 0x8(r4)
|
||||
|
|
@ -317,6 +321,7 @@ save_regs:
|
|||
SAVE_SPRN(TBRU, 0x5b)
|
||||
|
||||
blr
|
||||
SYM_FUNC_END(save_regs)
|
||||
|
||||
|
||||
/* restore registers */
|
||||
|
|
@ -336,7 +341,7 @@ save_regs:
|
|||
LOAD_SR(n+2, addr+2); \
|
||||
LOAD_SR(n+3, addr+3);
|
||||
|
||||
restore_regs:
|
||||
SYM_FUNC_START_LOCAL(restore_regs)
|
||||
lis r4, registers@h
|
||||
ori r4, r4, registers@l
|
||||
|
||||
|
|
@ -393,6 +398,7 @@ restore_regs:
|
|||
|
||||
blr
|
||||
_ASM_NOKPROBE_SYMBOL(restore_regs)
|
||||
SYM_FUNC_END(restore_regs)
|
||||
|
||||
|
||||
|
||||
|
|
@ -403,7 +409,7 @@ _ASM_NOKPROBE_SYMBOL(restore_regs)
|
|||
* Flush data cache
|
||||
* Do this by just reading lots of stuff into the cache.
|
||||
*/
|
||||
flush_data_cache:
|
||||
SYM_FUNC_START_LOCAL(flush_data_cache)
|
||||
lis r3,CONFIG_KERNEL_START@h
|
||||
ori r3,r3,CONFIG_KERNEL_START@l
|
||||
li r4,NUM_CACHE_LINES
|
||||
|
|
@ -413,3 +419,4 @@ flush_data_cache:
|
|||
addi r3,r3,L1_CACHE_BYTES /* Next line, please */
|
||||
bdnz 1b
|
||||
blr
|
||||
SYM_FUNC_END(flush_data_cache)
|
||||
|
|
|
|||
Loading…
Reference in New Issue