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clk: qcom: gcc: Add PCIe0 and PCIe1 GDSC for SM8150
Add the PCIe0 and PCIe1 GDSC defines & driver structures for SM8150. Cc: Stephen Boyd <sboyd@kernel.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220302203045.184500-4-bhupesh.sharma@linaro.org
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2 changed files with 22 additions and 0 deletions
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@ -3448,6 +3448,24 @@ static struct clk_branch gcc_video_xo_clk = {
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},
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};
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static struct gdsc pcie_0_gdsc = {
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.gdscr = 0x6b004,
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.pd = {
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.name = "pcie_0_gdsc",
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},
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.pwrsts = PWRSTS_OFF_ON,
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.flags = POLL_CFG_GDSCR,
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};
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static struct gdsc pcie_1_gdsc = {
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.gdscr = 0x8d004,
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.pd = {
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.name = "pcie_1_gdsc",
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},
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.pwrsts = PWRSTS_OFF_ON,
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.flags = POLL_CFG_GDSCR,
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};
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static struct gdsc usb30_prim_gdsc = {
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.gdscr = 0xf004,
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.pd = {
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@ -3714,6 +3732,8 @@ static const struct qcom_reset_map gcc_sm8150_resets[] = {
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};
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static struct gdsc *gcc_sm8150_gdscs[] = {
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[PCIE_0_GDSC] = &pcie_0_gdsc,
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[PCIE_1_GDSC] = &pcie_1_gdsc,
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[USB30_PRIM_GDSC] = &usb30_prim_gdsc,
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[USB30_SEC_GDSC] = &usb30_sec_gdsc,
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};
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@ -241,6 +241,8 @@
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#define GCC_USB_PHY_CFG_AHB2PHY_BCR 28
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/* GCC GDSCRs */
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#define PCIE_0_GDSC 0
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#define PCIE_1_GDSC 1
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#define USB30_PRIM_GDSC 4
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#define USB30_SEC_GDSC 5
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