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drm/amdgpu: drop soc15_init_golden_registers
The golden register arrays were empty so the function was effectively useless. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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670b603c11
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2dd744e0ce
1 changed files with 0 additions and 31 deletions
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@ -231,35 +231,6 @@ static u32 soc15_get_config_memsize(struct amdgpu_device *adev)
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return adev->nbio_funcs->get_memsize(adev);
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}
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static const u32 vega10_golden_init[] =
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{
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};
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static const u32 raven_golden_init[] =
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{
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};
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static void soc15_init_golden_registers(struct amdgpu_device *adev)
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{
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/* Some of the registers might be dependent on GRBM_GFX_INDEX */
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mutex_lock(&adev->grbm_idx_mutex);
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switch (adev->asic_type) {
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case CHIP_VEGA10:
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amdgpu_program_register_sequence(adev,
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vega10_golden_init,
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ARRAY_SIZE(vega10_golden_init));
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break;
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case CHIP_RAVEN:
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amdgpu_program_register_sequence(adev,
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raven_golden_init,
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ARRAY_SIZE(raven_golden_init));
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break;
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default:
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break;
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}
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mutex_unlock(&adev->grbm_idx_mutex);
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}
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static u32 soc15_get_xclk(struct amdgpu_device *adev)
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{
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return adev->clock.spll.reference_freq;
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@ -745,8 +716,6 @@ static int soc15_common_hw_init(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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/* move the golden regs per IP block */
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soc15_init_golden_registers(adev);
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/* enable pcie gen2/3 link */
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soc15_pcie_gen3_enable(adev);
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/* enable aspm */
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