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Merge master.kernel.org:/home/rmk/linux-2.6-arm
* master.kernel.org:/home/rmk/linux-2.6-arm: [ARM] 4298/1: fix memory barriers for DMA coherent and SMP platforms [ARM] 4295/2: Fix error-handling in pxaficp_ir.c (version 2) [ARM] Fix __NR_kexec_load [ARM] Export dma_channel_active() [ARM] 4296/1: ixp4xx: compile fix [ARM] 4289/1: AT91: SAM9260 NAND flash timing
This commit is contained in:
commit
2e175a9004
6 changed files with 49 additions and 43 deletions
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@ -228,6 +228,7 @@ int dma_channel_active(dmach_t channel)
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{
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return dma_chan[channel].active;
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}
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EXPORT_SYMBOL(dma_channel_active);
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void set_dma_page(dmach_t channel, char pagenr)
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{
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@ -320,16 +320,16 @@ void __init at91_add_device_nand(struct at91_nand_data *data)
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at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0)
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| AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
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at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(2) | AT91_SMC_NCS_WRPULSE_(5)
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| AT91_SMC_NRDPULSE_(2) | AT91_SMC_NCS_RDPULSE_(5));
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at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3)
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| AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
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at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(7));
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at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
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if (data->bus_width_16)
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mode = AT91_SMC_DBW_16;
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else
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mode = AT91_SMC_DBW_8;
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at91_sys_write(AT91_SMC_MODE(3), mode | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(1));
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at91_sys_write(AT91_SMC_MODE(3), mode | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(2));
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/* enable pin */
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if (data->enable_pin)
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@ -321,15 +321,22 @@ static void pxa_irda_fir_dma_tx_irq(int channel, void *data)
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pxa_irda_set_speed(si, si->newspeed);
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si->newspeed = 0;
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} else {
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int i = 64;
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ICCR0 = 0;
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pxa_irda_fir_dma_rx_start(si);
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while ((ICSR1 & ICSR1_RNE) && i--)
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(void)ICDR;
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ICCR0 = ICCR0_ITR | ICCR0_RXE;
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if (i < 0)
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printk(KERN_ERR "pxa_ir: cannot clear Rx FIFO!\n");
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}
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netif_wake_queue(dev);
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}
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/* EIF(Error in FIFO/End in Frame) handler for FIR */
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static void pxa_irda_fir_irq_eif(struct pxa_irda *si, struct net_device *dev)
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static void pxa_irda_fir_irq_eif(struct pxa_irda *si, struct net_device *dev, int icsr0)
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{
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unsigned int len, stat, data;
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@ -350,7 +357,7 @@ static void pxa_irda_fir_irq_eif(struct pxa_irda *si, struct net_device *dev)
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}
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if (stat & ICSR1_ROR) {
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printk(KERN_DEBUG "pxa_ir: fir receive overrun\n");
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si->stats.rx_frame_errors++;
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si->stats.rx_over_errors++;
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}
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} else {
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si->dma_rx_buff[len++] = data;
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@ -362,7 +369,15 @@ static void pxa_irda_fir_irq_eif(struct pxa_irda *si, struct net_device *dev)
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if (stat & ICSR1_EOF) {
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/* end of frame. */
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struct sk_buff *skb = alloc_skb(len+1,GFP_ATOMIC);
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struct sk_buff *skb;
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if (icsr0 & ICSR0_FRE) {
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printk(KERN_ERR "pxa_ir: dropping erroneous frame\n");
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si->stats.rx_dropped++;
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return;
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}
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skb = alloc_skb(len+1,GFP_ATOMIC);
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if (!skb) {
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printk(KERN_ERR "pxa_ir: fir out of memory for receive skb\n");
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si->stats.rx_dropped++;
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@ -392,7 +407,7 @@ static irqreturn_t pxa_irda_fir_irq(int irq, void *dev_id)
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{
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struct net_device *dev = dev_id;
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struct pxa_irda *si = netdev_priv(dev);
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int icsr0;
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int icsr0, i = 64;
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/* stop RX DMA */
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DCSR(si->rxdma) &= ~DCSR_RUN;
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@ -412,13 +427,18 @@ static irqreturn_t pxa_irda_fir_irq(int irq, void *dev_id)
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if (icsr0 & ICSR0_EIF) {
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/* An error in FIFO occured, or there is a end of frame */
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pxa_irda_fir_irq_eif(si, dev);
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pxa_irda_fir_irq_eif(si, dev, icsr0);
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}
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ICCR0 = 0;
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pxa_irda_fir_dma_rx_start(si);
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while ((ICSR1 & ICSR1_RNE) && i--)
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(void)ICDR;
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ICCR0 = ICCR0_ITR | ICCR0_RXE;
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if (i < 0)
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printk(KERN_ERR "pxa_ir: cannot clear Rx FIFO!\n");
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return IRQ_HANDLED;
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}
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@ -238,23 +238,6 @@ __ixp4xx_readsl(const volatile void __iomem *bus_addr, u32 *vaddr, u32 count)
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#define memcpy_fromio(a,c,l) _memcpy_fromio((a),(c),(l))
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#define memcpy_toio(c,a,l) _memcpy_toio((c),(a),(l))
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static inline int
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check_signature(const unsigned char __iomem *bus_addr, const unsigned char *signature,
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int length)
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{
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int retval = 0;
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do {
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if (readb(bus_addr) != *signature)
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goto out;
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bus_addr++;
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signature++;
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length--;
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} while (length);
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retval = 1;
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out:
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return retval;
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}
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#endif
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#ifndef CONFIG_PCI
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@ -3,6 +3,7 @@
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#ifdef __KERNEL__
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#include <asm/memory.h>
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#define CPU_ARCH_UNKNOWN 0
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#define CPU_ARCH_ARMv3 1
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@ -154,7 +155,7 @@ extern unsigned int user_debug;
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#define vectors_high() (0)
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#endif
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#if __LINUX_ARM_ARCH__ >= 6
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#if defined(CONFIG_CPU_XSC3) || __LINUX_ARM_ARCH__ >= 6
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#define isb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \
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: : "r" (0) : "memory")
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#define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
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@ -168,22 +169,23 @@ extern unsigned int user_debug;
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#define dmb() __asm__ __volatile__ ("" : : : "memory")
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#endif
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#define mb() barrier()
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#define rmb() barrier()
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#define wmb() barrier()
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#define read_barrier_depends() do { } while(0)
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#ifdef CONFIG_SMP
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#define smp_mb() dmb()
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#define smp_rmb() dmb()
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#define smp_wmb() dmb()
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#define smp_read_barrier_depends() read_barrier_depends()
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#ifndef CONFIG_SMP
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#define mb() do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
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#define rmb() do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
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#define wmb() do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
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#define smp_mb() barrier()
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#define smp_rmb() barrier()
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#define smp_wmb() barrier()
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#else
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#define smp_mb() barrier()
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#define smp_rmb() barrier()
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#define smp_wmb() barrier()
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#define smp_read_barrier_depends() read_barrier_depends()
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#endif /* CONFIG_SMP */
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#define mb() dmb()
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#define rmb() dmb()
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#define wmb() dmb()
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#define smp_mb() dmb()
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#define smp_rmb() dmb()
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#define smp_wmb() dmb()
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#endif
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#define read_barrier_depends() do { } while(0)
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#define smp_read_barrier_depends() do { } while(0)
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#define set_mb(var, value) do { var = value; smp_mb(); } while (0)
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#define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
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@ -372,7 +372,7 @@
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#define __NR_move_pages (__NR_SYSCALL_BASE+344)
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#define __NR_getcpu (__NR_SYSCALL_BASE+345)
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/* 346 for epoll_pwait */
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#define __NR_sys_kexec_load (__NR_SYSCALL_BASE+347)
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#define __NR_kexec_load (__NR_SYSCALL_BASE+347)
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/*
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* The following SWIs are ARM private.
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