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ARM: dts: rockchip: fix PPI misconfiguration on Cortex-A9 socs

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According to [0] pointed out by Marc Zyngier in a report about a
similar error message, PPIs 11 and 13 are edge triggered on
Cortex-A9 socs including the rk3066 and rk3188 which currently
mark them as level triggered.

Until some time ago the gic did not care but commit 992345a58e
("irqchip/gic: WARN if setting the interrupt type for a PPI fails")
introduced a warning for that case.

Fix the warning on these socs by describing the interrupts correctly
and also using the binding constants for easier reading in the future.

[0] http://infocenter.arm.com/help/topic/com.arm.doc.ddi0407f/CCHEIGIC.html

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This commit is contained in:
Heiko Stuebner 2017-03-22 00:05:16 +01:00
parent 2d1f1d4c9f
commit 2e1aa605fa
2 changed files with 4 additions and 4 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
arch/arm/boot/dts/rk3188.dtsi
View file

@ -529,11 +529,11 @@ &emac {
};
&global_timer {
interrupts = <GIC_PPI 11 0xf04>;
interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
};
&local_timer {
interrupts = <GIC_PPI 13 0xf04>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
};
&i2c0 {

4
arch/arm/boot/dts/rk3xxx.dtsi
View file

@ -132,14 +132,14 @@ scu@1013c000 {
global_timer: global-timer@1013c200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0x1013c200 0x20>;
interrupts = <GIC_PPI 11 0x304>;
interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
clocks = <&cru CORE_PERI>;
};
local_timer: local-timer@1013c600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0x1013c600 0x20>;
interrupts = <GIC_PPI 13 0x304>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
clocks = <&cru CORE_PERI>;
};