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drm/i915/mtl: Eliminate subplatforms
Now that we properly match the Xe_LPG IP versions associated with various workarounds, there's no longer any need to define separate MTL subplatform in the driver. Nothing in the code is conditional on MTL-M or MTL-P base platforms. Furthermore, I'm not sure the "M" and "P" designations are even an accurate representation of which specific platforms would have which IP versions; those were mostly just placeholders from a long time ago. The reality is that the IP version present on a platform gets read from a fuse register at driver init; we shouldn't be trying to guess which IP is present based on PCI ID anymore. Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Nemesa Garg <nemesa.garg@intel.com> Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230821180619.650007-18-matthew.d.roper@intel.com
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81af8abe65
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2e3c369f23
4 changed files with 4 additions and 31 deletions
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@ -573,10 +573,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
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#define IS_PONTEVECCHIO(i915) IS_PLATFORM(i915, INTEL_PONTEVECCHIO)
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#define IS_METEORLAKE(i915) IS_PLATFORM(i915, INTEL_METEORLAKE)
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#define IS_METEORLAKE_M(i915) \
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IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_M)
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#define IS_METEORLAKE_P(i915) \
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IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_P)
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#define IS_DG2_G10(i915) \
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IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G10)
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#define IS_DG2_G11(i915) \
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@ -206,14 +206,6 @@ static const u16 subplatform_g12_ids[] = {
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INTEL_DG2_G12_IDS(0),
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};
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static const u16 subplatform_m_ids[] = {
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INTEL_MTL_M_IDS(0),
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};
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static const u16 subplatform_p_ids[] = {
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INTEL_MTL_P_IDS(0),
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};
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static bool find_devid(u16 id, const u16 *p, unsigned int num)
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{
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for (; num; num--, p++) {
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@ -275,12 +267,6 @@ static void intel_device_info_subplatform_init(struct drm_i915_private *i915)
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} else if (find_devid(devid, subplatform_g12_ids,
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ARRAY_SIZE(subplatform_g12_ids))) {
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mask = BIT(INTEL_SUBPLATFORM_G12);
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} else if (find_devid(devid, subplatform_m_ids,
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ARRAY_SIZE(subplatform_m_ids))) {
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mask = BIT(INTEL_SUBPLATFORM_M);
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} else if (find_devid(devid, subplatform_p_ids,
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ARRAY_SIZE(subplatform_p_ids))) {
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mask = BIT(INTEL_SUBPLATFORM_P);
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}
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GEM_BUG_ON(mask & ~INTEL_SUBPLATFORM_MASK);
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@ -129,10 +129,6 @@ enum intel_platform {
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#define INTEL_SUBPLATFORM_N 1
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#define INTEL_SUBPLATFORM_RPLU 2
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/* MTL */
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#define INTEL_SUBPLATFORM_M 0
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#define INTEL_SUBPLATFORM_P 1
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enum intel_ppgtt_type {
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INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,
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INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING,
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@ -738,18 +738,13 @@
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#define INTEL_ATS_M_IDS(info) \
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INTEL_ATS_M150_IDS(info), \
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INTEL_ATS_M75_IDS(info)
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/* MTL */
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#define INTEL_MTL_M_IDS(info) \
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INTEL_VGA_DEVICE(0x7D40, info), \
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INTEL_VGA_DEVICE(0x7D60, info)
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#define INTEL_MTL_P_IDS(info) \
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/* MTL */
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#define INTEL_MTL_IDS(info) \
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INTEL_VGA_DEVICE(0x7D40, info), \
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INTEL_VGA_DEVICE(0x7D45, info), \
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INTEL_VGA_DEVICE(0x7D55, info), \
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INTEL_VGA_DEVICE(0x7D60, info), \
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INTEL_VGA_DEVICE(0x7DD5, info)
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#define INTEL_MTL_IDS(info) \
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INTEL_MTL_M_IDS(info), \
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INTEL_MTL_P_IDS(info)
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#endif /* _I915_PCIIDS_H */
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