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spi: spi-mem: stm32-qspi: add suspend/resume support
This patch adds suspend and resume support for spi-stm32-qspi drivers. Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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parent
3949ba3b37
commit
2e541b64ee
1 changed files with 35 additions and 4 deletions
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@ -13,6 +13,7 @@
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#include <linux/mutex.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/platform_device.h>
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#include <linux/reset.h>
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#include <linux/sizes.h>
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@ -101,6 +102,9 @@ struct stm32_qspi {
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struct completion data_completion;
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u32 fmode;
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u32 cr_reg;
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u32 dcr_reg;
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/*
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* to protect device configuration, could be different between
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* 2 flash access (bk1, bk2)
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@ -355,7 +359,7 @@ static int stm32_qspi_setup(struct spi_device *spi)
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struct spi_controller *ctrl = spi->master;
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struct stm32_qspi *qspi = spi_controller_get_devdata(ctrl);
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struct stm32_qspi_flash *flash;
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u32 cr, presc;
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u32 presc;
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if (ctrl->busy)
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return -EBUSY;
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@ -371,11 +375,12 @@ static int stm32_qspi_setup(struct spi_device *spi)
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flash->presc = presc;
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mutex_lock(&qspi->lock);
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cr = FIELD_PREP(CR_FTHRES_MASK, 3) | CR_SSHIFT | CR_EN;
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writel_relaxed(cr, qspi->io_base + QSPI_CR);
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qspi->cr_reg = FIELD_PREP(CR_FTHRES_MASK, 3) | CR_SSHIFT | CR_EN;
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writel_relaxed(qspi->cr_reg, qspi->io_base + QSPI_CR);
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/* set dcr fsize to max address */
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writel_relaxed(DCR_FSIZE_MASK, qspi->io_base + QSPI_DCR);
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qspi->dcr_reg = DCR_FSIZE_MASK;
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writel_relaxed(qspi->dcr_reg, qspi->io_base + QSPI_DCR);
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mutex_unlock(&qspi->lock);
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return 0;
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@ -489,6 +494,31 @@ static int stm32_qspi_remove(struct platform_device *pdev)
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return 0;
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}
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static int __maybe_unused stm32_qspi_suspend(struct device *dev)
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{
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struct stm32_qspi *qspi = dev_get_drvdata(dev);
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clk_disable_unprepare(qspi->clk);
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pinctrl_pm_select_sleep_state(dev);
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return 0;
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}
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static int __maybe_unused stm32_qspi_resume(struct device *dev)
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{
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struct stm32_qspi *qspi = dev_get_drvdata(dev);
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pinctrl_pm_select_default_state(dev);
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clk_prepare_enable(qspi->clk);
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writel_relaxed(qspi->cr_reg, qspi->io_base + QSPI_CR);
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writel_relaxed(qspi->dcr_reg, qspi->io_base + QSPI_DCR);
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return 0;
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}
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SIMPLE_DEV_PM_OPS(stm32_qspi_pm_ops, stm32_qspi_suspend, stm32_qspi_resume);
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static const struct of_device_id stm32_qspi_match[] = {
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{.compatible = "st,stm32f469-qspi"},
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{}
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@ -501,6 +531,7 @@ static struct platform_driver stm32_qspi_driver = {
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.driver = {
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.name = "stm32-qspi",
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.of_match_table = stm32_qspi_match,
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.pm = &stm32_qspi_pm_ops,
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},
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};
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module_platform_driver(stm32_qspi_driver);
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