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mtd: rawnand: arasan: Update NAND bus clock instead of system clock
commit7499bfeedb
upstream. In current implementation the Arasan NAND driver is updating the system clock(i.e., anand->clk) in accordance to the timing modes (i.e., SDR or NVDDR). But as per the Arasan NAND controller spec the flash clock or the NAND bus clock(i.e., nfc->bus_clk), need to be updated instead. This patch keeps the system clock unchanged and updates the NAND bus clock as per the timing modes. Fixes:197b88fecc
("mtd: rawnand: arasan: Add new Arasan NAND controller") CC: stable@vger.kernel.org # 5.8+ Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20220628154824.12222-2-amit.kumar-mahapatra@xilinx.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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1 changed files with 4 additions and 4 deletions
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@ -347,17 +347,17 @@ static int anfc_select_target(struct nand_chip *chip, int target)
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/* Update clock frequency */
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if (nfc->cur_clk != anand->clk) {
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clk_disable_unprepare(nfc->controller_clk);
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ret = clk_set_rate(nfc->controller_clk, anand->clk);
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clk_disable_unprepare(nfc->bus_clk);
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ret = clk_set_rate(nfc->bus_clk, anand->clk);
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if (ret) {
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dev_err(nfc->dev, "Failed to change clock rate\n");
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return ret;
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}
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ret = clk_prepare_enable(nfc->controller_clk);
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ret = clk_prepare_enable(nfc->bus_clk);
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if (ret) {
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dev_err(nfc->dev,
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"Failed to re-enable the controller clock\n");
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"Failed to re-enable the bus clock\n");
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return ret;
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}
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