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dmaengine: zxdma: Support cyclic dma
Support cyclic dma for audio playback Signed-off-by: Jun Nie <jun.nie@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
This commit is contained in:
parent
9bde2823dc
commit
2f2560e348
1 changed files with 84 additions and 9 deletions
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@ -101,6 +101,7 @@ struct zx_dma_chan {
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struct dma_slave_config slave_cfg;
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int id; /* Request phy chan id */
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u32 ccfg;
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u32 cyclic;
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struct virt_dma_chan vc;
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struct zx_dma_phy *phy;
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struct list_head node;
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@ -278,7 +279,7 @@ static irqreturn_t zx_dma_int_handler(int irq, void *dev_id)
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u32 serr = readl_relaxed(d->base + REG_ZX_SRC_ERR_IRQ);
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u32 derr = readl_relaxed(d->base + REG_ZX_DST_ERR_IRQ);
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u32 cfg = readl_relaxed(d->base + REG_ZX_CFG_ERR_IRQ);
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u32 i, irq_chan = 0;
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u32 i, irq_chan = 0, task = 0;
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while (tc) {
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i = __ffs(tc);
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@ -289,11 +290,16 @@ static irqreturn_t zx_dma_int_handler(int irq, void *dev_id)
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unsigned long flags;
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spin_lock_irqsave(&c->vc.lock, flags);
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vchan_cookie_complete(&p->ds_run->vd);
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p->ds_done = p->ds_run;
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if (c->cyclic) {
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vchan_cyclic_callback(&p->ds_run->vd);
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} else {
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vchan_cookie_complete(&p->ds_run->vd);
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p->ds_done = p->ds_run;
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task = 1;
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}
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spin_unlock_irqrestore(&c->vc.lock, flags);
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irq_chan |= BIT(i);
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}
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irq_chan |= BIT(i);
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}
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if (serr || derr || cfg)
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@ -305,12 +311,9 @@ static irqreturn_t zx_dma_int_handler(int irq, void *dev_id)
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writel_relaxed(derr, d->base + REG_ZX_DST_ERR_IRQ_RAW);
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writel_relaxed(cfg, d->base + REG_ZX_CFG_ERR_IRQ_RAW);
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if (irq_chan) {
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if (task)
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zx_dma_task(d);
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return IRQ_HANDLED;
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} else {
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return IRQ_NONE;
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}
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return IRQ_HANDLED;
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}
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static void zx_dma_free_chan_resources(struct dma_chan *chan)
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@ -534,6 +537,7 @@ static struct dma_async_tx_descriptor *zx_dma_prep_memcpy(
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len -= copy;
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} while (len);
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c->cyclic = 0;
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ds->desc_hw[num - 1].lli = 0; /* end of link */
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ds->desc_hw[num - 1].ctr |= ZX_IRQ_ENABLE_ALL;
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return vchan_tx_prep(&c->vc, &ds->vd, flags);
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@ -566,6 +570,7 @@ static struct dma_async_tx_descriptor *zx_dma_prep_slave_sg(
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if (!ds)
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return NULL;
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c->cyclic = 0;
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num = 0;
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for_each_sg(sgl, sg, sglen, i) {
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addr = sg_dma_address(sg);
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@ -596,6 +601,49 @@ static struct dma_async_tx_descriptor *zx_dma_prep_slave_sg(
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return vchan_tx_prep(&c->vc, &ds->vd, flags);
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}
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static struct dma_async_tx_descriptor *zx_dma_prep_dma_cyclic(
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struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
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size_t period_len, enum dma_transfer_direction dir,
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unsigned long flags)
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{
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struct zx_dma_chan *c = to_zx_chan(chan);
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struct zx_dma_desc_sw *ds;
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dma_addr_t src = 0, dst = 0;
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int num_periods = buf_len / period_len;
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int buf = 0, num = 0;
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if (period_len > DMA_MAX_SIZE) {
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dev_err(chan->device->dev, "maximum period size exceeded\n");
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return NULL;
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}
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if (zx_pre_config(c, dir))
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return NULL;
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ds = zx_alloc_desc_resource(num_periods, chan);
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if (!ds)
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return NULL;
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c->cyclic = 1;
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while (buf < buf_len) {
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if (dir == DMA_MEM_TO_DEV) {
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src = dma_addr;
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dst = c->dev_addr;
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} else if (dir == DMA_DEV_TO_MEM) {
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src = c->dev_addr;
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dst = dma_addr;
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}
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zx_dma_fill_desc(ds, dst, src, period_len, num++,
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c->ccfg | ZX_IRQ_ENABLE_ALL);
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dma_addr += period_len;
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buf += period_len;
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}
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ds->desc_hw[num - 1].lli = ds->desc_hw_lli;
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ds->size = buf_len;
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return vchan_tx_prep(&c->vc, &ds->vd, flags);
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}
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static int zx_dma_config(struct dma_chan *chan,
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struct dma_slave_config *cfg)
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{
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@ -641,6 +689,30 @@ static int zx_dma_terminate_all(struct dma_chan *chan)
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return 0;
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}
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static int zx_dma_transfer_pause(struct dma_chan *chan)
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{
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struct zx_dma_chan *c = to_zx_chan(chan);
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u32 val = 0;
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val = readl_relaxed(c->phy->base + REG_ZX_CTRL);
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val &= ~ZX_CH_ENABLE;
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writel_relaxed(val, c->phy->base + REG_ZX_CTRL);
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return 0;
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}
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static int zx_dma_transfer_resume(struct dma_chan *chan)
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{
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struct zx_dma_chan *c = to_zx_chan(chan);
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u32 val = 0;
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val = readl_relaxed(c->phy->base + REG_ZX_CTRL);
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val |= ZX_CH_ENABLE;
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writel_relaxed(val, c->phy->base + REG_ZX_CTRL);
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return 0;
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}
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static void zx_dma_free_desc(struct virt_dma_desc *vd)
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{
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struct zx_dma_desc_sw *ds =
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@ -745,9 +817,12 @@ static int zx_dma_probe(struct platform_device *op)
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d->slave.device_tx_status = zx_dma_tx_status;
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d->slave.device_prep_dma_memcpy = zx_dma_prep_memcpy;
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d->slave.device_prep_slave_sg = zx_dma_prep_slave_sg;
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d->slave.device_prep_dma_cyclic = zx_dma_prep_dma_cyclic;
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d->slave.device_issue_pending = zx_dma_issue_pending;
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d->slave.device_config = zx_dma_config;
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d->slave.device_terminate_all = zx_dma_terminate_all;
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d->slave.device_pause = zx_dma_transfer_pause;
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d->slave.device_resume = zx_dma_transfer_resume;
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d->slave.copy_align = DMA_ALIGN;
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d->slave.src_addr_widths = ZX_DMA_BUSWIDTHS;
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d->slave.dst_addr_widths = ZX_DMA_BUSWIDTHS;
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