mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-05 18:39:59 +00:00
Merge remote-tracking branch 'scott/next' into next
Highlights include corenet board file consolidation, the ability to run userspaces with lwsync on e500v1/v2, some cleanup patches that other KVM patches will build on, support for stripped-down e6500 emulation targets, and some fixes of minor longstanding issues.
This commit is contained in:
commit
2f29e3a561
51 changed files with 964 additions and 1081 deletions
|
@ -420,7 +420,7 @@ config FA_DUMP
|
|||
|
||||
config IRQ_ALL_CPUS
|
||||
bool "Distribute interrupts on all CPUs by default"
|
||||
depends on SMP && !MV64360
|
||||
depends on SMP
|
||||
help
|
||||
This option gives the kernel permission to distribute IRQs across
|
||||
multiple CPUs. Saying N here will route all IRQs to the first
|
||||
|
|
218
arch/powerpc/boot/dts/b4860emu.dts
Normal file
218
arch/powerpc/boot/dts/b4860emu.dts
Normal file
|
@ -0,0 +1,218 @@
|
|||
/*
|
||||
* B4860 emulator Device Tree Source
|
||||
*
|
||||
* Copyright 2013 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* This software is provided by Freescale Semiconductor "as is" and any
|
||||
* express or implied warranties, including, but not limited to, the implied
|
||||
* warranties of merchantability and fitness for a particular purpose are
|
||||
* disclaimed. In no event shall Freescale Semiconductor be liable for any
|
||||
* direct, indirect, incidental, special, exemplary, or consequential damages
|
||||
* (including, but not limited to, procurement of substitute goods or services;
|
||||
* loss of use, data, or profits; or business interruption) however caused and
|
||||
* on any theory of liability, whether in contract, strict liability, or tort
|
||||
* (including negligence or otherwise) arising in any way out of the use of
|
||||
* this software, even if advised of the possibility of such damage.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "fsl/e6500_power_isa.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "fsl,B4860";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
aliases {
|
||||
ccsr = &soc;
|
||||
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
serial2 = &serial2;
|
||||
serial3 = &serial3;
|
||||
dma0 = &dma0;
|
||||
dma1 = &dma1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: PowerPC,e6500@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0 1>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
cpu1: PowerPC,e6500@2 {
|
||||
device_type = "cpu";
|
||||
reg = <2 3>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
cpu2: PowerPC,e6500@4 {
|
||||
device_type = "cpu";
|
||||
reg = <4 5>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
cpu3: PowerPC,e6500@6 {
|
||||
device_type = "cpu";
|
||||
reg = <6 7>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/ {
|
||||
model = "fsl,B4860QDS";
|
||||
compatible = "fsl,B4860EMU", "fsl,B4860QDS";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
ifc: localbus@ffe124000 {
|
||||
reg = <0xf 0xfe124000 0 0x2000>;
|
||||
ranges = <0 0 0xf 0xe8000000 0x08000000
|
||||
2 0 0xf 0xff800000 0x00010000
|
||||
3 0 0xf 0xffdf0000 0x00008000>;
|
||||
|
||||
nor@0,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "cfi-flash";
|
||||
reg = <0x0 0x0 0x8000000>;
|
||||
bank-width = <2>;
|
||||
device-width = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
};
|
||||
|
||||
soc: soc@ffe000000 {
|
||||
ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
|
||||
reg = <0xf 0xfe000000 0 0x00001000>;
|
||||
};
|
||||
};
|
||||
|
||||
&ifc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,ifc", "simple-bus";
|
||||
interrupts = <25 2 0 0>;
|
||||
};
|
||||
|
||||
&soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "simple-bus";
|
||||
|
||||
soc-sram-error {
|
||||
compatible = "fsl,soc-sram-error";
|
||||
interrupts = <16 2 1 2>;
|
||||
};
|
||||
|
||||
corenet-law@0 {
|
||||
compatible = "fsl,corenet-law";
|
||||
reg = <0x0 0x1000>;
|
||||
fsl,num-laws = <32>;
|
||||
};
|
||||
|
||||
ddr1: memory-controller@8000 {
|
||||
compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
|
||||
reg = <0x8000 0x1000>;
|
||||
interrupts = <16 2 1 8>;
|
||||
};
|
||||
|
||||
ddr2: memory-controller@9000 {
|
||||
compatible = "fsl,qoriq-memory-controller-v4.5","fsl,qoriq-memory-controller";
|
||||
reg = <0x9000 0x1000>;
|
||||
interrupts = <16 2 1 9>;
|
||||
};
|
||||
|
||||
cpc: l3-cache-controller@10000 {
|
||||
compatible = "fsl,b4-l3-cache-controller", "cache";
|
||||
reg = <0x10000 0x1000
|
||||
0x11000 0x1000>;
|
||||
interrupts = <16 2 1 4>;
|
||||
};
|
||||
|
||||
corenet-cf@18000 {
|
||||
compatible = "fsl,b4-corenet-cf";
|
||||
reg = <0x18000 0x1000>;
|
||||
interrupts = <16 2 1 0>;
|
||||
fsl,ccf-num-csdids = <32>;
|
||||
fsl,ccf-num-snoopids = <32>;
|
||||
};
|
||||
|
||||
iommu@20000 {
|
||||
compatible = "fsl,pamu-v1.0", "fsl,pamu";
|
||||
reg = <0x20000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupts = <
|
||||
24 2 0 0
|
||||
16 2 1 1>;
|
||||
pamu0: pamu@0 {
|
||||
reg = <0 0x1000>;
|
||||
fsl,primary-cache-geometry = <8 1>;
|
||||
fsl,secondary-cache-geometry = <32 2>;
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "fsl/qoriq-mpic.dtsi"
|
||||
|
||||
guts: global-utilities@e0000 {
|
||||
compatible = "fsl,b4-device-config";
|
||||
reg = <0xe0000 0xe00>;
|
||||
fsl,has-rstcr;
|
||||
fsl,liodn-bits = <12>;
|
||||
};
|
||||
|
||||
clockgen: global-utilities@e1000 {
|
||||
compatible = "fsl,b4-clockgen", "fsl,qoriq-clockgen-2.0";
|
||||
reg = <0xe1000 0x1000>;
|
||||
};
|
||||
|
||||
/include/ "fsl/qoriq-dma-0.dtsi"
|
||||
dma@100300 {
|
||||
fsl,iommu-parent = <&pamu0>;
|
||||
fsl,liodn-reg = <&guts 0x580>; /* DMA1LIODNR */
|
||||
};
|
||||
|
||||
/include/ "fsl/qoriq-dma-1.dtsi"
|
||||
dma@101300 {
|
||||
fsl,iommu-parent = <&pamu0>;
|
||||
fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */
|
||||
};
|
||||
|
||||
/include/ "fsl/qoriq-i2c-0.dtsi"
|
||||
/include/ "fsl/qoriq-i2c-1.dtsi"
|
||||
/include/ "fsl/qoriq-duart-0.dtsi"
|
||||
/include/ "fsl/qoriq-duart-1.dtsi"
|
||||
|
||||
L2: l2-cache-controller@c20000 {
|
||||
compatible = "fsl,b4-l2-cache-controller";
|
||||
reg = <0xc20000 0x1000>;
|
||||
next-level-cache = <&cpc>;
|
||||
};
|
||||
};
|
|
@ -120,25 +120,38 @@ sdhc@114000 {
|
|||
};
|
||||
|
||||
i2c@118000 {
|
||||
eeprom@50 {
|
||||
compatible = "at24,24c64";
|
||||
reg = <0x50>;
|
||||
};
|
||||
eeprom@51 {
|
||||
compatible = "at24,24c256";
|
||||
reg = <0x51>;
|
||||
};
|
||||
eeprom@53 {
|
||||
compatible = "at24,24c256";
|
||||
reg = <0x53>;
|
||||
};
|
||||
eeprom@57 {
|
||||
compatible = "at24,24c256";
|
||||
reg = <0x57>;
|
||||
};
|
||||
rtc@68 {
|
||||
compatible = "dallas,ds3232";
|
||||
reg = <0x68>;
|
||||
mux@77 {
|
||||
compatible = "nxp,pca9547";
|
||||
reg = <0x77>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
i2c@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
|
||||
eeprom@50 {
|
||||
compatible = "at24,24c64";
|
||||
reg = <0x50>;
|
||||
};
|
||||
eeprom@51 {
|
||||
compatible = "at24,24c256";
|
||||
reg = <0x51>;
|
||||
};
|
||||
eeprom@53 {
|
||||
compatible = "at24,24c256";
|
||||
reg = <0x53>;
|
||||
};
|
||||
eeprom@57 {
|
||||
compatible = "at24,24c256";
|
||||
reg = <0x57>;
|
||||
};
|
||||
rtc@68 {
|
||||
compatible = "dallas,ds3232";
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
@ -45,6 +45,7 @@ memory {
|
|||
ifc: ifc@fffe1e000 {
|
||||
reg = <0xf 0xffe1e000 0 0x2000>;
|
||||
ranges = <0x0 0x0 0xf 0xec000000 0x04000000
|
||||
0x1 0x0 0xf 0xff800000 0x00010000
|
||||
0x2 0x0 0xf 0xffdf0000 0x00010000>;
|
||||
|
||||
};
|
||||
|
|
|
@ -34,6 +34,8 @@
|
|||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "e6500_power_isa.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "fsl,B4420";
|
||||
#address-cells = <2>;
|
||||
|
|
|
@ -41,7 +41,7 @@ &pci0 {
|
|||
|
||||
&rio {
|
||||
compatible = "fsl,srio";
|
||||
interrupts = <16 2 1 11>;
|
||||
interrupts = <16 2 1 20>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
fsl,iommu-parent = <&pamu0>;
|
||||
|
|
|
@ -34,6 +34,8 @@
|
|||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "e6500_power_isa.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "fsl,B4860";
|
||||
#address-cells = <2>;
|
||||
|
|
|
@ -130,7 +130,7 @@ usb@22000 {
|
|||
|
||||
/include/ "pq3-esdhc-0.dtsi"
|
||||
sdhc@2e000 {
|
||||
fsl,sdhci-auto-cmd12;
|
||||
sdhci,auto-cmd12;
|
||||
interrupts = <41 0x2 0 0>;
|
||||
};
|
||||
|
||||
|
|
|
@ -33,6 +33,9 @@
|
|||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "e500v2_power_isa.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "fsl,BSC9131";
|
||||
#address-cells = <2>;
|
||||
|
|
268
arch/powerpc/boot/dts/t4240emu.dts
Normal file
268
arch/powerpc/boot/dts/t4240emu.dts
Normal file
|
@ -0,0 +1,268 @@
|
|||
/*
|
||||
* T4240 emulator Device Tree Source
|
||||
*
|
||||
* Copyright 2013 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "fsl/e6500_power_isa.dtsi"
|
||||
/ {
|
||||
compatible = "fsl,T4240";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
aliases {
|
||||
ccsr = &soc;
|
||||
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
serial2 = &serial2;
|
||||
serial3 = &serial3;
|
||||
dma0 = &dma0;
|
||||
dma1 = &dma1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: PowerPC,e6500@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0 1>;
|
||||
next-level-cache = <&L2_1>;
|
||||
};
|
||||
cpu1: PowerPC,e6500@2 {
|
||||
device_type = "cpu";
|
||||
reg = <2 3>;
|
||||
next-level-cache = <&L2_1>;
|
||||
};
|
||||
cpu2: PowerPC,e6500@4 {
|
||||
device_type = "cpu";
|
||||
reg = <4 5>;
|
||||
next-level-cache = <&L2_1>;
|
||||
};
|
||||
cpu3: PowerPC,e6500@6 {
|
||||
device_type = "cpu";
|
||||
reg = <6 7>;
|
||||
next-level-cache = <&L2_1>;
|
||||
};
|
||||
|
||||
cpu4: PowerPC,e6500@8 {
|
||||
device_type = "cpu";
|
||||
reg = <8 9>;
|
||||
next-level-cache = <&L2_2>;
|
||||
};
|
||||
cpu5: PowerPC,e6500@10 {
|
||||
device_type = "cpu";
|
||||
reg = <10 11>;
|
||||
next-level-cache = <&L2_2>;
|
||||
};
|
||||
cpu6: PowerPC,e6500@12 {
|
||||
device_type = "cpu";
|
||||
reg = <12 13>;
|
||||
next-level-cache = <&L2_2>;
|
||||
};
|
||||
cpu7: PowerPC,e6500@14 {
|
||||
device_type = "cpu";
|
||||
reg = <14 15>;
|
||||
next-level-cache = <&L2_2>;
|
||||
};
|
||||
|
||||
cpu8: PowerPC,e6500@16 {
|
||||
device_type = "cpu";
|
||||
reg = <16 17>;
|
||||
next-level-cache = <&L2_3>;
|
||||
};
|
||||
cpu9: PowerPC,e6500@18 {
|
||||
device_type = "cpu";
|
||||
reg = <18 19>;
|
||||
next-level-cache = <&L2_3>;
|
||||
};
|
||||
cpu10: PowerPC,e6500@20 {
|
||||
device_type = "cpu";
|
||||
reg = <20 21>;
|
||||
next-level-cache = <&L2_3>;
|
||||
};
|
||||
cpu11: PowerPC,e6500@22 {
|
||||
device_type = "cpu";
|
||||
reg = <22 23>;
|
||||
next-level-cache = <&L2_3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/ {
|
||||
model = "fsl,T4240QDS";
|
||||
compatible = "fsl,T4240EMU", "fsl,T4240QDS";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
ifc: localbus@ffe124000 {
|
||||
reg = <0xf 0xfe124000 0 0x2000>;
|
||||
ranges = <0 0 0xf 0xe8000000 0x08000000
|
||||
2 0 0xf 0xff800000 0x00010000
|
||||
3 0 0xf 0xffdf0000 0x00008000>;
|
||||
|
||||
nor@0,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "cfi-flash";
|
||||
reg = <0x0 0x0 0x8000000>;
|
||||
|
||||
bank-width = <2>;
|
||||
device-width = <1>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
};
|
||||
|
||||
soc: soc@ffe000000 {
|
||||
ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
|
||||
reg = <0xf 0xfe000000 0 0x00001000>;
|
||||
|
||||
};
|
||||
};
|
||||
|
||||
&ifc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,ifc", "simple-bus";
|
||||
interrupts = <25 2 0 0>;
|
||||
};
|
||||
|
||||
&soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "simple-bus";
|
||||
|
||||
soc-sram-error {
|
||||
compatible = "fsl,soc-sram-error";
|
||||
interrupts = <16 2 1 29>;
|
||||
};
|
||||
|
||||
corenet-law@0 {
|
||||
compatible = "fsl,corenet-law";
|
||||
reg = <0x0 0x1000>;
|
||||
fsl,num-laws = <32>;
|
||||
};
|
||||
|
||||
ddr1: memory-controller@8000 {
|
||||
compatible = "fsl,qoriq-memory-controller-v4.7",
|
||||
"fsl,qoriq-memory-controller";
|
||||
reg = <0x8000 0x1000>;
|
||||
interrupts = <16 2 1 23>;
|
||||
};
|
||||
|
||||
ddr2: memory-controller@9000 {
|
||||
compatible = "fsl,qoriq-memory-controller-v4.7",
|
||||
"fsl,qoriq-memory-controller";
|
||||
reg = <0x9000 0x1000>;
|
||||
interrupts = <16 2 1 22>;
|
||||
};
|
||||
|
||||
ddr3: memory-controller@a000 {
|
||||
compatible = "fsl,qoriq-memory-controller-v4.7",
|
||||
"fsl,qoriq-memory-controller";
|
||||
reg = <0xa000 0x1000>;
|
||||
interrupts = <16 2 1 21>;
|
||||
};
|
||||
|
||||
cpc: l3-cache-controller@10000 {
|
||||
compatible = "fsl,t4240-l3-cache-controller", "cache";
|
||||
reg = <0x10000 0x1000
|
||||
0x11000 0x1000
|
||||
0x12000 0x1000>;
|
||||
interrupts = <16 2 1 27
|
||||
16 2 1 26
|
||||
16 2 1 25>;
|
||||
};
|
||||
|
||||
corenet-cf@18000 {
|
||||
compatible = "fsl,corenet-cf";
|
||||
reg = <0x18000 0x1000>;
|
||||
interrupts = <16 2 1 31>;
|
||||
fsl,ccf-num-csdids = <32>;
|
||||
fsl,ccf-num-snoopids = <32>;
|
||||
};
|
||||
|
||||
iommu@20000 {
|
||||
compatible = "fsl,pamu-v1.0", "fsl,pamu";
|
||||
reg = <0x20000 0x6000>;
|
||||
interrupts = <
|
||||
24 2 0 0
|
||||
16 2 1 30>;
|
||||
};
|
||||
|
||||
/include/ "fsl/qoriq-mpic.dtsi"
|
||||
|
||||
guts: global-utilities@e0000 {
|
||||
compatible = "fsl,t4240-device-config", "fsl,qoriq-device-config-2.0";
|
||||
reg = <0xe0000 0xe00>;
|
||||
fsl,has-rstcr;
|
||||
fsl,liodn-bits = <12>;
|
||||
};
|
||||
|
||||
clockgen: global-utilities@e1000 {
|
||||
compatible = "fsl,t4240-clockgen", "fsl,qoriq-clockgen-2.0";
|
||||
reg = <0xe1000 0x1000>;
|
||||
};
|
||||
|
||||
/include/ "fsl/qoriq-dma-0.dtsi"
|
||||
/include/ "fsl/qoriq-dma-1.dtsi"
|
||||
|
||||
/include/ "fsl/qoriq-i2c-0.dtsi"
|
||||
/include/ "fsl/qoriq-i2c-1.dtsi"
|
||||
/include/ "fsl/qoriq-duart-0.dtsi"
|
||||
/include/ "fsl/qoriq-duart-1.dtsi"
|
||||
|
||||
L2_1: l2-cache-controller@c20000 {
|
||||
compatible = "fsl,t4240-l2-cache-controller";
|
||||
reg = <0xc20000 0x40000>;
|
||||
next-level-cache = <&cpc>;
|
||||
};
|
||||
L2_2: l2-cache-controller@c60000 {
|
||||
compatible = "fsl,t4240-l2-cache-controller";
|
||||
reg = <0xc60000 0x40000>;
|
||||
next-level-cache = <&cpc>;
|
||||
};
|
||||
L2_3: l2-cache-controller@ca0000 {
|
||||
compatible = "fsl,t4240-l2-cache-controller";
|
||||
reg = <0xca0000 0x40000>;
|
||||
next-level-cache = <&cpc>;
|
||||
};
|
||||
};
|
|
@ -118,36 +118,53 @@ flash@0 {
|
|||
};
|
||||
|
||||
i2c@118000 {
|
||||
eeprom@51 {
|
||||
compatible = "at24,24c256";
|
||||
reg = <0x51>;
|
||||
};
|
||||
eeprom@52 {
|
||||
compatible = "at24,24c256";
|
||||
reg = <0x52>;
|
||||
};
|
||||
eeprom@53 {
|
||||
compatible = "at24,24c256";
|
||||
reg = <0x53>;
|
||||
};
|
||||
eeprom@54 {
|
||||
compatible = "at24,24c256";
|
||||
reg = <0x54>;
|
||||
};
|
||||
eeprom@55 {
|
||||
compatible = "at24,24c256";
|
||||
reg = <0x55>;
|
||||
};
|
||||
eeprom@56 {
|
||||
compatible = "at24,24c256";
|
||||
reg = <0x56>;
|
||||
};
|
||||
rtc@68 {
|
||||
compatible = "dallas,ds3232";
|
||||
reg = <0x68>;
|
||||
interrupts = <0x1 0x1 0 0>;
|
||||
mux@77 {
|
||||
compatible = "nxp,pca9547";
|
||||
reg = <0x77>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
i2c@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
|
||||
eeprom@51 {
|
||||
compatible = "at24,24c256";
|
||||
reg = <0x51>;
|
||||
};
|
||||
eeprom@52 {
|
||||
compatible = "at24,24c256";
|
||||
reg = <0x52>;
|
||||
};
|
||||
eeprom@53 {
|
||||
compatible = "at24,24c256";
|
||||
reg = <0x53>;
|
||||
};
|
||||
eeprom@54 {
|
||||
compatible = "at24,24c256";
|
||||
reg = <0x54>;
|
||||
};
|
||||
eeprom@55 {
|
||||
compatible = "at24,24c256";
|
||||
reg = <0x55>;
|
||||
};
|
||||
eeprom@56 {
|
||||
compatible = "at24,24c256";
|
||||
reg = <0x56>;
|
||||
};
|
||||
rtc@68 {
|
||||
compatible = "dallas,ds3232";
|
||||
reg = <0x68>;
|
||||
interrupts = <0x1 0x1 0 0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
sdhc@114000 {
|
||||
voltage-ranges = <1800 1800 3300 3300>;
|
||||
};
|
||||
};
|
||||
|
||||
pci0: pcie@ffe240000 {
|
||||
|
|
|
@ -23,11 +23,7 @@ CONFIG_MODVERSIONS=y
|
|||
# CONFIG_BLK_DEV_BSG is not set
|
||||
CONFIG_PARTITION_ADVANCED=y
|
||||
CONFIG_MAC_PARTITION=y
|
||||
CONFIG_P2041_RDB=y
|
||||
CONFIG_P3041_DS=y
|
||||
CONFIG_P4080_DS=y
|
||||
CONFIG_P5020_DS=y
|
||||
CONFIG_P5040_DS=y
|
||||
CONFIG_CORENET_GENERIC=y
|
||||
CONFIG_HIGHMEM=y
|
||||
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
|
||||
CONFIG_BINFMT_MISC=m
|
||||
|
@ -104,6 +100,7 @@ CONFIG_FSL_PQ_MDIO=y
|
|||
CONFIG_E1000=y
|
||||
CONFIG_E1000E=y
|
||||
CONFIG_VITESSE_PHY=y
|
||||
CONFIG_AT803X_PHY=y
|
||||
CONFIG_FIXED_PHY=y
|
||||
# CONFIG_INPUT_MOUSEDEV is not set
|
||||
# CONFIG_INPUT_KEYBOARD is not set
|
||||
|
|
|
@ -21,10 +21,7 @@ CONFIG_MODVERSIONS=y
|
|||
# CONFIG_BLK_DEV_BSG is not set
|
||||
CONFIG_PARTITION_ADVANCED=y
|
||||
CONFIG_MAC_PARTITION=y
|
||||
CONFIG_B4_QDS=y
|
||||
CONFIG_P5020_DS=y
|
||||
CONFIG_P5040_DS=y
|
||||
CONFIG_T4240_QDS=y
|
||||
CONFIG_CORENET_GENERIC=y
|
||||
# CONFIG_PPC_OF_BOOT_TRAMPOLINE is not set
|
||||
CONFIG_BINFMT_MISC=m
|
||||
CONFIG_MATH_EMULATION=y
|
||||
|
|
|
@ -138,6 +138,7 @@ CONFIG_MARVELL_PHY=y
|
|||
CONFIG_DAVICOM_PHY=y
|
||||
CONFIG_CICADA_PHY=y
|
||||
CONFIG_VITESSE_PHY=y
|
||||
CONFIG_AT803X_PHY=y
|
||||
CONFIG_FIXED_PHY=y
|
||||
CONFIG_INPUT_FF_MEMLESS=m
|
||||
# CONFIG_INPUT_MOUSEDEV is not set
|
||||
|
|
|
@ -138,6 +138,7 @@ CONFIG_MARVELL_PHY=y
|
|||
CONFIG_DAVICOM_PHY=y
|
||||
CONFIG_CICADA_PHY=y
|
||||
CONFIG_VITESSE_PHY=y
|
||||
CONFIG_AT803X_PHY=y
|
||||
CONFIG_FIXED_PHY=y
|
||||
CONFIG_INPUT_FF_MEMLESS=m
|
||||
# CONFIG_INPUT_MOUSEDEV is not set
|
||||
|
|
|
@ -23,7 +23,7 @@ CONFIG_MODULE_SRCVERSION_ALL=y
|
|||
CONFIG_PARTITION_ADVANCED=y
|
||||
CONFIG_MAC_PARTITION=y
|
||||
CONFIG_EFI_PARTITION=y
|
||||
CONFIG_P5020_DS=y
|
||||
CONFIG_CORENET_GENERIC=y
|
||||
CONFIG_CPU_FREQ=y
|
||||
CONFIG_CPU_FREQ_GOV_POWERSAVE=y
|
||||
CONFIG_CPU_FREQ_GOV_USERSPACE=y
|
||||
|
|
|
@ -71,7 +71,7 @@ CONFIG_QUICC_ENGINE=y
|
|||
CONFIG_QE_GPIO=y
|
||||
CONFIG_PPC_BESTCOMM=y
|
||||
CONFIG_GPIO_MPC8XXX=y
|
||||
CONFIG_MCU_MPC8349EMITX=m
|
||||
CONFIG_MCU_MPC8349EMITX=y
|
||||
CONFIG_HIGHMEM=y
|
||||
CONFIG_NO_HZ=y
|
||||
CONFIG_HIGH_RES_TIMERS=y
|
||||
|
|
|
@ -43,6 +43,7 @@ extern struct ppc_emulated {
|
|||
struct ppc_emulated_entry popcntb;
|
||||
struct ppc_emulated_entry spe;
|
||||
struct ppc_emulated_entry string;
|
||||
struct ppc_emulated_entry sync;
|
||||
struct ppc_emulated_entry unaligned;
|
||||
#ifdef CONFIG_MATH_EMULATION
|
||||
struct ppc_emulated_entry math;
|
||||
|
|
|
@ -143,6 +143,8 @@
|
|||
#define PPC_INST_LSWX 0x7c00042a
|
||||
#define PPC_INST_LWARX 0x7c000028
|
||||
#define PPC_INST_LWSYNC 0x7c2004ac
|
||||
#define PPC_INST_SYNC 0x7c0004ac
|
||||
#define PPC_INST_SYNC_MASK 0xfc0007fe
|
||||
#define PPC_INST_LXVD2X 0x7c000698
|
||||
#define PPC_INST_MCRXR 0x7c000400
|
||||
#define PPC_INST_MCRXR_MASK 0xfc0007fe
|
||||
|
|
|
@ -167,21 +167,7 @@ struct thread_vr_state {
|
|||
vector128 vscr __attribute__((aligned(16)));
|
||||
};
|
||||
|
||||
struct thread_struct {
|
||||
unsigned long ksp; /* Kernel stack pointer */
|
||||
#ifdef CONFIG_PPC64
|
||||
unsigned long ksp_vsid;
|
||||
#endif
|
||||
struct pt_regs *regs; /* Pointer to saved register state */
|
||||
mm_segment_t fs; /* for get_fs() validation */
|
||||
#ifdef CONFIG_BOOKE
|
||||
/* BookE base exception scratch space; align on cacheline */
|
||||
unsigned long normsave[8] ____cacheline_aligned;
|
||||
#endif
|
||||
#ifdef CONFIG_PPC32
|
||||
void *pgdir; /* root of page-table tree */
|
||||
unsigned long ksp_limit; /* if ksp <= ksp_limit stack overflow */
|
||||
#endif
|
||||
struct debug_reg {
|
||||
#ifdef CONFIG_PPC_ADV_DEBUG_REGS
|
||||
/*
|
||||
* The following help to manage the use of Debug Control Registers
|
||||
|
@ -218,6 +204,24 @@ struct thread_struct {
|
|||
unsigned long dvc2;
|
||||
#endif
|
||||
#endif
|
||||
};
|
||||
|
||||
struct thread_struct {
|
||||
unsigned long ksp; /* Kernel stack pointer */
|
||||
#ifdef CONFIG_PPC64
|
||||
unsigned long ksp_vsid;
|
||||
#endif
|
||||
struct pt_regs *regs; /* Pointer to saved register state */
|
||||
mm_segment_t fs; /* for get_fs() validation */
|
||||
#ifdef CONFIG_BOOKE
|
||||
/* BookE base exception scratch space; align on cacheline */
|
||||
unsigned long normsave[8] ____cacheline_aligned;
|
||||
#endif
|
||||
#ifdef CONFIG_PPC32
|
||||
void *pgdir; /* root of page-table tree */
|
||||
unsigned long ksp_limit; /* if ksp <= ksp_limit stack overflow */
|
||||
#endif
|
||||
struct debug_reg debug;
|
||||
struct thread_fp_state fp_state;
|
||||
struct thread_fp_state *fp_save_area;
|
||||
int fpexc_mode; /* floating-point exception mode */
|
||||
|
|
|
@ -381,7 +381,7 @@
|
|||
#define DBCR0_IA34T 0x00004000 /* Instr Addr 3-4 range Toggle */
|
||||
#define DBCR0_FT 0x00000001 /* Freeze Timers on debug event */
|
||||
|
||||
#define dbcr_iac_range(task) ((task)->thread.dbcr0)
|
||||
#define dbcr_iac_range(task) ((task)->thread.debug.dbcr0)
|
||||
#define DBCR_IAC12I DBCR0_IA12 /* Range Inclusive */
|
||||
#define DBCR_IAC12X (DBCR0_IA12 | DBCR0_IA12X) /* Range Exclusive */
|
||||
#define DBCR_IAC12MODE (DBCR0_IA12 | DBCR0_IA12X) /* IAC 1-2 Mode Bits */
|
||||
|
@ -395,7 +395,7 @@
|
|||
#define DBCR1_DAC1W 0x20000000 /* DAC1 Write Debug Event */
|
||||
#define DBCR1_DAC2W 0x10000000 /* DAC2 Write Debug Event */
|
||||
|
||||
#define dbcr_dac(task) ((task)->thread.dbcr1)
|
||||
#define dbcr_dac(task) ((task)->thread.debug.dbcr1)
|
||||
#define DBCR_DAC1R DBCR1_DAC1R
|
||||
#define DBCR_DAC1W DBCR1_DAC1W
|
||||
#define DBCR_DAC2R DBCR1_DAC2R
|
||||
|
@ -441,7 +441,7 @@
|
|||
#define DBCR0_CRET 0x00000020 /* Critical Return Debug Event */
|
||||
#define DBCR0_FT 0x00000001 /* Freeze Timers on debug event */
|
||||
|
||||
#define dbcr_dac(task) ((task)->thread.dbcr0)
|
||||
#define dbcr_dac(task) ((task)->thread.debug.dbcr0)
|
||||
#define DBCR_DAC1R DBCR0_DAC1R
|
||||
#define DBCR_DAC1W DBCR0_DAC1W
|
||||
#define DBCR_DAC2R DBCR0_DAC2R
|
||||
|
@ -475,7 +475,7 @@
|
|||
#define DBCR1_IAC34MX 0x000000C0 /* Instr Addr 3-4 range eXclusive */
|
||||
#define DBCR1_IAC34AT 0x00000001 /* Instr Addr 3-4 range Toggle */
|
||||
|
||||
#define dbcr_iac_range(task) ((task)->thread.dbcr1)
|
||||
#define dbcr_iac_range(task) ((task)->thread.debug.dbcr1)
|
||||
#define DBCR_IAC12I DBCR1_IAC12M /* Range Inclusive */
|
||||
#define DBCR_IAC12X DBCR1_IAC12MX /* Range Exclusive */
|
||||
#define DBCR_IAC12MODE DBCR1_IAC12MX /* IAC 1-2 Mode Bits */
|
||||
|
|
|
@ -35,6 +35,7 @@ extern void giveup_vsx(struct task_struct *);
|
|||
extern void enable_kernel_spe(void);
|
||||
extern void giveup_spe(struct task_struct *);
|
||||
extern void load_up_spe(struct task_struct *);
|
||||
extern void switch_booke_debug_regs(struct thread_struct *new_thread);
|
||||
|
||||
#ifndef CONFIG_SMP
|
||||
extern void discard_lazy_cpu_state(void);
|
||||
|
|
|
@ -115,7 +115,7 @@ int main(void)
|
|||
#endif /* CONFIG_SPE */
|
||||
#endif /* CONFIG_PPC64 */
|
||||
#if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
|
||||
DEFINE(THREAD_DBCR0, offsetof(struct thread_struct, dbcr0));
|
||||
DEFINE(THREAD_DBCR0, offsetof(struct thread_struct, debug.dbcr0));
|
||||
#endif
|
||||
#ifdef CONFIG_KVM_BOOK3S_32_HANDLER
|
||||
DEFINE(THREAD_KVM_SVCPU, offsetof(struct thread_struct, kvm_shadow_vcpu));
|
||||
|
|
|
@ -399,7 +399,7 @@ interrupt_end_book3e:
|
|||
|
||||
/* Altivec Unavailable Interrupt */
|
||||
START_EXCEPTION(altivec_unavailable);
|
||||
NORMAL_EXCEPTION_PROLOG(0x200, BOOKE_INTERRUPT_ALTIVEC_UNAVAIL,
|
||||
NORMAL_EXCEPTION_PROLOG(0x200, BOOKE_INTERRUPT_SPE_ALTIVEC_UNAVAIL,
|
||||
PROLOG_ADDITION_NONE)
|
||||
/* we can probably do a shorter exception entry for that one... */
|
||||
EXCEPTION_COMMON(0x200, PACA_EXGEN, INTS_KEEP)
|
||||
|
@ -421,7 +421,8 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
|
|||
|
||||
/* AltiVec Assist */
|
||||
START_EXCEPTION(altivec_assist);
|
||||
NORMAL_EXCEPTION_PROLOG(0x220, BOOKE_INTERRUPT_ALTIVEC_ASSIST,
|
||||
NORMAL_EXCEPTION_PROLOG(0x220,
|
||||
BOOKE_INTERRUPT_SPE_FP_DATA_ALTIVEC_ASSIST,
|
||||
PROLOG_ADDITION_NONE)
|
||||
EXCEPTION_COMMON(0x220, PACA_EXGEN, INTS_DISABLE)
|
||||
bl .save_nvgprs
|
||||
|
|
|
@ -858,6 +858,9 @@ initial_mmu:
|
|||
addis r11, r11, 0x0080 /* Add 8M */
|
||||
mtspr SPRN_MD_RPN, r11
|
||||
|
||||
addi r10, r10, 0x0100
|
||||
mtspr SPRN_MD_CTR, r10
|
||||
|
||||
addis r8, r8, 0x0080 /* Add 8M */
|
||||
mtspr SPRN_MD_EPN, r8
|
||||
mtspr SPRN_MD_TWC, r9
|
||||
|
|
|
@ -555,27 +555,27 @@ END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
|
|||
#ifdef CONFIG_SPE
|
||||
/* SPE Unavailable */
|
||||
START_EXCEPTION(SPEUnavailable)
|
||||
NORMAL_EXCEPTION_PROLOG(SPE_UNAVAIL)
|
||||
NORMAL_EXCEPTION_PROLOG(SPE_ALTIVEC_UNAVAIL)
|
||||
beq 1f
|
||||
bl load_up_spe
|
||||
b fast_exception_return
|
||||
1: addi r3,r1,STACK_FRAME_OVERHEAD
|
||||
EXC_XFER_EE_LITE(0x2010, KernelSPE)
|
||||
#else
|
||||
EXCEPTION(0x2020, SPE_UNAVAIL, SPEUnavailable, \
|
||||
EXCEPTION(0x2020, SPE_ALTIVEC_UNAVAIL, SPEUnavailable, \
|
||||
unknown_exception, EXC_XFER_EE)
|
||||
#endif /* CONFIG_SPE */
|
||||
|
||||
/* SPE Floating Point Data */
|
||||
#ifdef CONFIG_SPE
|
||||
EXCEPTION(0x2030, SPE_FP_DATA, SPEFloatingPointData, \
|
||||
SPEFloatingPointException, EXC_XFER_EE);
|
||||
EXCEPTION(0x2030, SPE_FP_DATA_ALTIVEC_ASSIST, SPEFloatingPointData,
|
||||
SPEFloatingPointException, EXC_XFER_EE)
|
||||
|
||||
/* SPE Floating Point Round */
|
||||
EXCEPTION(0x2050, SPE_FP_ROUND, SPEFloatingPointRound, \
|
||||
SPEFloatingPointRoundException, EXC_XFER_EE)
|
||||
#else
|
||||
EXCEPTION(0x2040, SPE_FP_DATA, SPEFloatingPointData, \
|
||||
EXCEPTION(0x2040, SPE_FP_DATA_ALTIVEC_ASSIST, SPEFloatingPointData,
|
||||
unknown_exception, EXC_XFER_EE)
|
||||
EXCEPTION(0x2050, SPE_FP_ROUND, SPEFloatingPointRound, \
|
||||
unknown_exception, EXC_XFER_EE)
|
||||
|
|
|
@ -151,15 +151,16 @@ static int kgdb_handle_breakpoint(struct pt_regs *regs)
|
|||
return 1;
|
||||
}
|
||||
|
||||
static DEFINE_PER_CPU(struct thread_info, kgdb_thread_info);
|
||||
static int kgdb_singlestep(struct pt_regs *regs)
|
||||
{
|
||||
struct thread_info *thread_info, *exception_thread_info;
|
||||
struct thread_info *backup_current_thread_info;
|
||||
struct thread_info *backup_current_thread_info =
|
||||
&__get_cpu_var(kgdb_thread_info);
|
||||
|
||||
if (user_mode(regs))
|
||||
return 0;
|
||||
|
||||
backup_current_thread_info = kmalloc(sizeof(struct thread_info), GFP_KERNEL);
|
||||
/*
|
||||
* On Book E and perhaps other processors, singlestep is handled on
|
||||
* the critical exception stack. This causes current_thread_info()
|
||||
|
@ -185,7 +186,6 @@ static int kgdb_singlestep(struct pt_regs *regs)
|
|||
/* Restore current_thread_info lastly. */
|
||||
memcpy(exception_thread_info, backup_current_thread_info, sizeof *thread_info);
|
||||
|
||||
kfree(backup_current_thread_info);
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
|
|
@ -314,28 +314,28 @@ static DEFINE_PER_CPU(struct arch_hw_breakpoint, current_brk);
|
|||
*/
|
||||
static void set_debug_reg_defaults(struct thread_struct *thread)
|
||||
{
|
||||
thread->iac1 = thread->iac2 = 0;
|
||||
thread->debug.iac1 = thread->debug.iac2 = 0;
|
||||
#if CONFIG_PPC_ADV_DEBUG_IACS > 2
|
||||
thread->iac3 = thread->iac4 = 0;
|
||||
thread->debug.iac3 = thread->debug.iac4 = 0;
|
||||
#endif
|
||||
thread->dac1 = thread->dac2 = 0;
|
||||
thread->debug.dac1 = thread->debug.dac2 = 0;
|
||||
#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
|
||||
thread->dvc1 = thread->dvc2 = 0;
|
||||
thread->debug.dvc1 = thread->debug.dvc2 = 0;
|
||||
#endif
|
||||
thread->dbcr0 = 0;
|
||||
thread->debug.dbcr0 = 0;
|
||||
#ifdef CONFIG_BOOKE
|
||||
/*
|
||||
* Force User/Supervisor bits to b11 (user-only MSR[PR]=1)
|
||||
*/
|
||||
thread->dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US | \
|
||||
thread->debug.dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US |
|
||||
DBCR1_IAC3US | DBCR1_IAC4US;
|
||||
/*
|
||||
* Force Data Address Compare User/Supervisor bits to be User-only
|
||||
* (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0.
|
||||
*/
|
||||
thread->dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US;
|
||||
thread->debug.dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US;
|
||||
#else
|
||||
thread->dbcr1 = 0;
|
||||
thread->debug.dbcr1 = 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
|
@ -348,22 +348,22 @@ static void prime_debug_regs(struct thread_struct *thread)
|
|||
*/
|
||||
mtmsr(mfmsr() & ~MSR_DE);
|
||||
|
||||
mtspr(SPRN_IAC1, thread->iac1);
|
||||
mtspr(SPRN_IAC2, thread->iac2);
|
||||
mtspr(SPRN_IAC1, thread->debug.iac1);
|
||||
mtspr(SPRN_IAC2, thread->debug.iac2);
|
||||
#if CONFIG_PPC_ADV_DEBUG_IACS > 2
|
||||
mtspr(SPRN_IAC3, thread->iac3);
|
||||
mtspr(SPRN_IAC4, thread->iac4);
|
||||
mtspr(SPRN_IAC3, thread->debug.iac3);
|
||||
mtspr(SPRN_IAC4, thread->debug.iac4);
|
||||
#endif
|
||||
mtspr(SPRN_DAC1, thread->dac1);
|
||||
mtspr(SPRN_DAC2, thread->dac2);
|
||||
mtspr(SPRN_DAC1, thread->debug.dac1);
|
||||
mtspr(SPRN_DAC2, thread->debug.dac2);
|
||||
#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
|
||||
mtspr(SPRN_DVC1, thread->dvc1);
|
||||
mtspr(SPRN_DVC2, thread->dvc2);
|
||||
mtspr(SPRN_DVC1, thread->debug.dvc1);
|
||||
mtspr(SPRN_DVC2, thread->debug.dvc2);
|
||||
#endif
|
||||
mtspr(SPRN_DBCR0, thread->dbcr0);
|
||||
mtspr(SPRN_DBCR1, thread->dbcr1);
|
||||
mtspr(SPRN_DBCR0, thread->debug.dbcr0);
|
||||
mtspr(SPRN_DBCR1, thread->debug.dbcr1);
|
||||
#ifdef CONFIG_BOOKE
|
||||
mtspr(SPRN_DBCR2, thread->dbcr2);
|
||||
mtspr(SPRN_DBCR2, thread->debug.dbcr2);
|
||||
#endif
|
||||
}
|
||||
/*
|
||||
|
@ -371,12 +371,13 @@ static void prime_debug_regs(struct thread_struct *thread)
|
|||
* debug registers, set the debug registers from the values
|
||||
* stored in the new thread.
|
||||
*/
|
||||
static void switch_booke_debug_regs(struct thread_struct *new_thread)
|
||||
void switch_booke_debug_regs(struct thread_struct *new_thread)
|
||||
{
|
||||
if ((current->thread.dbcr0 & DBCR0_IDM)
|
||||
|| (new_thread->dbcr0 & DBCR0_IDM))
|
||||
if ((current->thread.debug.dbcr0 & DBCR0_IDM)
|
||||
|| (new_thread->debug.dbcr0 & DBCR0_IDM))
|
||||
prime_debug_regs(new_thread);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(switch_booke_debug_regs);
|
||||
#else /* !CONFIG_PPC_ADV_DEBUG_REGS */
|
||||
#ifndef CONFIG_HAVE_HW_BREAKPOINT
|
||||
static void set_debug_reg_defaults(struct thread_struct *thread)
|
||||
|
|
|
@ -658,7 +658,7 @@ static const struct user_regset native_regsets[] = {
|
|||
#endif
|
||||
#ifdef CONFIG_SPE
|
||||
[REGSET_SPE] = {
|
||||
.n = 35,
|
||||
.core_note_type = NT_PPC_SPE, .n = 35,
|
||||
.size = sizeof(u32), .align = sizeof(u32),
|
||||
.active = evr_active, .get = evr_get, .set = evr_set
|
||||
},
|
||||
|
@ -855,8 +855,8 @@ void user_enable_single_step(struct task_struct *task)
|
|||
|
||||
if (regs != NULL) {
|
||||
#ifdef CONFIG_PPC_ADV_DEBUG_REGS
|
||||
task->thread.dbcr0 &= ~DBCR0_BT;
|
||||
task->thread.dbcr0 |= DBCR0_IDM | DBCR0_IC;
|
||||
task->thread.debug.dbcr0 &= ~DBCR0_BT;
|
||||
task->thread.debug.dbcr0 |= DBCR0_IDM | DBCR0_IC;
|
||||
regs->msr |= MSR_DE;
|
||||
#else
|
||||
regs->msr &= ~MSR_BE;
|
||||
|
@ -872,8 +872,8 @@ void user_enable_block_step(struct task_struct *task)
|
|||
|
||||
if (regs != NULL) {
|
||||
#ifdef CONFIG_PPC_ADV_DEBUG_REGS
|
||||
task->thread.dbcr0 &= ~DBCR0_IC;
|
||||
task->thread.dbcr0 = DBCR0_IDM | DBCR0_BT;
|
||||
task->thread.debug.dbcr0 &= ~DBCR0_IC;
|
||||
task->thread.debug.dbcr0 = DBCR0_IDM | DBCR0_BT;
|
||||
regs->msr |= MSR_DE;
|
||||
#else
|
||||
regs->msr &= ~MSR_SE;
|
||||
|
@ -895,16 +895,16 @@ void user_disable_single_step(struct task_struct *task)
|
|||
* And, after doing so, if all debug flags are off, turn
|
||||
* off DBCR0(IDM) and MSR(DE) .... Torez
|
||||
*/
|
||||
task->thread.dbcr0 &= ~DBCR0_IC;
|
||||
task->thread.debug.dbcr0 &= ~(DBCR0_IC|DBCR0_BT);
|
||||
/*
|
||||
* Test to see if any of the DBCR_ACTIVE_EVENTS bits are set.
|
||||
*/
|
||||
if (!DBCR_ACTIVE_EVENTS(task->thread.dbcr0,
|
||||
task->thread.dbcr1)) {
|
||||
if (!DBCR_ACTIVE_EVENTS(task->thread.debug.dbcr0,
|
||||
task->thread.debug.dbcr1)) {
|
||||
/*
|
||||
* All debug events were off.....
|
||||
*/
|
||||
task->thread.dbcr0 &= ~DBCR0_IDM;
|
||||
task->thread.debug.dbcr0 &= ~DBCR0_IDM;
|
||||
regs->msr &= ~MSR_DE;
|
||||
}
|
||||
#else
|
||||
|
@ -1023,14 +1023,14 @@ int ptrace_set_debugreg(struct task_struct *task, unsigned long addr,
|
|||
*/
|
||||
|
||||
/* DAC's hold the whole address without any mode flags */
|
||||
task->thread.dac1 = data & ~0x3UL;
|
||||
task->thread.debug.dac1 = data & ~0x3UL;
|
||||
|
||||
if (task->thread.dac1 == 0) {
|
||||
if (task->thread.debug.dac1 == 0) {
|
||||
dbcr_dac(task) &= ~(DBCR_DAC1R | DBCR_DAC1W);
|
||||
if (!DBCR_ACTIVE_EVENTS(task->thread.dbcr0,
|
||||
task->thread.dbcr1)) {
|
||||
if (!DBCR_ACTIVE_EVENTS(task->thread.debug.dbcr0,
|
||||
task->thread.debug.dbcr1)) {
|
||||
task->thread.regs->msr &= ~MSR_DE;
|
||||
task->thread.dbcr0 &= ~DBCR0_IDM;
|
||||
task->thread.debug.dbcr0 &= ~DBCR0_IDM;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
@ -1042,7 +1042,7 @@ int ptrace_set_debugreg(struct task_struct *task, unsigned long addr,
|
|||
|
||||
/* Set the Internal Debugging flag (IDM bit 1) for the DBCR0
|
||||
register */
|
||||
task->thread.dbcr0 |= DBCR0_IDM;
|
||||
task->thread.debug.dbcr0 |= DBCR0_IDM;
|
||||
|
||||
/* Check for write and read flags and set DBCR0
|
||||
accordingly */
|
||||
|
@ -1072,10 +1072,10 @@ static long set_instruction_bp(struct task_struct *child,
|
|||
struct ppc_hw_breakpoint *bp_info)
|
||||
{
|
||||
int slot;
|
||||
int slot1_in_use = ((child->thread.dbcr0 & DBCR0_IAC1) != 0);
|
||||
int slot2_in_use = ((child->thread.dbcr0 & DBCR0_IAC2) != 0);
|
||||
int slot3_in_use = ((child->thread.dbcr0 & DBCR0_IAC3) != 0);
|
||||
int slot4_in_use = ((child->thread.dbcr0 & DBCR0_IAC4) != 0);
|
||||
int slot1_in_use = ((child->thread.debug.dbcr0 & DBCR0_IAC1) != 0);
|
||||
int slot2_in_use = ((child->thread.debug.dbcr0 & DBCR0_IAC2) != 0);
|
||||
int slot3_in_use = ((child->thread.debug.dbcr0 & DBCR0_IAC3) != 0);
|
||||
int slot4_in_use = ((child->thread.debug.dbcr0 & DBCR0_IAC4) != 0);
|
||||
|
||||
if (dbcr_iac_range(child) & DBCR_IAC12MODE)
|
||||
slot2_in_use = 1;
|
||||
|
@ -1094,9 +1094,9 @@ static long set_instruction_bp(struct task_struct *child,
|
|||
/* We need a pair of IAC regsisters */
|
||||
if ((!slot1_in_use) && (!slot2_in_use)) {
|
||||
slot = 1;
|
||||
child->thread.iac1 = bp_info->addr;
|
||||
child->thread.iac2 = bp_info->addr2;
|
||||
child->thread.dbcr0 |= DBCR0_IAC1;
|
||||
child->thread.debug.iac1 = bp_info->addr;
|
||||
child->thread.debug.iac2 = bp_info->addr2;
|
||||
child->thread.debug.dbcr0 |= DBCR0_IAC1;
|
||||
if (bp_info->addr_mode ==
|
||||
PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE)
|
||||
dbcr_iac_range(child) |= DBCR_IAC12X;
|
||||
|
@ -1105,9 +1105,9 @@ static long set_instruction_bp(struct task_struct *child,
|
|||
#if CONFIG_PPC_ADV_DEBUG_IACS > 2
|
||||
} else if ((!slot3_in_use) && (!slot4_in_use)) {
|
||||
slot = 3;
|
||||
child->thread.iac3 = bp_info->addr;
|
||||
child->thread.iac4 = bp_info->addr2;
|
||||
child->thread.dbcr0 |= DBCR0_IAC3;
|
||||
child->thread.debug.iac3 = bp_info->addr;
|
||||
child->thread.debug.iac4 = bp_info->addr2;
|
||||
child->thread.debug.dbcr0 |= DBCR0_IAC3;
|
||||
if (bp_info->addr_mode ==
|
||||
PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE)
|
||||
dbcr_iac_range(child) |= DBCR_IAC34X;
|
||||
|
@ -1127,30 +1127,30 @@ static long set_instruction_bp(struct task_struct *child,
|
|||
*/
|
||||
if (slot2_in_use || (slot3_in_use == slot4_in_use)) {
|
||||
slot = 1;
|
||||
child->thread.iac1 = bp_info->addr;
|
||||
child->thread.dbcr0 |= DBCR0_IAC1;
|
||||
child->thread.debug.iac1 = bp_info->addr;
|
||||
child->thread.debug.dbcr0 |= DBCR0_IAC1;
|
||||
goto out;
|
||||
}
|
||||
}
|
||||
if (!slot2_in_use) {
|
||||
slot = 2;
|
||||
child->thread.iac2 = bp_info->addr;
|
||||
child->thread.dbcr0 |= DBCR0_IAC2;
|
||||
child->thread.debug.iac2 = bp_info->addr;
|
||||
child->thread.debug.dbcr0 |= DBCR0_IAC2;
|
||||
#if CONFIG_PPC_ADV_DEBUG_IACS > 2
|
||||
} else if (!slot3_in_use) {
|
||||
slot = 3;
|
||||
child->thread.iac3 = bp_info->addr;
|
||||
child->thread.dbcr0 |= DBCR0_IAC3;
|
||||
child->thread.debug.iac3 = bp_info->addr;
|
||||
child->thread.debug.dbcr0 |= DBCR0_IAC3;
|
||||
} else if (!slot4_in_use) {
|
||||
slot = 4;
|
||||
child->thread.iac4 = bp_info->addr;
|
||||
child->thread.dbcr0 |= DBCR0_IAC4;
|
||||
child->thread.debug.iac4 = bp_info->addr;
|
||||
child->thread.debug.dbcr0 |= DBCR0_IAC4;
|
||||
#endif
|
||||
} else
|
||||
return -ENOSPC;
|
||||
}
|
||||
out:
|
||||
child->thread.dbcr0 |= DBCR0_IDM;
|
||||
child->thread.debug.dbcr0 |= DBCR0_IDM;
|
||||
child->thread.regs->msr |= MSR_DE;
|
||||
|
||||
return slot;
|
||||
|
@ -1160,49 +1160,49 @@ static int del_instruction_bp(struct task_struct *child, int slot)
|
|||
{
|
||||
switch (slot) {
|
||||
case 1:
|
||||
if ((child->thread.dbcr0 & DBCR0_IAC1) == 0)
|
||||
if ((child->thread.debug.dbcr0 & DBCR0_IAC1) == 0)
|
||||
return -ENOENT;
|
||||
|
||||
if (dbcr_iac_range(child) & DBCR_IAC12MODE) {
|
||||
/* address range - clear slots 1 & 2 */
|
||||
child->thread.iac2 = 0;
|
||||
child->thread.debug.iac2 = 0;
|
||||
dbcr_iac_range(child) &= ~DBCR_IAC12MODE;
|
||||
}
|
||||
child->thread.iac1 = 0;
|
||||
child->thread.dbcr0 &= ~DBCR0_IAC1;
|
||||
child->thread.debug.iac1 = 0;
|
||||
child->thread.debug.dbcr0 &= ~DBCR0_IAC1;
|
||||
break;
|
||||
case 2:
|
||||
if ((child->thread.dbcr0 & DBCR0_IAC2) == 0)
|
||||
if ((child->thread.debug.dbcr0 & DBCR0_IAC2) == 0)
|
||||
return -ENOENT;
|
||||
|
||||
if (dbcr_iac_range(child) & DBCR_IAC12MODE)
|
||||
/* used in a range */
|
||||
return -EINVAL;
|
||||
child->thread.iac2 = 0;
|
||||
child->thread.dbcr0 &= ~DBCR0_IAC2;
|
||||
child->thread.debug.iac2 = 0;
|
||||
child->thread.debug.dbcr0 &= ~DBCR0_IAC2;
|
||||
break;
|
||||
#if CONFIG_PPC_ADV_DEBUG_IACS > 2
|
||||
case 3:
|
||||
if ((child->thread.dbcr0 & DBCR0_IAC3) == 0)
|
||||
if ((child->thread.debug.dbcr0 & DBCR0_IAC3) == 0)
|
||||
return -ENOENT;
|
||||
|
||||
if (dbcr_iac_range(child) & DBCR_IAC34MODE) {
|
||||
/* address range - clear slots 3 & 4 */
|
||||
child->thread.iac4 = 0;
|
||||
child->thread.debug.iac4 = 0;
|
||||
dbcr_iac_range(child) &= ~DBCR_IAC34MODE;
|
||||
}
|
||||
child->thread.iac3 = 0;
|
||||
child->thread.dbcr0 &= ~DBCR0_IAC3;
|
||||
child->thread.debug.iac3 = 0;
|
||||
child->thread.debug.dbcr0 &= ~DBCR0_IAC3;
|
||||
break;
|
||||
case 4:
|
||||
if ((child->thread.dbcr0 & DBCR0_IAC4) == 0)
|
||||
if ((child->thread.debug.dbcr0 & DBCR0_IAC4) == 0)
|
||||
return -ENOENT;
|
||||
|
||||
if (dbcr_iac_range(child) & DBCR_IAC34MODE)
|
||||
/* Used in a range */
|
||||
return -EINVAL;
|
||||
child->thread.iac4 = 0;
|
||||
child->thread.dbcr0 &= ~DBCR0_IAC4;
|
||||
child->thread.debug.iac4 = 0;
|
||||
child->thread.debug.dbcr0 &= ~DBCR0_IAC4;
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
|
@ -1232,18 +1232,18 @@ static int set_dac(struct task_struct *child, struct ppc_hw_breakpoint *bp_info)
|
|||
dbcr_dac(child) |= DBCR_DAC1R;
|
||||
if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE)
|
||||
dbcr_dac(child) |= DBCR_DAC1W;
|
||||
child->thread.dac1 = (unsigned long)bp_info->addr;
|
||||
child->thread.debug.dac1 = (unsigned long)bp_info->addr;
|
||||
#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
|
||||
if (byte_enable) {
|
||||
child->thread.dvc1 =
|
||||
child->thread.debug.dvc1 =
|
||||
(unsigned long)bp_info->condition_value;
|
||||
child->thread.dbcr2 |=
|
||||
child->thread.debug.dbcr2 |=
|
||||
((byte_enable << DBCR2_DVC1BE_SHIFT) |
|
||||
(condition_mode << DBCR2_DVC1M_SHIFT));
|
||||
}
|
||||
#endif
|
||||
#ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
|
||||
} else if (child->thread.dbcr2 & DBCR2_DAC12MODE) {
|
||||
} else if (child->thread.debug.dbcr2 & DBCR2_DAC12MODE) {
|
||||
/* Both dac1 and dac2 are part of a range */
|
||||
return -ENOSPC;
|
||||
#endif
|
||||
|
@ -1253,19 +1253,19 @@ static int set_dac(struct task_struct *child, struct ppc_hw_breakpoint *bp_info)
|
|||
dbcr_dac(child) |= DBCR_DAC2R;
|
||||
if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE)
|
||||
dbcr_dac(child) |= DBCR_DAC2W;
|
||||
child->thread.dac2 = (unsigned long)bp_info->addr;
|
||||
child->thread.debug.dac2 = (unsigned long)bp_info->addr;
|
||||
#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
|
||||
if (byte_enable) {
|
||||
child->thread.dvc2 =
|
||||
child->thread.debug.dvc2 =
|
||||
(unsigned long)bp_info->condition_value;
|
||||
child->thread.dbcr2 |=
|
||||
child->thread.debug.dbcr2 |=
|
||||
((byte_enable << DBCR2_DVC2BE_SHIFT) |
|
||||
(condition_mode << DBCR2_DVC2M_SHIFT));
|
||||
}
|
||||
#endif
|
||||
} else
|
||||
return -ENOSPC;
|
||||
child->thread.dbcr0 |= DBCR0_IDM;
|
||||
child->thread.debug.dbcr0 |= DBCR0_IDM;
|
||||
child->thread.regs->msr |= MSR_DE;
|
||||
|
||||
return slot + 4;
|
||||
|
@ -1277,32 +1277,32 @@ static int del_dac(struct task_struct *child, int slot)
|
|||
if ((dbcr_dac(child) & (DBCR_DAC1R | DBCR_DAC1W)) == 0)
|
||||
return -ENOENT;
|
||||
|
||||
child->thread.dac1 = 0;
|
||||
child->thread.debug.dac1 = 0;
|
||||
dbcr_dac(child) &= ~(DBCR_DAC1R | DBCR_DAC1W);
|
||||
#ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
|
||||
if (child->thread.dbcr2 & DBCR2_DAC12MODE) {
|
||||
child->thread.dac2 = 0;
|
||||
child->thread.dbcr2 &= ~DBCR2_DAC12MODE;
|
||||
if (child->thread.debug.dbcr2 & DBCR2_DAC12MODE) {
|
||||
child->thread.debug.dac2 = 0;
|
||||
child->thread.debug.dbcr2 &= ~DBCR2_DAC12MODE;
|
||||
}
|
||||
child->thread.dbcr2 &= ~(DBCR2_DVC1M | DBCR2_DVC1BE);
|
||||
child->thread.debug.dbcr2 &= ~(DBCR2_DVC1M | DBCR2_DVC1BE);
|
||||
#endif
|
||||
#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
|
||||
child->thread.dvc1 = 0;
|
||||
child->thread.debug.dvc1 = 0;
|
||||
#endif
|
||||
} else if (slot == 2) {
|
||||
if ((dbcr_dac(child) & (DBCR_DAC2R | DBCR_DAC2W)) == 0)
|
||||
return -ENOENT;
|
||||
|
||||
#ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
|
||||
if (child->thread.dbcr2 & DBCR2_DAC12MODE)
|
||||
if (child->thread.debug.dbcr2 & DBCR2_DAC12MODE)
|
||||
/* Part of a range */
|
||||
return -EINVAL;
|
||||
child->thread.dbcr2 &= ~(DBCR2_DVC2M | DBCR2_DVC2BE);
|
||||
child->thread.debug.dbcr2 &= ~(DBCR2_DVC2M | DBCR2_DVC2BE);
|
||||
#endif
|
||||
#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
|
||||
child->thread.dvc2 = 0;
|
||||
child->thread.debug.dvc2 = 0;
|
||||
#endif
|
||||
child->thread.dac2 = 0;
|
||||
child->thread.debug.dac2 = 0;
|
||||
dbcr_dac(child) &= ~(DBCR_DAC2R | DBCR_DAC2W);
|
||||
} else
|
||||
return -EINVAL;
|
||||
|
@ -1344,22 +1344,22 @@ static int set_dac_range(struct task_struct *child,
|
|||
return -EIO;
|
||||
}
|
||||
|
||||
if (child->thread.dbcr0 &
|
||||
if (child->thread.debug.dbcr0 &
|
||||
(DBCR0_DAC1R | DBCR0_DAC1W | DBCR0_DAC2R | DBCR0_DAC2W))
|
||||
return -ENOSPC;
|
||||
|
||||
if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ)
|
||||
child->thread.dbcr0 |= (DBCR0_DAC1R | DBCR0_IDM);
|
||||
child->thread.debug.dbcr0 |= (DBCR0_DAC1R | DBCR0_IDM);
|
||||
if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE)
|
||||
child->thread.dbcr0 |= (DBCR0_DAC1W | DBCR0_IDM);
|
||||
child->thread.dac1 = bp_info->addr;
|
||||
child->thread.dac2 = bp_info->addr2;
|
||||
child->thread.debug.dbcr0 |= (DBCR0_DAC1W | DBCR0_IDM);
|
||||
child->thread.debug.dac1 = bp_info->addr;
|
||||
child->thread.debug.dac2 = bp_info->addr2;
|
||||
if (mode == PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE)
|
||||
child->thread.dbcr2 |= DBCR2_DAC12M;
|
||||
child->thread.debug.dbcr2 |= DBCR2_DAC12M;
|
||||
else if (mode == PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE)
|
||||
child->thread.dbcr2 |= DBCR2_DAC12MX;
|
||||
child->thread.debug.dbcr2 |= DBCR2_DAC12MX;
|
||||
else /* PPC_BREAKPOINT_MODE_MASK */
|
||||
child->thread.dbcr2 |= DBCR2_DAC12MM;
|
||||
child->thread.debug.dbcr2 |= DBCR2_DAC12MM;
|
||||
child->thread.regs->msr |= MSR_DE;
|
||||
|
||||
return 5;
|
||||
|
@ -1490,9 +1490,9 @@ static long ppc_del_hwdebug(struct task_struct *child, long data)
|
|||
rc = del_dac(child, (int)data - 4);
|
||||
|
||||
if (!rc) {
|
||||
if (!DBCR_ACTIVE_EVENTS(child->thread.dbcr0,
|
||||
child->thread.dbcr1)) {
|
||||
child->thread.dbcr0 &= ~DBCR0_IDM;
|
||||
if (!DBCR_ACTIVE_EVENTS(child->thread.debug.dbcr0,
|
||||
child->thread.debug.dbcr1)) {
|
||||
child->thread.debug.dbcr0 &= ~DBCR0_IDM;
|
||||
child->thread.regs->msr &= ~MSR_DE;
|
||||
}
|
||||
}
|
||||
|
@ -1670,7 +1670,7 @@ long arch_ptrace(struct task_struct *child, long request,
|
|||
if (addr > 0)
|
||||
break;
|
||||
#ifdef CONFIG_PPC_ADV_DEBUG_REGS
|
||||
ret = put_user(child->thread.dac1, datalp);
|
||||
ret = put_user(child->thread.debug.dac1, datalp);
|
||||
#else
|
||||
dabr_fake = ((child->thread.hw_brk.address & (~HW_BRK_TYPE_DABR)) |
|
||||
(child->thread.hw_brk.type & HW_BRK_TYPE_DABR));
|
||||
|
|
|
@ -266,7 +266,7 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
|
|||
if (addr > 0)
|
||||
break;
|
||||
#ifdef CONFIG_PPC_ADV_DEBUG_REGS
|
||||
ret = put_user(child->thread.dac1, (u32 __user *)data);
|
||||
ret = put_user(child->thread.debug.dac1, (u32 __user *)data);
|
||||
#else
|
||||
dabr_fake = (
|
||||
(child->thread.hw_brk.address & (~HW_BRK_TYPE_DABR)) |
|
||||
|
|
|
@ -1312,7 +1312,7 @@ int sys_debug_setcontext(struct ucontext __user *ctx,
|
|||
unsigned char tmp;
|
||||
unsigned long new_msr = regs->msr;
|
||||
#ifdef CONFIG_PPC_ADV_DEBUG_REGS
|
||||
unsigned long new_dbcr0 = current->thread.dbcr0;
|
||||
unsigned long new_dbcr0 = current->thread.debug.dbcr0;
|
||||
#endif
|
||||
|
||||
for (i=0; i<ndbg; i++) {
|
||||
|
@ -1327,7 +1327,7 @@ int sys_debug_setcontext(struct ucontext __user *ctx,
|
|||
} else {
|
||||
new_dbcr0 &= ~DBCR0_IC;
|
||||
if (!DBCR_ACTIVE_EVENTS(new_dbcr0,
|
||||
current->thread.dbcr1)) {
|
||||
current->thread.debug.dbcr1)) {
|
||||
new_msr &= ~MSR_DE;
|
||||
new_dbcr0 &= ~DBCR0_IDM;
|
||||
}
|
||||
|
@ -1362,7 +1362,7 @@ int sys_debug_setcontext(struct ucontext __user *ctx,
|
|||
the user is really doing something wrong. */
|
||||
regs->msr = new_msr;
|
||||
#ifdef CONFIG_PPC_ADV_DEBUG_REGS
|
||||
current->thread.dbcr0 = new_dbcr0;
|
||||
current->thread.debug.dbcr0 = new_dbcr0;
|
||||
#endif
|
||||
|
||||
if (!access_ok(VERIFY_READ, ctx, sizeof(*ctx))
|
||||
|
|
|
@ -351,8 +351,8 @@ static inline int check_io_access(struct pt_regs *regs)
|
|||
#define REASON_TRAP ESR_PTR
|
||||
|
||||
/* single-step stuff */
|
||||
#define single_stepping(regs) (current->thread.dbcr0 & DBCR0_IC)
|
||||
#define clear_single_step(regs) (current->thread.dbcr0 &= ~DBCR0_IC)
|
||||
#define single_stepping(regs) (current->thread.debug.dbcr0 & DBCR0_IC)
|
||||
#define clear_single_step(regs) (current->thread.debug.dbcr0 &= ~DBCR0_IC)
|
||||
|
||||
#else
|
||||
/* On non-4xx, the reason for the machine check or program
|
||||
|
@ -1018,6 +1018,13 @@ static int emulate_instruction(struct pt_regs *regs)
|
|||
return emulate_isel(regs, instword);
|
||||
}
|
||||
|
||||
/* Emulate sync instruction variants */
|
||||
if ((instword & PPC_INST_SYNC_MASK) == PPC_INST_SYNC) {
|
||||
PPC_WARN_EMULATED(sync, regs);
|
||||
asm volatile("sync");
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PPC64
|
||||
/* Emulate the mfspr rD, DSCR. */
|
||||
if ((((instword & PPC_INST_MFSPR_DSCR_USER_MASK) ==
|
||||
|
@ -1461,7 +1468,8 @@ void SoftwareEmulation(struct pt_regs *regs)
|
|||
|
||||
if (!user_mode(regs)) {
|
||||
debugger(regs);
|
||||
die("Kernel Mode Software FPU Emulation", regs, SIGFPE);
|
||||
die("Kernel Mode Unimplemented Instruction or SW FPU Emulation",
|
||||
regs, SIGFPE);
|
||||
}
|
||||
|
||||
if (!emulate_math(regs))
|
||||
|
@ -1482,7 +1490,7 @@ static void handle_debug(struct pt_regs *regs, unsigned long debug_status)
|
|||
if (debug_status & (DBSR_DAC1R | DBSR_DAC1W)) {
|
||||
dbcr_dac(current) &= ~(DBCR_DAC1R | DBCR_DAC1W);
|
||||
#ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
|
||||
current->thread.dbcr2 &= ~DBCR2_DAC12MODE;
|
||||
current->thread.debug.dbcr2 &= ~DBCR2_DAC12MODE;
|
||||
#endif
|
||||
do_send_trap(regs, mfspr(SPRN_DAC1), debug_status, TRAP_HWBKPT,
|
||||
5);
|
||||
|
@ -1493,24 +1501,24 @@ static void handle_debug(struct pt_regs *regs, unsigned long debug_status)
|
|||
6);
|
||||
changed |= 0x01;
|
||||
} else if (debug_status & DBSR_IAC1) {
|
||||
current->thread.dbcr0 &= ~DBCR0_IAC1;
|
||||
current->thread.debug.dbcr0 &= ~DBCR0_IAC1;
|
||||
dbcr_iac_range(current) &= ~DBCR_IAC12MODE;
|
||||
do_send_trap(regs, mfspr(SPRN_IAC1), debug_status, TRAP_HWBKPT,
|
||||
1);
|
||||
changed |= 0x01;
|
||||
} else if (debug_status & DBSR_IAC2) {
|
||||
current->thread.dbcr0 &= ~DBCR0_IAC2;
|
||||
current->thread.debug.dbcr0 &= ~DBCR0_IAC2;
|
||||
do_send_trap(regs, mfspr(SPRN_IAC2), debug_status, TRAP_HWBKPT,
|
||||
2);
|
||||
changed |= 0x01;
|
||||
} else if (debug_status & DBSR_IAC3) {
|
||||
current->thread.dbcr0 &= ~DBCR0_IAC3;
|
||||
current->thread.debug.dbcr0 &= ~DBCR0_IAC3;
|
||||
dbcr_iac_range(current) &= ~DBCR_IAC34MODE;
|
||||
do_send_trap(regs, mfspr(SPRN_IAC3), debug_status, TRAP_HWBKPT,
|
||||
3);
|
||||
changed |= 0x01;
|
||||
} else if (debug_status & DBSR_IAC4) {
|
||||
current->thread.dbcr0 &= ~DBCR0_IAC4;
|
||||
current->thread.debug.dbcr0 &= ~DBCR0_IAC4;
|
||||
do_send_trap(regs, mfspr(SPRN_IAC4), debug_status, TRAP_HWBKPT,
|
||||
4);
|
||||
changed |= 0x01;
|
||||
|
@ -1520,19 +1528,20 @@ static void handle_debug(struct pt_regs *regs, unsigned long debug_status)
|
|||
* Check all other debug flags and see if that bit needs to be turned
|
||||
* back on or not.
|
||||
*/
|
||||
if (DBCR_ACTIVE_EVENTS(current->thread.dbcr0, current->thread.dbcr1))
|
||||
if (DBCR_ACTIVE_EVENTS(current->thread.debug.dbcr0,
|
||||
current->thread.debug.dbcr1))
|
||||
regs->msr |= MSR_DE;
|
||||
else
|
||||
/* Make sure the IDM flag is off */
|
||||
current->thread.dbcr0 &= ~DBCR0_IDM;
|
||||
current->thread.debug.dbcr0 &= ~DBCR0_IDM;
|
||||
|
||||
if (changed & 0x01)
|
||||
mtspr(SPRN_DBCR0, current->thread.dbcr0);
|
||||
mtspr(SPRN_DBCR0, current->thread.debug.dbcr0);
|
||||
}
|
||||
|
||||
void __kprobes DebugException(struct pt_regs *regs, unsigned long debug_status)
|
||||
{
|
||||
current->thread.dbsr = debug_status;
|
||||
current->thread.debug.dbsr = debug_status;
|
||||
|
||||
/* Hack alert: On BookE, Branch Taken stops on the branch itself, while
|
||||
* on server, it stops on the target of the branch. In order to simulate
|
||||
|
@ -1549,8 +1558,8 @@ void __kprobes DebugException(struct pt_regs *regs, unsigned long debug_status)
|
|||
|
||||
/* Do the single step trick only when coming from userspace */
|
||||
if (user_mode(regs)) {
|
||||
current->thread.dbcr0 &= ~DBCR0_BT;
|
||||
current->thread.dbcr0 |= DBCR0_IDM | DBCR0_IC;
|
||||
current->thread.debug.dbcr0 &= ~DBCR0_BT;
|
||||
current->thread.debug.dbcr0 |= DBCR0_IDM | DBCR0_IC;
|
||||
regs->msr |= MSR_DE;
|
||||
return;
|
||||
}
|
||||
|
@ -1578,13 +1587,13 @@ void __kprobes DebugException(struct pt_regs *regs, unsigned long debug_status)
|
|||
return;
|
||||
|
||||
if (user_mode(regs)) {
|
||||
current->thread.dbcr0 &= ~DBCR0_IC;
|
||||
if (DBCR_ACTIVE_EVENTS(current->thread.dbcr0,
|
||||
current->thread.dbcr1))
|
||||
current->thread.debug.dbcr0 &= ~DBCR0_IC;
|
||||
if (DBCR_ACTIVE_EVENTS(current->thread.debug.dbcr0,
|
||||
current->thread.debug.dbcr1))
|
||||
regs->msr |= MSR_DE;
|
||||
else
|
||||
/* Make sure the IDM bit is off */
|
||||
current->thread.dbcr0 &= ~DBCR0_IDM;
|
||||
current->thread.debug.dbcr0 &= ~DBCR0_IDM;
|
||||
}
|
||||
|
||||
_exception(SIGTRAP, regs, TRAP_TRACE, regs->nip);
|
||||
|
@ -1811,6 +1820,7 @@ struct ppc_emulated ppc_emulated = {
|
|||
WARN_EMULATED_SETUP(popcntb),
|
||||
WARN_EMULATED_SETUP(spe),
|
||||
WARN_EMULATED_SETUP(string),
|
||||
WARN_EMULATED_SETUP(sync),
|
||||
WARN_EMULATED_SETUP(unaligned),
|
||||
#ifdef CONFIG_MATH_EMULATION
|
||||
WARN_EMULATED_SETUP(math),
|
||||
|
|
|
@ -213,7 +213,12 @@ void setup_initial_memory_limit(phys_addr_t first_memblock_base,
|
|||
*/
|
||||
BUG_ON(first_memblock_base != 0);
|
||||
|
||||
#ifdef CONFIG_PIN_TLB
|
||||
/* 8xx can only access 24MB at the moment */
|
||||
memblock_set_current_limit(min_t(u64, first_memblock_size, 0x01800000));
|
||||
#else
|
||||
/* 8xx can only access 8MB at the moment */
|
||||
memblock_set_current_limit(min_t(u64, first_memblock_size, 0x00800000));
|
||||
#endif
|
||||
}
|
||||
#endif /* CONFIG_8xx */
|
||||
|
|
|
@ -32,8 +32,6 @@
|
|||
#include <asm/tlbflush.h>
|
||||
#include <asm/tlb.h>
|
||||
|
||||
#include "mmu_decl.h"
|
||||
|
||||
static inline int is_exec_fault(void)
|
||||
{
|
||||
return current->thread.regs && TRAP(current->thread.regs) == 0x400;
|
||||
|
@ -72,7 +70,7 @@ struct page * maybe_pte_to_page(pte_t pte)
|
|||
* support falls into the same category.
|
||||
*/
|
||||
|
||||
static pte_t set_pte_filter(pte_t pte, unsigned long addr)
|
||||
static pte_t set_pte_filter(pte_t pte)
|
||||
{
|
||||
pte = __pte(pte_val(pte) & ~_PAGE_HPTEFLAGS);
|
||||
if (pte_looks_normal(pte) && !(cpu_has_feature(CPU_FTR_COHERENT_ICACHE) ||
|
||||
|
@ -81,17 +79,6 @@ static pte_t set_pte_filter(pte_t pte, unsigned long addr)
|
|||
if (!pg)
|
||||
return pte;
|
||||
if (!test_bit(PG_arch_1, &pg->flags)) {
|
||||
#ifdef CONFIG_8xx
|
||||
/* On 8xx, cache control instructions (particularly
|
||||
* "dcbst" from flush_dcache_icache) fault as write
|
||||
* operation if there is an unpopulated TLB entry
|
||||
* for the address in question. To workaround that,
|
||||
* we invalidate the TLB here, thus avoiding dcbst
|
||||
* misbehaviour.
|
||||
*/
|
||||
/* 8xx doesn't care about PID, size or ind args */
|
||||
_tlbil_va(addr, 0, 0, 0);
|
||||
#endif /* CONFIG_8xx */
|
||||
flush_dcache_icache_page(pg);
|
||||
set_bit(PG_arch_1, &pg->flags);
|
||||
}
|
||||
|
@ -111,7 +98,7 @@ static pte_t set_access_flags_filter(pte_t pte, struct vm_area_struct *vma,
|
|||
* as we don't have two bits to spare for _PAGE_EXEC and _PAGE_HWEXEC so
|
||||
* instead we "filter out" the exec permission for non clean pages.
|
||||
*/
|
||||
static pte_t set_pte_filter(pte_t pte, unsigned long addr)
|
||||
static pte_t set_pte_filter(pte_t pte)
|
||||
{
|
||||
struct page *pg;
|
||||
|
||||
|
@ -193,7 +180,7 @@ void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep,
|
|||
* this context might not have been activated yet when this
|
||||
* is called.
|
||||
*/
|
||||
pte = set_pte_filter(pte, addr);
|
||||
pte = set_pte_filter(pte);
|
||||
|
||||
/* Perform the setting of the PTE */
|
||||
__set_pte_at(mm, addr, ptep, pte, 0);
|
||||
|
|
|
@ -204,7 +204,6 @@ static int mcu_remove(struct i2c_client *client)
|
|||
ret = mcu_gpiochip_remove(mcu);
|
||||
if (ret)
|
||||
return ret;
|
||||
i2c_set_clientdata(client, NULL);
|
||||
kfree(mcu);
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -218,83 +218,16 @@ config GE_IMP3A
|
|||
This board is a 3U CompactPCI Single Board Computer with a Freescale
|
||||
P2020 processor.
|
||||
|
||||
config P2041_RDB
|
||||
bool "Freescale P2041 RDB"
|
||||
select DEFAULT_UIMAGE
|
||||
select PPC_E500MC
|
||||
select PHYS_64BIT
|
||||
select SWIOTLB
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select GPIO_MPC8XXX
|
||||
select HAS_RAPIDIO
|
||||
select PPC_EPAPR_HV_PIC
|
||||
help
|
||||
This option enables support for the P2041 RDB board
|
||||
|
||||
config P3041_DS
|
||||
bool "Freescale P3041 DS"
|
||||
select DEFAULT_UIMAGE
|
||||
select PPC_E500MC
|
||||
select PHYS_64BIT
|
||||
select SWIOTLB
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select GPIO_MPC8XXX
|
||||
select HAS_RAPIDIO
|
||||
select PPC_EPAPR_HV_PIC
|
||||
help
|
||||
This option enables support for the P3041 DS board
|
||||
|
||||
config P4080_DS
|
||||
bool "Freescale P4080 DS"
|
||||
select DEFAULT_UIMAGE
|
||||
select PPC_E500MC
|
||||
select PHYS_64BIT
|
||||
select SWIOTLB
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select GPIO_MPC8XXX
|
||||
select HAS_RAPIDIO
|
||||
select PPC_EPAPR_HV_PIC
|
||||
help
|
||||
This option enables support for the P4080 DS board
|
||||
|
||||
config SGY_CTS1000
|
||||
tristate "Servergy CTS-1000 support"
|
||||
select GPIOLIB
|
||||
select OF_GPIO
|
||||
depends on P4080_DS
|
||||
depends on CORENET_GENERIC
|
||||
help
|
||||
Enable this to support functionality in Servergy's CTS-1000 systems.
|
||||
|
||||
endif # PPC32
|
||||
|
||||
config P5020_DS
|
||||
bool "Freescale P5020 DS"
|
||||
select DEFAULT_UIMAGE
|
||||
select E500
|
||||
select PPC_E500MC
|
||||
select PHYS_64BIT
|
||||
select SWIOTLB
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select GPIO_MPC8XXX
|
||||
select HAS_RAPIDIO
|
||||
select PPC_EPAPR_HV_PIC
|
||||
help
|
||||
This option enables support for the P5020 DS board
|
||||
|
||||
config P5040_DS
|
||||
bool "Freescale P5040 DS"
|
||||
select DEFAULT_UIMAGE
|
||||
select E500
|
||||
select PPC_E500MC
|
||||
select PHYS_64BIT
|
||||
select SWIOTLB
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select GPIO_MPC8XXX
|
||||
select HAS_RAPIDIO
|
||||
select PPC_EPAPR_HV_PIC
|
||||
help
|
||||
This option enables support for the P5040 DS board
|
||||
|
||||
config PPC_QEMU_E500
|
||||
bool "QEMU generic e500 platform"
|
||||
select DEFAULT_UIMAGE
|
||||
|
@ -310,10 +243,8 @@ config PPC_QEMU_E500
|
|||
unset based on the emulated CPU (or actual host CPU in the case
|
||||
of KVM).
|
||||
|
||||
if PPC64
|
||||
|
||||
config T4240_QDS
|
||||
bool "Freescale T4240 QDS"
|
||||
config CORENET_GENERIC
|
||||
bool "Freescale CoreNet Generic"
|
||||
select DEFAULT_UIMAGE
|
||||
select E500
|
||||
select PPC_E500MC
|
||||
|
@ -324,26 +255,14 @@ config T4240_QDS
|
|||
select HAS_RAPIDIO
|
||||
select PPC_EPAPR_HV_PIC
|
||||
help
|
||||
This option enables support for the T4240 QDS board
|
||||
This option enables support for the FSL CoreNet based boards.
|
||||
For 32bit kernel, the following boards are supported:
|
||||
P2041 RDB, P3041 DS and P4080 DS
|
||||
For 64bit kernel, the following boards are supported:
|
||||
T4240 QDS and B4 QDS
|
||||
The following boards are supported for both 32bit and 64bit kernel:
|
||||
P5020 DS and P5040 DS
|
||||
|
||||
config B4_QDS
|
||||
bool "Freescale B4 QDS"
|
||||
select DEFAULT_UIMAGE
|
||||
select E500
|
||||
select PPC_E500MC
|
||||
select PHYS_64BIT
|
||||
select SWIOTLB
|
||||
select GPIOLIB
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select HAS_RAPIDIO
|
||||
select PPC_EPAPR_HV_PIC
|
||||
help
|
||||
This option enables support for the B4 QDS board
|
||||
The B4 application development system B4 QDS is a complete
|
||||
debugging environment intended for engineers developing
|
||||
applications for the B4.
|
||||
|
||||
endif
|
||||
endif # FSL_SOC_BOOKE
|
||||
|
||||
config TQM85xx
|
||||
|
|
|
@ -18,13 +18,7 @@ obj-$(CONFIG_P1010_RDB) += p1010rdb.o
|
|||
obj-$(CONFIG_P1022_DS) += p1022_ds.o
|
||||
obj-$(CONFIG_P1022_RDK) += p1022_rdk.o
|
||||
obj-$(CONFIG_P1023_RDS) += p1023_rds.o
|
||||
obj-$(CONFIG_P2041_RDB) += p2041_rdb.o corenet_ds.o
|
||||
obj-$(CONFIG_P3041_DS) += p3041_ds.o corenet_ds.o
|
||||
obj-$(CONFIG_P4080_DS) += p4080_ds.o corenet_ds.o
|
||||
obj-$(CONFIG_P5020_DS) += p5020_ds.o corenet_ds.o
|
||||
obj-$(CONFIG_P5040_DS) += p5040_ds.o corenet_ds.o
|
||||
obj-$(CONFIG_T4240_QDS) += t4240_qds.o corenet_ds.o
|
||||
obj-$(CONFIG_B4_QDS) += b4_qds.o corenet_ds.o
|
||||
obj-$(CONFIG_CORENET_GENERIC) += corenet_generic.o
|
||||
obj-$(CONFIG_STX_GP3) += stx_gp3.o
|
||||
obj-$(CONFIG_TQM85xx) += tqm85xx.o
|
||||
obj-$(CONFIG_SBC8548) += sbc8548.o
|
||||
|
|
|
@ -1,102 +0,0 @@
|
|||
/*
|
||||
* B4 QDS Setup
|
||||
* Should apply for QDS platform of B4860 and it's personalities.
|
||||
* viz B4860/B4420/B4220QDS
|
||||
*
|
||||
* Copyright 2012 Freescale Semiconductor Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/kdev_t.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/phy.h>
|
||||
|
||||
#include <asm/time.h>
|
||||
#include <asm/machdep.h>
|
||||
#include <asm/pci-bridge.h>
|
||||
#include <mm/mmu_decl.h>
|
||||
#include <asm/prom.h>
|
||||
#include <asm/udbg.h>
|
||||
#include <asm/mpic.h>
|
||||
|
||||
#include <linux/of_platform.h>
|
||||
#include <sysdev/fsl_soc.h>
|
||||
#include <sysdev/fsl_pci.h>
|
||||
#include <asm/ehv_pic.h>
|
||||
|
||||
#include "corenet_ds.h"
|
||||
|
||||
/*
|
||||
* Called very early, device-tree isn't unflattened
|
||||
*/
|
||||
static int __init b4_qds_probe(void)
|
||||
{
|
||||
unsigned long root = of_get_flat_dt_root();
|
||||
#ifdef CONFIG_SMP
|
||||
extern struct smp_ops_t smp_85xx_ops;
|
||||
#endif
|
||||
|
||||
if ((of_flat_dt_is_compatible(root, "fsl,B4860QDS")) ||
|
||||
(of_flat_dt_is_compatible(root, "fsl,B4420QDS")) ||
|
||||
(of_flat_dt_is_compatible(root, "fsl,B4220QDS")))
|
||||
return 1;
|
||||
|
||||
/* Check if we're running under the Freescale hypervisor */
|
||||
if ((of_flat_dt_is_compatible(root, "fsl,B4860QDS-hv")) ||
|
||||
(of_flat_dt_is_compatible(root, "fsl,B4420QDS-hv")) ||
|
||||
(of_flat_dt_is_compatible(root, "fsl,B4220QDS-hv"))) {
|
||||
ppc_md.init_IRQ = ehv_pic_init;
|
||||
ppc_md.get_irq = ehv_pic_get_irq;
|
||||
ppc_md.restart = fsl_hv_restart;
|
||||
ppc_md.power_off = fsl_hv_halt;
|
||||
ppc_md.halt = fsl_hv_halt;
|
||||
#ifdef CONFIG_SMP
|
||||
/*
|
||||
* Disable the timebase sync operations because we can't write
|
||||
* to the timebase registers under the hypervisor.
|
||||
*/
|
||||
smp_85xx_ops.give_timebase = NULL;
|
||||
smp_85xx_ops.take_timebase = NULL;
|
||||
#endif
|
||||
return 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
define_machine(b4_qds) {
|
||||
.name = "B4 QDS",
|
||||
.probe = b4_qds_probe,
|
||||
.setup_arch = corenet_ds_setup_arch,
|
||||
.init_IRQ = corenet_ds_pic_init,
|
||||
#ifdef CONFIG_PCI
|
||||
.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
|
||||
#endif
|
||||
/* coreint doesn't play nice with lazy EE, use legacy mpic for now */
|
||||
#ifdef CONFIG_PPC64
|
||||
.get_irq = mpic_get_irq,
|
||||
#else
|
||||
.get_irq = mpic_get_coreint_irq,
|
||||
#endif
|
||||
.restart = fsl_rstcr_restart,
|
||||
.calibrate_decr = generic_calibrate_decr,
|
||||
.progress = udbg_progress,
|
||||
#ifdef CONFIG_PPC64
|
||||
.power_save = book3e_idle,
|
||||
#else
|
||||
.power_save = e500_idle,
|
||||
#endif
|
||||
};
|
||||
|
||||
machine_arch_initcall(b4_qds, corenet_ds_publish_devices);
|
||||
|
||||
#ifdef CONFIG_SWIOTLB
|
||||
machine_arch_initcall(b4_qds, swiotlb_setup_bus_notifier);
|
||||
#endif
|
|
@ -1,96 +0,0 @@
|
|||
/*
|
||||
* Corenet based SoC DS Setup
|
||||
*
|
||||
* Maintained by Kumar Gala (see MAINTAINERS for contact information)
|
||||
*
|
||||
* Copyright 2009-2011 Freescale Semiconductor Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/kdev_t.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/interrupt.h>
|
||||
|
||||
#include <asm/time.h>
|
||||
#include <asm/machdep.h>
|
||||
#include <asm/pci-bridge.h>
|
||||
#include <asm/ppc-pci.h>
|
||||
#include <mm/mmu_decl.h>
|
||||
#include <asm/prom.h>
|
||||
#include <asm/udbg.h>
|
||||
#include <asm/mpic.h>
|
||||
|
||||
#include <linux/of_platform.h>
|
||||
#include <sysdev/fsl_soc.h>
|
||||
#include <sysdev/fsl_pci.h>
|
||||
#include "smp.h"
|
||||
|
||||
void __init corenet_ds_pic_init(void)
|
||||
{
|
||||
struct mpic *mpic;
|
||||
unsigned int flags = MPIC_BIG_ENDIAN | MPIC_SINGLE_DEST_CPU |
|
||||
MPIC_NO_RESET;
|
||||
|
||||
if (ppc_md.get_irq == mpic_get_coreint_irq)
|
||||
flags |= MPIC_ENABLE_COREINT;
|
||||
|
||||
mpic = mpic_alloc(NULL, 0, flags, 0, 512, " OpenPIC ");
|
||||
BUG_ON(mpic == NULL);
|
||||
|
||||
mpic_init(mpic);
|
||||
}
|
||||
|
||||
/*
|
||||
* Setup the architecture
|
||||
*/
|
||||
void __init corenet_ds_setup_arch(void)
|
||||
{
|
||||
mpc85xx_smp_init();
|
||||
|
||||
swiotlb_detect_4g();
|
||||
|
||||
pr_info("%s board from Freescale Semiconductor\n", ppc_md.name);
|
||||
}
|
||||
|
||||
static const struct of_device_id of_device_ids[] = {
|
||||
{
|
||||
.compatible = "simple-bus"
|
||||
},
|
||||
{
|
||||
.compatible = "fsl,srio",
|
||||
},
|
||||
{
|
||||
.compatible = "fsl,p4080-pcie",
|
||||
},
|
||||
{
|
||||
.compatible = "fsl,qoriq-pcie-v2.2",
|
||||
},
|
||||
{
|
||||
.compatible = "fsl,qoriq-pcie-v2.3",
|
||||
},
|
||||
{
|
||||
.compatible = "fsl,qoriq-pcie-v2.4",
|
||||
},
|
||||
{
|
||||
.compatible = "fsl,qoriq-pcie-v3.0",
|
||||
},
|
||||
/* The following two are for the Freescale hypervisor */
|
||||
{
|
||||
.name = "hypervisor",
|
||||
},
|
||||
{
|
||||
.name = "handles",
|
||||
},
|
||||
{}
|
||||
};
|
||||
|
||||
int __init corenet_ds_publish_devices(void)
|
||||
{
|
||||
return of_platform_bus_probe(NULL, of_device_ids, NULL);
|
||||
}
|
|
@ -1,19 +0,0 @@
|
|||
/*
|
||||
* Corenet based SoC DS Setup
|
||||
*
|
||||
* Copyright 2009 Freescale Semiconductor Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef CORENET_DS_H
|
||||
#define CORENET_DS_H
|
||||
|
||||
extern void __init corenet_ds_pic_init(void);
|
||||
extern void __init corenet_ds_setup_arch(void);
|
||||
extern int __init corenet_ds_publish_devices(void);
|
||||
|
||||
#endif
|
182
arch/powerpc/platforms/85xx/corenet_generic.c
Normal file
182
arch/powerpc/platforms/85xx/corenet_generic.c
Normal file
|
@ -0,0 +1,182 @@
|
|||
/*
|
||||
* Corenet based SoC DS Setup
|
||||
*
|
||||
* Maintained by Kumar Gala (see MAINTAINERS for contact information)
|
||||
*
|
||||
* Copyright 2009-2011 Freescale Semiconductor Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/kdev_t.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/interrupt.h>
|
||||
|
||||
#include <asm/time.h>
|
||||
#include <asm/machdep.h>
|
||||
#include <asm/pci-bridge.h>
|
||||
#include <asm/ppc-pci.h>
|
||||
#include <mm/mmu_decl.h>
|
||||
#include <asm/prom.h>
|
||||
#include <asm/udbg.h>
|
||||
#include <asm/mpic.h>
|
||||
#include <asm/ehv_pic.h>
|
||||
|
||||
#include <linux/of_platform.h>
|
||||
#include <sysdev/fsl_soc.h>
|
||||
#include <sysdev/fsl_pci.h>
|
||||
#include "smp.h"
|
||||
|
||||
void __init corenet_gen_pic_init(void)
|
||||
{
|
||||
struct mpic *mpic;
|
||||
unsigned int flags = MPIC_BIG_ENDIAN | MPIC_SINGLE_DEST_CPU |
|
||||
MPIC_NO_RESET;
|
||||
|
||||
if (ppc_md.get_irq == mpic_get_coreint_irq)
|
||||
flags |= MPIC_ENABLE_COREINT;
|
||||
|
||||
mpic = mpic_alloc(NULL, 0, flags, 0, 512, " OpenPIC ");
|
||||
BUG_ON(mpic == NULL);
|
||||
|
||||
mpic_init(mpic);
|
||||
}
|
||||
|
||||
/*
|
||||
* Setup the architecture
|
||||
*/
|
||||
void __init corenet_gen_setup_arch(void)
|
||||
{
|
||||
mpc85xx_smp_init();
|
||||
|
||||
swiotlb_detect_4g();
|
||||
|
||||
pr_info("%s board from Freescale Semiconductor\n", ppc_md.name);
|
||||
}
|
||||
|
||||
static const struct of_device_id of_device_ids[] = {
|
||||
{
|
||||
.compatible = "simple-bus"
|
||||
},
|
||||
{
|
||||
.compatible = "fsl,srio",
|
||||
},
|
||||
{
|
||||
.compatible = "fsl,p4080-pcie",
|
||||
},
|
||||
{
|
||||
.compatible = "fsl,qoriq-pcie-v2.2",
|
||||
},
|
||||
{
|
||||
.compatible = "fsl,qoriq-pcie-v2.3",
|
||||
},
|
||||
{
|
||||
.compatible = "fsl,qoriq-pcie-v2.4",
|
||||
},
|
||||
{
|
||||
.compatible = "fsl,qoriq-pcie-v3.0",
|
||||
},
|
||||
/* The following two are for the Freescale hypervisor */
|
||||
{
|
||||
.name = "hypervisor",
|
||||
},
|
||||
{
|
||||
.name = "handles",
|
||||
},
|
||||
{}
|
||||
};
|
||||
|
||||
int __init corenet_gen_publish_devices(void)
|
||||
{
|
||||
return of_platform_bus_probe(NULL, of_device_ids, NULL);
|
||||
}
|
||||
|
||||
static const char * const boards[] __initconst = {
|
||||
"fsl,P2041RDB",
|
||||
"fsl,P3041DS",
|
||||
"fsl,P4080DS",
|
||||
"fsl,P5020DS",
|
||||
"fsl,P5040DS",
|
||||
"fsl,T4240QDS",
|
||||
"fsl,B4860QDS",
|
||||
"fsl,B4420QDS",
|
||||
"fsl,B4220QDS",
|
||||
NULL
|
||||
};
|
||||
|
||||
static const char * const hv_boards[] __initconst = {
|
||||
"fsl,P2041RDB-hv",
|
||||
"fsl,P3041DS-hv",
|
||||
"fsl,P4080DS-hv",
|
||||
"fsl,P5020DS-hv",
|
||||
"fsl,P5040DS-hv",
|
||||
"fsl,T4240QDS-hv",
|
||||
"fsl,B4860QDS-hv",
|
||||
"fsl,B4420QDS-hv",
|
||||
"fsl,B4220QDS-hv",
|
||||
NULL
|
||||
};
|
||||
|
||||
/*
|
||||
* Called very early, device-tree isn't unflattened
|
||||
*/
|
||||
static int __init corenet_generic_probe(void)
|
||||
{
|
||||
unsigned long root = of_get_flat_dt_root();
|
||||
#ifdef CONFIG_SMP
|
||||
extern struct smp_ops_t smp_85xx_ops;
|
||||
#endif
|
||||
|
||||
if (of_flat_dt_match(root, boards))
|
||||
return 1;
|
||||
|
||||
/* Check if we're running under the Freescale hypervisor */
|
||||
if (of_flat_dt_match(root, hv_boards)) {
|
||||
ppc_md.init_IRQ = ehv_pic_init;
|
||||
ppc_md.get_irq = ehv_pic_get_irq;
|
||||
ppc_md.restart = fsl_hv_restart;
|
||||
ppc_md.power_off = fsl_hv_halt;
|
||||
ppc_md.halt = fsl_hv_halt;
|
||||
#ifdef CONFIG_SMP
|
||||
/*
|
||||
* Disable the timebase sync operations because we can't write
|
||||
* to the timebase registers under the hypervisor.
|
||||
*/
|
||||
smp_85xx_ops.give_timebase = NULL;
|
||||
smp_85xx_ops.take_timebase = NULL;
|
||||
#endif
|
||||
return 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
define_machine(corenet_generic) {
|
||||
.name = "CoreNet Generic",
|
||||
.probe = corenet_generic_probe,
|
||||
.setup_arch = corenet_gen_setup_arch,
|
||||
.init_IRQ = corenet_gen_pic_init,
|
||||
#ifdef CONFIG_PCI
|
||||
.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
|
||||
#endif
|
||||
.get_irq = mpic_get_coreint_irq,
|
||||
.restart = fsl_rstcr_restart,
|
||||
.calibrate_decr = generic_calibrate_decr,
|
||||
.progress = udbg_progress,
|
||||
#ifdef CONFIG_PPC64
|
||||
.power_save = book3e_idle,
|
||||
#else
|
||||
.power_save = e500_idle,
|
||||
#endif
|
||||
};
|
||||
|
||||
machine_arch_initcall(corenet_generic, corenet_gen_publish_devices);
|
||||
|
||||
#ifdef CONFIG_SWIOTLB
|
||||
machine_arch_initcall(corenet_generic, swiotlb_setup_bus_notifier);
|
||||
#endif
|
|
@ -66,6 +66,8 @@ static int __init p1010_rdb_probe(void)
|
|||
|
||||
if (of_flat_dt_is_compatible(root, "fsl,P1010RDB"))
|
||||
return 1;
|
||||
if (of_flat_dt_is_compatible(root, "fsl,P1010RDB-PB"))
|
||||
return 1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
@ -1,87 +0,0 @@
|
|||
/*
|
||||
* P2041 RDB Setup
|
||||
*
|
||||
* Copyright 2011 Freescale Semiconductor Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/kdev_t.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/phy.h>
|
||||
|
||||
#include <asm/time.h>
|
||||
#include <asm/machdep.h>
|
||||
#include <asm/pci-bridge.h>
|
||||
#include <mm/mmu_decl.h>
|
||||
#include <asm/prom.h>
|
||||
#include <asm/udbg.h>
|
||||
#include <asm/mpic.h>
|
||||
|
||||
#include <linux/of_platform.h>
|
||||
#include <sysdev/fsl_soc.h>
|
||||
#include <sysdev/fsl_pci.h>
|
||||
#include <asm/ehv_pic.h>
|
||||
|
||||
#include "corenet_ds.h"
|
||||
|
||||
/*
|
||||
* Called very early, device-tree isn't unflattened
|
||||
*/
|
||||
static int __init p2041_rdb_probe(void)
|
||||
{
|
||||
unsigned long root = of_get_flat_dt_root();
|
||||
#ifdef CONFIG_SMP
|
||||
extern struct smp_ops_t smp_85xx_ops;
|
||||
#endif
|
||||
|
||||
if (of_flat_dt_is_compatible(root, "fsl,P2041RDB"))
|
||||
return 1;
|
||||
|
||||
/* Check if we're running under the Freescale hypervisor */
|
||||
if (of_flat_dt_is_compatible(root, "fsl,P2041RDB-hv")) {
|
||||
ppc_md.init_IRQ = ehv_pic_init;
|
||||
ppc_md.get_irq = ehv_pic_get_irq;
|
||||
ppc_md.restart = fsl_hv_restart;
|
||||
ppc_md.power_off = fsl_hv_halt;
|
||||
ppc_md.halt = fsl_hv_halt;
|
||||
#ifdef CONFIG_SMP
|
||||
/*
|
||||
* Disable the timebase sync operations because we can't write
|
||||
* to the timebase registers under the hypervisor.
|
||||
*/
|
||||
smp_85xx_ops.give_timebase = NULL;
|
||||
smp_85xx_ops.take_timebase = NULL;
|
||||
#endif
|
||||
return 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
define_machine(p2041_rdb) {
|
||||
.name = "P2041 RDB",
|
||||
.probe = p2041_rdb_probe,
|
||||
.setup_arch = corenet_ds_setup_arch,
|
||||
.init_IRQ = corenet_ds_pic_init,
|
||||
#ifdef CONFIG_PCI
|
||||
.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
|
||||
#endif
|
||||
.get_irq = mpic_get_coreint_irq,
|
||||
.restart = fsl_rstcr_restart,
|
||||
.calibrate_decr = generic_calibrate_decr,
|
||||
.progress = udbg_progress,
|
||||
.power_save = e500_idle,
|
||||
};
|
||||
|
||||
machine_arch_initcall(p2041_rdb, corenet_ds_publish_devices);
|
||||
|
||||
#ifdef CONFIG_SWIOTLB
|
||||
machine_arch_initcall(p2041_rdb, swiotlb_setup_bus_notifier);
|
||||
#endif
|
|
@ -1,89 +0,0 @@
|
|||
/*
|
||||
* P3041 DS Setup
|
||||
*
|
||||
* Maintained by Kumar Gala (see MAINTAINERS for contact information)
|
||||
*
|
||||
* Copyright 2009-2010 Freescale Semiconductor Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/kdev_t.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/phy.h>
|
||||
|
||||
#include <asm/time.h>
|
||||
#include <asm/machdep.h>
|
||||
#include <asm/pci-bridge.h>
|
||||
#include <mm/mmu_decl.h>
|
||||
#include <asm/prom.h>
|
||||
#include <asm/udbg.h>
|
||||
#include <asm/mpic.h>
|
||||
|
||||
#include <linux/of_platform.h>
|
||||
#include <sysdev/fsl_soc.h>
|
||||
#include <sysdev/fsl_pci.h>
|
||||
#include <asm/ehv_pic.h>
|
||||
|
||||
#include "corenet_ds.h"
|
||||
|
||||
/*
|
||||
* Called very early, device-tree isn't unflattened
|
||||
*/
|
||||
static int __init p3041_ds_probe(void)
|
||||
{
|
||||
unsigned long root = of_get_flat_dt_root();
|
||||
#ifdef CONFIG_SMP
|
||||
extern struct smp_ops_t smp_85xx_ops;
|
||||
#endif
|
||||
|
||||
if (of_flat_dt_is_compatible(root, "fsl,P3041DS"))
|
||||
return 1;
|
||||
|
||||
/* Check if we're running under the Freescale hypervisor */
|
||||
if (of_flat_dt_is_compatible(root, "fsl,P3041DS-hv")) {
|
||||
ppc_md.init_IRQ = ehv_pic_init;
|
||||
ppc_md.get_irq = ehv_pic_get_irq;
|
||||
ppc_md.restart = fsl_hv_restart;
|
||||
ppc_md.power_off = fsl_hv_halt;
|
||||
ppc_md.halt = fsl_hv_halt;
|
||||
#ifdef CONFIG_SMP
|
||||
/*
|
||||
* Disable the timebase sync operations because we can't write
|
||||
* to the timebase registers under the hypervisor.
|
||||
*/
|
||||
smp_85xx_ops.give_timebase = NULL;
|
||||
smp_85xx_ops.take_timebase = NULL;
|
||||
#endif
|
||||
return 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
define_machine(p3041_ds) {
|
||||
.name = "P3041 DS",
|
||||
.probe = p3041_ds_probe,
|
||||
.setup_arch = corenet_ds_setup_arch,
|
||||
.init_IRQ = corenet_ds_pic_init,
|
||||
#ifdef CONFIG_PCI
|
||||
.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
|
||||
#endif
|
||||
.get_irq = mpic_get_coreint_irq,
|
||||
.restart = fsl_rstcr_restart,
|
||||
.calibrate_decr = generic_calibrate_decr,
|
||||
.progress = udbg_progress,
|
||||
.power_save = e500_idle,
|
||||
};
|
||||
|
||||
machine_arch_initcall(p3041_ds, corenet_ds_publish_devices);
|
||||
|
||||
#ifdef CONFIG_SWIOTLB
|
||||
machine_arch_initcall(p3041_ds, swiotlb_setup_bus_notifier);
|
||||
#endif
|
|
@ -1,87 +0,0 @@
|
|||
/*
|
||||
* P4080 DS Setup
|
||||
*
|
||||
* Maintained by Kumar Gala (see MAINTAINERS for contact information)
|
||||
*
|
||||
* Copyright 2009 Freescale Semiconductor Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/kdev_t.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/interrupt.h>
|
||||
|
||||
#include <asm/time.h>
|
||||
#include <asm/machdep.h>
|
||||
#include <asm/pci-bridge.h>
|
||||
#include <mm/mmu_decl.h>
|
||||
#include <asm/prom.h>
|
||||
#include <asm/udbg.h>
|
||||
#include <asm/mpic.h>
|
||||
|
||||
#include <linux/of_platform.h>
|
||||
#include <sysdev/fsl_soc.h>
|
||||
#include <sysdev/fsl_pci.h>
|
||||
#include <asm/ehv_pic.h>
|
||||
|
||||
#include "corenet_ds.h"
|
||||
|
||||
/*
|
||||
* Called very early, device-tree isn't unflattened
|
||||
*/
|
||||
static int __init p4080_ds_probe(void)
|
||||
{
|
||||
unsigned long root = of_get_flat_dt_root();
|
||||
#ifdef CONFIG_SMP
|
||||
extern struct smp_ops_t smp_85xx_ops;
|
||||
#endif
|
||||
|
||||
if (of_flat_dt_is_compatible(root, "fsl,P4080DS"))
|
||||
return 1;
|
||||
|
||||
/* Check if we're running under the Freescale hypervisor */
|
||||
if (of_flat_dt_is_compatible(root, "fsl,P4080DS-hv")) {
|
||||
ppc_md.init_IRQ = ehv_pic_init;
|
||||
ppc_md.get_irq = ehv_pic_get_irq;
|
||||
ppc_md.restart = fsl_hv_restart;
|
||||
ppc_md.power_off = fsl_hv_halt;
|
||||
ppc_md.halt = fsl_hv_halt;
|
||||
#ifdef CONFIG_SMP
|
||||
/*
|
||||
* Disable the timebase sync operations because we can't write
|
||||
* to the timebase registers under the hypervisor.
|
||||
*/
|
||||
smp_85xx_ops.give_timebase = NULL;
|
||||
smp_85xx_ops.take_timebase = NULL;
|
||||
#endif
|
||||
return 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
define_machine(p4080_ds) {
|
||||
.name = "P4080 DS",
|
||||
.probe = p4080_ds_probe,
|
||||
.setup_arch = corenet_ds_setup_arch,
|
||||
.init_IRQ = corenet_ds_pic_init,
|
||||
#ifdef CONFIG_PCI
|
||||
.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
|
||||
#endif
|
||||
.get_irq = mpic_get_coreint_irq,
|
||||
.restart = fsl_rstcr_restart,
|
||||
.calibrate_decr = generic_calibrate_decr,
|
||||
.progress = udbg_progress,
|
||||
.power_save = e500_idle,
|
||||
};
|
||||
|
||||
machine_arch_initcall(p4080_ds, corenet_ds_publish_devices);
|
||||
#ifdef CONFIG_SWIOTLB
|
||||
machine_arch_initcall(p4080_ds, swiotlb_setup_bus_notifier);
|
||||
#endif
|
|
@ -1,93 +0,0 @@
|
|||
/*
|
||||
* P5020 DS Setup
|
||||
*
|
||||
* Maintained by Kumar Gala (see MAINTAINERS for contact information)
|
||||
*
|
||||
* Copyright 2009-2010 Freescale Semiconductor Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/kdev_t.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/phy.h>
|
||||
|
||||
#include <asm/time.h>
|
||||
#include <asm/machdep.h>
|
||||
#include <asm/pci-bridge.h>
|
||||
#include <mm/mmu_decl.h>
|
||||
#include <asm/prom.h>
|
||||
#include <asm/udbg.h>
|
||||
#include <asm/mpic.h>
|
||||
|
||||
#include <linux/of_platform.h>
|
||||
#include <sysdev/fsl_soc.h>
|
||||
#include <sysdev/fsl_pci.h>
|
||||
#include <asm/ehv_pic.h>
|
||||
|
||||
#include "corenet_ds.h"
|
||||
|
||||
/*
|
||||
* Called very early, device-tree isn't unflattened
|
||||
*/
|
||||
static int __init p5020_ds_probe(void)
|
||||
{
|
||||
unsigned long root = of_get_flat_dt_root();
|
||||
#ifdef CONFIG_SMP
|
||||
extern struct smp_ops_t smp_85xx_ops;
|
||||
#endif
|
||||
|
||||
if (of_flat_dt_is_compatible(root, "fsl,P5020DS"))
|
||||
return 1;
|
||||
|
||||
/* Check if we're running under the Freescale hypervisor */
|
||||
if (of_flat_dt_is_compatible(root, "fsl,P5020DS-hv")) {
|
||||
ppc_md.init_IRQ = ehv_pic_init;
|
||||
ppc_md.get_irq = ehv_pic_get_irq;
|
||||
ppc_md.restart = fsl_hv_restart;
|
||||
ppc_md.power_off = fsl_hv_halt;
|
||||
ppc_md.halt = fsl_hv_halt;
|
||||
#ifdef CONFIG_SMP
|
||||
/*
|
||||
* Disable the timebase sync operations because we can't write
|
||||
* to the timebase registers under the hypervisor.
|
||||
*/
|
||||
smp_85xx_ops.give_timebase = NULL;
|
||||
smp_85xx_ops.take_timebase = NULL;
|
||||
#endif
|
||||
return 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
define_machine(p5020_ds) {
|
||||
.name = "P5020 DS",
|
||||
.probe = p5020_ds_probe,
|
||||
.setup_arch = corenet_ds_setup_arch,
|
||||
.init_IRQ = corenet_ds_pic_init,
|
||||
#ifdef CONFIG_PCI
|
||||
.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
|
||||
#endif
|
||||
.get_irq = mpic_get_coreint_irq,
|
||||
.restart = fsl_rstcr_restart,
|
||||
.calibrate_decr = generic_calibrate_decr,
|
||||
.progress = udbg_progress,
|
||||
#ifdef CONFIG_PPC64
|
||||
.power_save = book3e_idle,
|
||||
#else
|
||||
.power_save = e500_idle,
|
||||
#endif
|
||||
};
|
||||
|
||||
machine_arch_initcall(p5020_ds, corenet_ds_publish_devices);
|
||||
|
||||
#ifdef CONFIG_SWIOTLB
|
||||
machine_arch_initcall(p5020_ds, swiotlb_setup_bus_notifier);
|
||||
#endif
|
|
@ -1,84 +0,0 @@
|
|||
/*
|
||||
* P5040 DS Setup
|
||||
*
|
||||
* Copyright 2009-2010 Freescale Semiconductor Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/pci.h>
|
||||
|
||||
#include <asm/machdep.h>
|
||||
#include <asm/udbg.h>
|
||||
#include <asm/mpic.h>
|
||||
|
||||
#include <linux/of_fdt.h>
|
||||
|
||||
#include <sysdev/fsl_soc.h>
|
||||
#include <sysdev/fsl_pci.h>
|
||||
#include <asm/ehv_pic.h>
|
||||
|
||||
#include "corenet_ds.h"
|
||||
|
||||
/*
|
||||
* Called very early, device-tree isn't unflattened
|
||||
*/
|
||||
static int __init p5040_ds_probe(void)
|
||||
{
|
||||
unsigned long root = of_get_flat_dt_root();
|
||||
#ifdef CONFIG_SMP
|
||||
extern struct smp_ops_t smp_85xx_ops;
|
||||
#endif
|
||||
|
||||
if (of_flat_dt_is_compatible(root, "fsl,P5040DS"))
|
||||
return 1;
|
||||
|
||||
/* Check if we're running under the Freescale hypervisor */
|
||||
if (of_flat_dt_is_compatible(root, "fsl,P5040DS-hv")) {
|
||||
ppc_md.init_IRQ = ehv_pic_init;
|
||||
ppc_md.get_irq = ehv_pic_get_irq;
|
||||
ppc_md.restart = fsl_hv_restart;
|
||||
ppc_md.power_off = fsl_hv_halt;
|
||||
ppc_md.halt = fsl_hv_halt;
|
||||
#ifdef CONFIG_SMP
|
||||
/*
|
||||
* Disable the timebase sync operations because we can't write
|
||||
* to the timebase registers under the hypervisor.
|
||||
*/
|
||||
smp_85xx_ops.give_timebase = NULL;
|
||||
smp_85xx_ops.take_timebase = NULL;
|
||||
#endif
|
||||
return 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
define_machine(p5040_ds) {
|
||||
.name = "P5040 DS",
|
||||
.probe = p5040_ds_probe,
|
||||
.setup_arch = corenet_ds_setup_arch,
|
||||
.init_IRQ = corenet_ds_pic_init,
|
||||
#ifdef CONFIG_PCI
|
||||
.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
|
||||
#endif
|
||||
.get_irq = mpic_get_coreint_irq,
|
||||
.restart = fsl_rstcr_restart,
|
||||
.calibrate_decr = generic_calibrate_decr,
|
||||
.progress = udbg_progress,
|
||||
#ifdef CONFIG_PPC64
|
||||
.power_save = book3e_idle,
|
||||
#else
|
||||
.power_save = e500_idle,
|
||||
#endif
|
||||
};
|
||||
|
||||
machine_arch_initcall(p5040_ds, corenet_ds_publish_devices);
|
||||
|
||||
#ifdef CONFIG_SWIOTLB
|
||||
machine_arch_initcall(p5040_ds, swiotlb_setup_bus_notifier);
|
||||
#endif
|
|
@ -1,93 +0,0 @@
|
|||
/*
|
||||
* T4240 QDS Setup
|
||||
*
|
||||
* Maintained by Kumar Gala (see MAINTAINERS for contact information)
|
||||
*
|
||||
* Copyright 2012 Freescale Semiconductor Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/kdev_t.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/phy.h>
|
||||
|
||||
#include <asm/time.h>
|
||||
#include <asm/machdep.h>
|
||||
#include <asm/pci-bridge.h>
|
||||
#include <mm/mmu_decl.h>
|
||||
#include <asm/prom.h>
|
||||
#include <asm/udbg.h>
|
||||
#include <asm/mpic.h>
|
||||
|
||||
#include <linux/of_platform.h>
|
||||
#include <sysdev/fsl_soc.h>
|
||||
#include <sysdev/fsl_pci.h>
|
||||
#include <asm/ehv_pic.h>
|
||||
|
||||
#include "corenet_ds.h"
|
||||
|
||||
/*
|
||||
* Called very early, device-tree isn't unflattened
|
||||
*/
|
||||
static int __init t4240_qds_probe(void)
|
||||
{
|
||||
unsigned long root = of_get_flat_dt_root();
|
||||
#ifdef CONFIG_SMP
|
||||
extern struct smp_ops_t smp_85xx_ops;
|
||||
#endif
|
||||
|
||||
if (of_flat_dt_is_compatible(root, "fsl,T4240QDS"))
|
||||
return 1;
|
||||
|
||||
/* Check if we're running under the Freescale hypervisor */
|
||||
if (of_flat_dt_is_compatible(root, "fsl,T4240QDS-hv")) {
|
||||
ppc_md.init_IRQ = ehv_pic_init;
|
||||
ppc_md.get_irq = ehv_pic_get_irq;
|
||||
ppc_md.restart = fsl_hv_restart;
|
||||
ppc_md.power_off = fsl_hv_halt;
|
||||
ppc_md.halt = fsl_hv_halt;
|
||||
#ifdef CONFIG_SMP
|
||||
/*
|
||||
* Disable the timebase sync operations because we can't write
|
||||
* to the timebase registers under the hypervisor.
|
||||
*/
|
||||
smp_85xx_ops.give_timebase = NULL;
|
||||
smp_85xx_ops.take_timebase = NULL;
|
||||
#endif
|
||||
return 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
define_machine(t4240_qds) {
|
||||
.name = "T4240 QDS",
|
||||
.probe = t4240_qds_probe,
|
||||
.setup_arch = corenet_ds_setup_arch,
|
||||
.init_IRQ = corenet_ds_pic_init,
|
||||
#ifdef CONFIG_PCI
|
||||
.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
|
||||
#endif
|
||||
.get_irq = mpic_get_coreint_irq,
|
||||
.restart = fsl_rstcr_restart,
|
||||
.calibrate_decr = generic_calibrate_decr,
|
||||
.progress = udbg_progress,
|
||||
#ifdef CONFIG_PPC64
|
||||
.power_save = book3e_idle,
|
||||
#else
|
||||
.power_save = e500_idle,
|
||||
#endif
|
||||
};
|
||||
|
||||
machine_arch_initcall(t4240_qds, corenet_ds_publish_devices);
|
||||
|
||||
#ifdef CONFIG_SWIOTLB
|
||||
machine_arch_initcall(t4240_qds, swiotlb_setup_bus_notifier);
|
||||
#endif
|
|
@ -181,6 +181,7 @@ struct irq_domain *hlwd_pic_init(struct device_node *np)
|
|||
&hlwd_irq_domain_ops, io_base);
|
||||
if (!irq_domain) {
|
||||
pr_err("failed to allocate irq_domain\n");
|
||||
iounmap(io_base);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
|
|
|
@ -40,7 +40,7 @@
|
|||
|
||||
static int fsl_pcie_bus_fixup, is_mpc83xx_pci;
|
||||
|
||||
static void quirk_fsl_pcie_header(struct pci_dev *dev)
|
||||
static void quirk_fsl_pcie_early(struct pci_dev *dev)
|
||||
{
|
||||
u8 hdr_type;
|
||||
|
||||
|
@ -562,7 +562,8 @@ int __init fsl_add_bridge(struct platform_device *pdev, int is_primary)
|
|||
}
|
||||
#endif /* CONFIG_FSL_SOC_BOOKE || CONFIG_PPC_86xx */
|
||||
|
||||
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_pcie_header);
|
||||
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID,
|
||||
quirk_fsl_pcie_early);
|
||||
|
||||
#if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_MPC512x)
|
||||
struct mpc83xx_pcie_priv {
|
||||
|
|
|
@ -228,7 +228,7 @@ static struct platform_device * __init mv64x60_eth_register_shared_pdev(
|
|||
|
||||
if (id == 0) {
|
||||
pdev = platform_device_register_simple("orion-mdio", -1, &r[1], 1);
|
||||
if (!pdev)
|
||||
if (IS_ERR(pdev))
|
||||
return pdev;
|
||||
}
|
||||
|
||||
|
|
Loading…
Reference in a new issue