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brcmfmac: 4373 save-restore support 

Use chipcommon sr_control0 register to check 4373 sr support.

Reviewed-by: Arend van Spriel <arend.vanspriel@broadcom.com>
Signed-off-by: Chi-Hsien Lin <chi-hsien.lin@cypress.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
This commit is contained in:
Chi-Hsien Lin 2018-11-21 07:53:50 +00:00 committed by Kalle Valo
parent f95a8d9c6a
commit 2f2d389efd
2 changed files with 24 additions and 0 deletions
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5
drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c
View File

@ -1365,6 +1365,11 @@ bool brcmf_chip_sr_capable(struct brcmf_chip *pub)
addr = CORE_CC_REG(base, sr_control1);
reg = chip->ops->read32(chip->ctx, addr);
return reg != 0;
case CY_CC_4373_CHIP_ID:
/* explicitly check SR engine enable bit */
addr = CORE_CC_REG(base, sr_control0);
reg = chip->ops->read32(chip->ctx, addr);
return (reg & CC_SR_CTL0_ENABLE_MASK) != 0;
case CY_CC_43012_CHIP_ID:
addr = CORE_CC_REG(pmu->base, retention_ctl);
reg = chip->ops->read32(chip->ctx, addr);

19
drivers/net/wireless/broadcom/brcm80211/include/chipcommon.h
View File

@ -269,6 +269,25 @@ struct chipcregs {
/* GSIO (spi/i2c) present, rev >= 37 */
#define CC_CAP2_GSIO 0x00000002
/* sr_control0, rev >= 48 */
#define CC_SR_CTL0_ENABLE_MASK BIT(0)
#define CC_SR_CTL0_ENABLE_SHIFT 0
#define CC_SR_CTL0_EN_SR_ENG_CLK_SHIFT 1 /* sr_clk to sr_memory enable */
#define CC_SR_CTL0_RSRC_TRIGGER_SHIFT 2 /* Rising edge resource trigger 0 to
* sr_engine
*/
#define CC_SR_CTL0_MIN_DIV_SHIFT 6 /* Min division value for fast clk
* in sr_engine
*/
#define CC_SR_CTL0_EN_SBC_STBY_SHIFT 16
#define CC_SR_CTL0_EN_SR_ALP_CLK_MASK_SHIFT 18
#define CC_SR_CTL0_EN_SR_HT_CLK_SHIFT 19
#define CC_SR_CTL0_ALLOW_PIC_SHIFT 20 /* Allow pic to separate power
* domains
*/
#define CC_SR_CTL0_MAX_SR_LQ_CLK_CNT_SHIFT 25
#define CC_SR_CTL0_EN_MEM_DISABLE_FOR_SLEEP 30
/* pmucapabilities */
#define PCAP_REV_MASK 0x000000ff
#define PCAP_RC_MASK 0x00001f00