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drm/amdgpu: clean up hw semaphore support in driver
No longer used. Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Ken Wang <Qingqing.Wang@amd.com> Reviewed-by: Monk Liu <monk.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
parent
a8480309df
commit
2f4b940033
19 changed files with 17 additions and 724 deletions
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@ -20,7 +20,7 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \
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amdgpu_fb.o amdgpu_gem.o amdgpu_ring.o \
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amdgpu_cs.o amdgpu_bios.o amdgpu_benchmark.o amdgpu_test.o \
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amdgpu_pm.o atombios_dp.o amdgpu_afmt.o amdgpu_trace_points.o \
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atombios_encoders.o amdgpu_semaphore.o amdgpu_sa.o atombios_i2c.o \
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atombios_encoders.o amdgpu_sa.o atombios_i2c.o \
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amdgpu_prime.o amdgpu_vm.o amdgpu_ib.o amdgpu_pll.o \
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amdgpu_ucode.o amdgpu_bo_list.o amdgpu_ctx.o amdgpu_sync.o
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@ -638,31 +638,10 @@ int amdgpu_mode_dumb_create(struct drm_file *file_priv,
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int amdgpu_mode_dumb_mmap(struct drm_file *filp,
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struct drm_device *dev,
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uint32_t handle, uint64_t *offset_p);
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/*
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* Semaphores.
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*/
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struct amdgpu_semaphore {
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struct amdgpu_sa_bo *sa_bo;
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signed waiters;
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uint64_t gpu_addr;
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};
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int amdgpu_semaphore_create(struct amdgpu_device *adev,
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struct amdgpu_semaphore **semaphore);
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bool amdgpu_semaphore_emit_signal(struct amdgpu_ring *ring,
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struct amdgpu_semaphore *semaphore);
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bool amdgpu_semaphore_emit_wait(struct amdgpu_ring *ring,
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struct amdgpu_semaphore *semaphore);
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void amdgpu_semaphore_free(struct amdgpu_device *adev,
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struct amdgpu_semaphore **semaphore,
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struct fence *fence);
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/*
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* Synchronization
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*/
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struct amdgpu_sync {
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struct amdgpu_semaphore *semaphores[AMDGPU_NUM_SYNCS];
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struct fence *sync_to[AMDGPU_MAX_RINGS];
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DECLARE_HASHTABLE(fences, 4);
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struct fence *last_vm_update;
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@ -81,7 +81,6 @@ int amdgpu_exp_hw_support = 0;
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int amdgpu_enable_scheduler = 1;
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int amdgpu_sched_jobs = 32;
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int amdgpu_sched_hw_submission = 2;
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int amdgpu_enable_semaphores = 0;
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int amdgpu_powerplay = -1;
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MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
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@ -162,9 +161,6 @@ module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444);
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MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)");
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module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444);
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MODULE_PARM_DESC(enable_semaphores, "Enable semaphores (1 = enable, 0 = disable (default))");
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module_param_named(enable_semaphores, amdgpu_enable_semaphores, int, 0644);
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#ifdef CONFIG_DRM_AMD_POWERPLAY
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MODULE_PARM_DESC(powerplay, "Powerplay component (1 = enable, 0 = disable, -1 = auto (default))");
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module_param_named(powerplay, amdgpu_powerplay, int, 0444);
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@ -1,102 +0,0 @@
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/*
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* Copyright 2011 Christian König.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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*/
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/*
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* Authors:
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* Christian König <deathsimple@vodafone.de>
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*/
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#include <drm/drmP.h>
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#include "amdgpu.h"
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#include "amdgpu_trace.h"
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int amdgpu_semaphore_create(struct amdgpu_device *adev,
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struct amdgpu_semaphore **semaphore)
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{
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int r;
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*semaphore = kmalloc(sizeof(struct amdgpu_semaphore), GFP_KERNEL);
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if (*semaphore == NULL) {
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return -ENOMEM;
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}
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r = amdgpu_sa_bo_new(&adev->ring_tmp_bo,
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&(*semaphore)->sa_bo, 8, 8);
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if (r) {
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kfree(*semaphore);
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*semaphore = NULL;
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return r;
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}
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(*semaphore)->waiters = 0;
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(*semaphore)->gpu_addr = amdgpu_sa_bo_gpu_addr((*semaphore)->sa_bo);
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*((uint64_t *)amdgpu_sa_bo_cpu_addr((*semaphore)->sa_bo)) = 0;
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return 0;
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}
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bool amdgpu_semaphore_emit_signal(struct amdgpu_ring *ring,
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struct amdgpu_semaphore *semaphore)
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{
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trace_amdgpu_semaphore_signale(ring->idx, semaphore);
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if (amdgpu_ring_emit_semaphore(ring, semaphore, false)) {
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--semaphore->waiters;
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/* for debugging lockup only, used by sysfs debug files */
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ring->last_semaphore_signal_addr = semaphore->gpu_addr;
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return true;
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}
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return false;
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}
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bool amdgpu_semaphore_emit_wait(struct amdgpu_ring *ring,
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struct amdgpu_semaphore *semaphore)
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{
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trace_amdgpu_semaphore_wait(ring->idx, semaphore);
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if (amdgpu_ring_emit_semaphore(ring, semaphore, true)) {
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++semaphore->waiters;
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/* for debugging lockup only, used by sysfs debug files */
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ring->last_semaphore_wait_addr = semaphore->gpu_addr;
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return true;
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}
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return false;
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}
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void amdgpu_semaphore_free(struct amdgpu_device *adev,
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struct amdgpu_semaphore **semaphore,
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struct fence *fence)
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{
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if (semaphore == NULL || *semaphore == NULL) {
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return;
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}
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if ((*semaphore)->waiters > 0) {
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dev_err(adev->dev, "semaphore %p has more waiters than signalers,"
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" hardware lockup imminent!\n", *semaphore);
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}
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amdgpu_sa_bo_free(adev, &(*semaphore)->sa_bo, fence);
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kfree(*semaphore);
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*semaphore = NULL;
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}
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@ -48,9 +48,6 @@ void amdgpu_sync_create(struct amdgpu_sync *sync)
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{
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unsigned i;
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for (i = 0; i < AMDGPU_NUM_SYNCS; ++i)
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sync->semaphores[i] = NULL;
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for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
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sync->sync_to[i] = NULL;
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@ -153,13 +150,13 @@ static void *amdgpu_sync_get_owner(struct fence *f)
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}
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/**
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* amdgpu_sync_resv - use the semaphores to sync to a reservation object
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* amdgpu_sync_resv - sync to a reservation object
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*
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* @sync: sync object to add fences from reservation object to
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* @resv: reservation object with embedded fence
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* @shared: true if we should only sync to the exclusive fence
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*
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* Sync to the fence using the semaphore objects
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* Sync to the fence
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*/
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int amdgpu_sync_resv(struct amdgpu_device *adev,
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struct amdgpu_sync *sync,
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@ -250,9 +247,6 @@ int amdgpu_sync_wait(struct amdgpu_sync *sync)
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kfree(e);
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}
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if (amdgpu_enable_semaphores)
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return 0;
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for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
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struct fence *fence = sync->sync_to[i];
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if (!fence)
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@ -279,12 +273,10 @@ int amdgpu_sync_rings(struct amdgpu_sync *sync,
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struct amdgpu_ring *ring)
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{
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struct amdgpu_device *adev = ring->adev;
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unsigned count = 0;
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int i, r;
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for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
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struct amdgpu_ring *other = adev->rings[i];
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struct amdgpu_semaphore *semaphore;
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struct amdgpu_fence *fence;
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if (!sync->sync_to[i])
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@ -292,64 +284,19 @@ int amdgpu_sync_rings(struct amdgpu_sync *sync,
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fence = to_amdgpu_fence(sync->sync_to[i]);
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/* check if we really need to sync */
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if (!amdgpu_enable_scheduler &&
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!amdgpu_fence_need_sync(fence, ring))
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continue;
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/* prevent GPU deadlocks */
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if (!other->ready) {
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dev_err(adev->dev, "Syncing to a disabled ring!");
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return -EINVAL;
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}
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if (amdgpu_enable_scheduler || !amdgpu_enable_semaphores) {
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if (amdgpu_enable_scheduler) {
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r = fence_wait(sync->sync_to[i], true);
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if (r)
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return r;
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continue;
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}
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if (count >= AMDGPU_NUM_SYNCS) {
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/* not enough room, wait manually */
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r = fence_wait(&fence->base, false);
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if (r)
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return r;
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continue;
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}
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r = amdgpu_semaphore_create(adev, &semaphore);
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if (r)
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return r;
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sync->semaphores[count++] = semaphore;
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/* allocate enough space for sync command */
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r = amdgpu_ring_alloc(other, 16);
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if (r)
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return r;
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/* emit the signal semaphore */
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if (!amdgpu_semaphore_emit_signal(other, semaphore)) {
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/* signaling wasn't successful wait manually */
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amdgpu_ring_undo(other);
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r = fence_wait(&fence->base, false);
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if (r)
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return r;
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continue;
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}
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/* we assume caller has already allocated space on waiters ring */
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if (!amdgpu_semaphore_emit_wait(ring, semaphore)) {
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/* waiting wasn't successful wait manually */
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amdgpu_ring_undo(other);
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r = fence_wait(&fence->base, false);
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if (r)
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return r;
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continue;
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}
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amdgpu_ring_commit(other);
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amdgpu_fence_note_sync(fence, ring);
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}
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return 0;
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@ -362,7 +309,7 @@ int amdgpu_sync_rings(struct amdgpu_sync *sync,
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* @sync: sync object to use
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* @fence: fence to use for the free
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*
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* Free the sync object by freeing all semaphores in it.
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* Free the sync object.
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*/
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void amdgpu_sync_free(struct amdgpu_device *adev,
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struct amdgpu_sync *sync,
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@ -378,9 +325,6 @@ void amdgpu_sync_free(struct amdgpu_device *adev,
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kfree(e);
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}
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for (i = 0; i < AMDGPU_NUM_SYNCS; ++i)
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amdgpu_semaphore_free(adev, &sync->semaphores[i], fence);
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for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
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fence_put(sync->sync_to[i]);
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@ -238,144 +238,10 @@ void amdgpu_test_moves(struct amdgpu_device *adev)
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amdgpu_do_test_moves(adev);
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}
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static int amdgpu_test_create_and_emit_fence(struct amdgpu_device *adev,
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struct amdgpu_ring *ring,
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struct fence **fence)
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{
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uint32_t handle = ring->idx ^ 0xdeafbeef;
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int r;
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if (ring == &adev->uvd.ring) {
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r = amdgpu_uvd_get_create_msg(ring, handle, NULL);
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if (r) {
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DRM_ERROR("Failed to get dummy create msg\n");
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return r;
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}
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r = amdgpu_uvd_get_destroy_msg(ring, handle, fence);
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if (r) {
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DRM_ERROR("Failed to get dummy destroy msg\n");
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return r;
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}
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} else if (ring == &adev->vce.ring[0] ||
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ring == &adev->vce.ring[1]) {
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r = amdgpu_vce_get_create_msg(ring, handle, NULL);
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if (r) {
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DRM_ERROR("Failed to get dummy create msg\n");
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return r;
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}
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r = amdgpu_vce_get_destroy_msg(ring, handle, fence);
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if (r) {
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DRM_ERROR("Failed to get dummy destroy msg\n");
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return r;
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}
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} else {
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struct amdgpu_fence *a_fence = NULL;
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r = amdgpu_ring_lock(ring, 64);
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if (r) {
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DRM_ERROR("Failed to lock ring A %d\n", ring->idx);
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return r;
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}
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amdgpu_fence_emit(ring, AMDGPU_FENCE_OWNER_UNDEFINED, &a_fence);
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amdgpu_ring_unlock_commit(ring);
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*fence = &a_fence->base;
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}
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return 0;
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}
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void amdgpu_test_ring_sync(struct amdgpu_device *adev,
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struct amdgpu_ring *ringA,
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struct amdgpu_ring *ringB)
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{
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struct fence *fence1 = NULL, *fence2 = NULL;
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struct amdgpu_semaphore *semaphore = NULL;
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int r;
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r = amdgpu_semaphore_create(adev, &semaphore);
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if (r) {
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DRM_ERROR("Failed to create semaphore\n");
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goto out_cleanup;
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}
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r = amdgpu_ring_lock(ringA, 64);
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if (r) {
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DRM_ERROR("Failed to lock ring A %d\n", ringA->idx);
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goto out_cleanup;
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}
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amdgpu_semaphore_emit_wait(ringA, semaphore);
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amdgpu_ring_unlock_commit(ringA);
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r = amdgpu_test_create_and_emit_fence(adev, ringA, &fence1);
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if (r)
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goto out_cleanup;
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r = amdgpu_ring_lock(ringA, 64);
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if (r) {
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DRM_ERROR("Failed to lock ring A %d\n", ringA->idx);
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goto out_cleanup;
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}
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amdgpu_semaphore_emit_wait(ringA, semaphore);
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amdgpu_ring_unlock_commit(ringA);
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r = amdgpu_test_create_and_emit_fence(adev, ringA, &fence2);
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if (r)
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goto out_cleanup;
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mdelay(1000);
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if (fence_is_signaled(fence1)) {
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DRM_ERROR("Fence 1 signaled without waiting for semaphore.\n");
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goto out_cleanup;
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}
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r = amdgpu_ring_lock(ringB, 64);
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if (r) {
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DRM_ERROR("Failed to lock ring B %p\n", ringB);
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goto out_cleanup;
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}
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amdgpu_semaphore_emit_signal(ringB, semaphore);
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amdgpu_ring_unlock_commit(ringB);
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r = fence_wait(fence1, false);
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if (r) {
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DRM_ERROR("Failed to wait for sync fence 1\n");
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goto out_cleanup;
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}
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mdelay(1000);
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if (fence_is_signaled(fence2)) {
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DRM_ERROR("Fence 2 signaled without waiting for semaphore.\n");
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goto out_cleanup;
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}
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r = amdgpu_ring_lock(ringB, 64);
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if (r) {
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DRM_ERROR("Failed to lock ring B %p\n", ringB);
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goto out_cleanup;
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}
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amdgpu_semaphore_emit_signal(ringB, semaphore);
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amdgpu_ring_unlock_commit(ringB);
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r = fence_wait(fence2, false);
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if (r) {
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DRM_ERROR("Failed to wait for sync fence 1\n");
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goto out_cleanup;
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}
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out_cleanup:
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amdgpu_semaphore_free(adev, &semaphore, NULL);
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|
||||
if (fence1)
|
||||
fence_put(fence1);
|
||||
|
||||
if (fence2)
|
||||
fence_put(fence2);
|
||||
|
||||
if (r)
|
||||
printk(KERN_WARNING "Error while testing ring sync (%d).\n", r);
|
||||
}
|
||||
|
||||
static void amdgpu_test_ring_sync2(struct amdgpu_device *adev,
|
||||
|
@ -383,109 +249,6 @@ static void amdgpu_test_ring_sync2(struct amdgpu_device *adev,
|
|||
struct amdgpu_ring *ringB,
|
||||
struct amdgpu_ring *ringC)
|
||||
{
|
||||
struct fence *fenceA = NULL, *fenceB = NULL;
|
||||
struct amdgpu_semaphore *semaphore = NULL;
|
||||
bool sigA, sigB;
|
||||
int i, r;
|
||||
|
||||
r = amdgpu_semaphore_create(adev, &semaphore);
|
||||
if (r) {
|
||||
DRM_ERROR("Failed to create semaphore\n");
|
||||
goto out_cleanup;
|
||||
}
|
||||
|
||||
r = amdgpu_ring_lock(ringA, 64);
|
||||
if (r) {
|
||||
DRM_ERROR("Failed to lock ring A %d\n", ringA->idx);
|
||||
goto out_cleanup;
|
||||
}
|
||||
amdgpu_semaphore_emit_wait(ringA, semaphore);
|
||||
amdgpu_ring_unlock_commit(ringA);
|
||||
|
||||
r = amdgpu_test_create_and_emit_fence(adev, ringA, &fenceA);
|
||||
if (r)
|
||||
goto out_cleanup;
|
||||
|
||||
r = amdgpu_ring_lock(ringB, 64);
|
||||
if (r) {
|
||||
DRM_ERROR("Failed to lock ring B %d\n", ringB->idx);
|
||||
goto out_cleanup;
|
||||
}
|
||||
amdgpu_semaphore_emit_wait(ringB, semaphore);
|
||||
amdgpu_ring_unlock_commit(ringB);
|
||||
r = amdgpu_test_create_and_emit_fence(adev, ringB, &fenceB);
|
||||
if (r)
|
||||
goto out_cleanup;
|
||||
|
||||
mdelay(1000);
|
||||
|
||||
if (fence_is_signaled(fenceA)) {
|
||||
DRM_ERROR("Fence A signaled without waiting for semaphore.\n");
|
||||
goto out_cleanup;
|
||||
}
|
||||
if (fence_is_signaled(fenceB)) {
|
||||
DRM_ERROR("Fence B signaled without waiting for semaphore.\n");
|
||||
goto out_cleanup;
|
||||
}
|
||||
|
||||
r = amdgpu_ring_lock(ringC, 64);
|
||||
if (r) {
|
||||
DRM_ERROR("Failed to lock ring B %p\n", ringC);
|
||||
goto out_cleanup;
|
||||
}
|
||||
amdgpu_semaphore_emit_signal(ringC, semaphore);
|
||||
amdgpu_ring_unlock_commit(ringC);
|
||||
|
||||
for (i = 0; i < 30; ++i) {
|
||||
mdelay(100);
|
||||
sigA = fence_is_signaled(fenceA);
|
||||
sigB = fence_is_signaled(fenceB);
|
||||
if (sigA || sigB)
|
||||
break;
|
||||
}
|
||||
|
||||
if (!sigA && !sigB) {
|
||||
DRM_ERROR("Neither fence A nor B has been signaled\n");
|
||||
goto out_cleanup;
|
||||
} else if (sigA && sigB) {
|
||||
DRM_ERROR("Both fence A and B has been signaled\n");
|
||||
goto out_cleanup;
|
||||
}
|
||||
|
||||
DRM_INFO("Fence %c was first signaled\n", sigA ? 'A' : 'B');
|
||||
|
||||
r = amdgpu_ring_lock(ringC, 64);
|
||||
if (r) {
|
||||
DRM_ERROR("Failed to lock ring B %p\n", ringC);
|
||||
goto out_cleanup;
|
||||
}
|
||||
amdgpu_semaphore_emit_signal(ringC, semaphore);
|
||||
amdgpu_ring_unlock_commit(ringC);
|
||||
|
||||
mdelay(1000);
|
||||
|
||||
r = fence_wait(fenceA, false);
|
||||
if (r) {
|
||||
DRM_ERROR("Failed to wait for sync fence A\n");
|
||||
goto out_cleanup;
|
||||
}
|
||||
r = fence_wait(fenceB, false);
|
||||
if (r) {
|
||||
DRM_ERROR("Failed to wait for sync fence B\n");
|
||||
goto out_cleanup;
|
||||
}
|
||||
|
||||
out_cleanup:
|
||||
amdgpu_semaphore_free(adev, &semaphore, NULL);
|
||||
|
||||
if (fenceA)
|
||||
fence_put(fenceA);
|
||||
|
||||
if (fenceB)
|
||||
fence_put(fenceB);
|
||||
|
||||
if (r)
|
||||
printk(KERN_WARNING "Error while testing ring sync (%d).\n", r);
|
||||
}
|
||||
|
||||
static bool amdgpu_test_sync_possible(struct amdgpu_ring *ringA,
|
||||
|
|
|
@ -247,42 +247,6 @@ TRACE_EVENT(amdgpu_bo_list_set,
|
|||
TP_printk("list=%p, bo=%p", __entry->list, __entry->bo)
|
||||
);
|
||||
|
||||
DECLARE_EVENT_CLASS(amdgpu_semaphore_request,
|
||||
|
||||
TP_PROTO(int ring, struct amdgpu_semaphore *sem),
|
||||
|
||||
TP_ARGS(ring, sem),
|
||||
|
||||
TP_STRUCT__entry(
|
||||
__field(int, ring)
|
||||
__field(signed, waiters)
|
||||
__field(uint64_t, gpu_addr)
|
||||
),
|
||||
|
||||
TP_fast_assign(
|
||||
__entry->ring = ring;
|
||||
__entry->waiters = sem->waiters;
|
||||
__entry->gpu_addr = sem->gpu_addr;
|
||||
),
|
||||
|
||||
TP_printk("ring=%u, waiters=%d, addr=%010Lx", __entry->ring,
|
||||
__entry->waiters, __entry->gpu_addr)
|
||||
);
|
||||
|
||||
DEFINE_EVENT(amdgpu_semaphore_request, amdgpu_semaphore_signale,
|
||||
|
||||
TP_PROTO(int ring, struct amdgpu_semaphore *sem),
|
||||
|
||||
TP_ARGS(ring, sem)
|
||||
);
|
||||
|
||||
DEFINE_EVENT(amdgpu_semaphore_request, amdgpu_semaphore_wait,
|
||||
|
||||
TP_PROTO(int ring, struct amdgpu_semaphore *sem),
|
||||
|
||||
TP_ARGS(ring, sem)
|
||||
);
|
||||
|
||||
#endif
|
||||
|
||||
/* This part must be outside protection */
|
||||
|
|
|
@ -742,30 +742,6 @@ int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, uint32_t ib_idx)
|
|||
return r;
|
||||
}
|
||||
|
||||
/**
|
||||
* amdgpu_vce_ring_emit_semaphore - emit a semaphore command
|
||||
*
|
||||
* @ring: engine to use
|
||||
* @semaphore: address of semaphore
|
||||
* @emit_wait: true=emit wait, false=emit signal
|
||||
*
|
||||
*/
|
||||
bool amdgpu_vce_ring_emit_semaphore(struct amdgpu_ring *ring,
|
||||
struct amdgpu_semaphore *semaphore,
|
||||
bool emit_wait)
|
||||
{
|
||||
uint64_t addr = semaphore->gpu_addr;
|
||||
|
||||
amdgpu_ring_write(ring, VCE_CMD_SEMAPHORE);
|
||||
amdgpu_ring_write(ring, (addr >> 3) & 0x000FFFFF);
|
||||
amdgpu_ring_write(ring, (addr >> 23) & 0x000FFFFF);
|
||||
amdgpu_ring_write(ring, 0x01003000 | (emit_wait ? 1 : 0));
|
||||
if (!emit_wait)
|
||||
amdgpu_ring_write(ring, VCE_CMD_END);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
/**
|
||||
* amdgpu_vce_ring_emit_ib - execute indirect buffer
|
||||
*
|
||||
|
|
|
@ -34,9 +34,6 @@ int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
|
|||
struct fence **fence);
|
||||
void amdgpu_vce_free_handles(struct amdgpu_device *adev, struct drm_file *filp);
|
||||
int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, uint32_t ib_idx);
|
||||
bool amdgpu_vce_ring_emit_semaphore(struct amdgpu_ring *ring,
|
||||
struct amdgpu_semaphore *semaphore,
|
||||
bool emit_wait);
|
||||
void amdgpu_vce_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
|
||||
void amdgpu_vce_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
|
||||
unsigned flags);
|
||||
|
|
|
@ -294,30 +294,6 @@ static void cik_sdma_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq
|
|||
amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_TRAP, 0, 0));
|
||||
}
|
||||
|
||||
/**
|
||||
* cik_sdma_ring_emit_semaphore - emit a semaphore on the dma ring
|
||||
*
|
||||
* @ring: amdgpu_ring structure holding ring information
|
||||
* @semaphore: amdgpu semaphore object
|
||||
* @emit_wait: wait or signal semaphore
|
||||
*
|
||||
* Add a DMA semaphore packet to the ring wait on or signal
|
||||
* other rings (CIK).
|
||||
*/
|
||||
static bool cik_sdma_ring_emit_semaphore(struct amdgpu_ring *ring,
|
||||
struct amdgpu_semaphore *semaphore,
|
||||
bool emit_wait)
|
||||
{
|
||||
u64 addr = semaphore->gpu_addr;
|
||||
u32 extra_bits = emit_wait ? 0 : SDMA_SEMAPHORE_EXTRA_S;
|
||||
|
||||
amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SEMAPHORE, 0, extra_bits));
|
||||
amdgpu_ring_write(ring, addr & 0xfffffff8);
|
||||
amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
/**
|
||||
* cik_sdma_gfx_stop - stop the gfx async dma engines
|
||||
*
|
||||
|
@ -1297,7 +1273,7 @@ static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = {
|
|||
.parse_cs = NULL,
|
||||
.emit_ib = cik_sdma_ring_emit_ib,
|
||||
.emit_fence = cik_sdma_ring_emit_fence,
|
||||
.emit_semaphore = cik_sdma_ring_emit_semaphore,
|
||||
.emit_semaphore = NULL,
|
||||
.emit_vm_flush = cik_sdma_ring_emit_vm_flush,
|
||||
.emit_hdp_flush = cik_sdma_ring_emit_hdp_flush,
|
||||
.test_ring = cik_sdma_ring_test_ring,
|
||||
|
|
|
@ -2516,36 +2516,6 @@ static void gfx_v7_0_ring_emit_fence_compute(struct amdgpu_ring *ring,
|
|||
amdgpu_ring_write(ring, upper_32_bits(seq));
|
||||
}
|
||||
|
||||
/**
|
||||
* gfx_v7_0_ring_emit_semaphore - emit a semaphore on the CP ring
|
||||
*
|
||||
* @ring: amdgpu ring buffer object
|
||||
* @semaphore: amdgpu semaphore object
|
||||
* @emit_wait: Is this a sempahore wait?
|
||||
*
|
||||
* Emits a semaphore signal/wait packet to the CP ring and prevents the PFP
|
||||
* from running ahead of semaphore waits.
|
||||
*/
|
||||
static bool gfx_v7_0_ring_emit_semaphore(struct amdgpu_ring *ring,
|
||||
struct amdgpu_semaphore *semaphore,
|
||||
bool emit_wait)
|
||||
{
|
||||
uint64_t addr = semaphore->gpu_addr;
|
||||
unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL;
|
||||
|
||||
amdgpu_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1));
|
||||
amdgpu_ring_write(ring, addr & 0xffffffff);
|
||||
amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | sel);
|
||||
|
||||
if (emit_wait && (ring->type == AMDGPU_RING_TYPE_GFX)) {
|
||||
/* Prevent the PFP from running ahead of the semaphore wait */
|
||||
amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
|
||||
amdgpu_ring_write(ring, 0x0);
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
/*
|
||||
* IB stuff
|
||||
*/
|
||||
|
@ -5567,7 +5537,7 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = {
|
|||
.parse_cs = NULL,
|
||||
.emit_ib = gfx_v7_0_ring_emit_ib_gfx,
|
||||
.emit_fence = gfx_v7_0_ring_emit_fence_gfx,
|
||||
.emit_semaphore = gfx_v7_0_ring_emit_semaphore,
|
||||
.emit_semaphore = NULL,
|
||||
.emit_vm_flush = gfx_v7_0_ring_emit_vm_flush,
|
||||
.emit_gds_switch = gfx_v7_0_ring_emit_gds_switch,
|
||||
.emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush,
|
||||
|
@ -5583,7 +5553,7 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = {
|
|||
.parse_cs = NULL,
|
||||
.emit_ib = gfx_v7_0_ring_emit_ib_compute,
|
||||
.emit_fence = gfx_v7_0_ring_emit_fence_compute,
|
||||
.emit_semaphore = gfx_v7_0_ring_emit_semaphore,
|
||||
.emit_semaphore = NULL,
|
||||
.emit_vm_flush = gfx_v7_0_ring_emit_vm_flush,
|
||||
.emit_gds_switch = gfx_v7_0_ring_emit_gds_switch,
|
||||
.emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush,
|
||||
|
|
|
@ -4762,44 +4762,6 @@ static void gfx_v8_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
|
|||
|
||||
}
|
||||
|
||||
/**
|
||||
* gfx_v8_0_ring_emit_semaphore - emit a semaphore on the CP ring
|
||||
*
|
||||
* @ring: amdgpu ring buffer object
|
||||
* @semaphore: amdgpu semaphore object
|
||||
* @emit_wait: Is this a sempahore wait?
|
||||
*
|
||||
* Emits a semaphore signal/wait packet to the CP ring and prevents the PFP
|
||||
* from running ahead of semaphore waits.
|
||||
*/
|
||||
static bool gfx_v8_0_ring_emit_semaphore(struct amdgpu_ring *ring,
|
||||
struct amdgpu_semaphore *semaphore,
|
||||
bool emit_wait)
|
||||
{
|
||||
uint64_t addr = semaphore->gpu_addr;
|
||||
unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL;
|
||||
|
||||
if (ring->adev->asic_type == CHIP_TOPAZ ||
|
||||
ring->adev->asic_type == CHIP_TONGA ||
|
||||
ring->adev->asic_type == CHIP_FIJI)
|
||||
/* we got a hw semaphore bug in VI TONGA, return false to switch back to sw fence wait */
|
||||
return false;
|
||||
else {
|
||||
amdgpu_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 2));
|
||||
amdgpu_ring_write(ring, lower_32_bits(addr));
|
||||
amdgpu_ring_write(ring, upper_32_bits(addr));
|
||||
amdgpu_ring_write(ring, sel);
|
||||
}
|
||||
|
||||
if (emit_wait && (ring->type == AMDGPU_RING_TYPE_GFX)) {
|
||||
/* Prevent the PFP from running ahead of the semaphore wait */
|
||||
amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
|
||||
amdgpu_ring_write(ring, 0x0);
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
|
||||
unsigned vm_id, uint64_t pd_addr)
|
||||
{
|
||||
|
@ -5145,7 +5107,7 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = {
|
|||
.parse_cs = NULL,
|
||||
.emit_ib = gfx_v8_0_ring_emit_ib_gfx,
|
||||
.emit_fence = gfx_v8_0_ring_emit_fence_gfx,
|
||||
.emit_semaphore = gfx_v8_0_ring_emit_semaphore,
|
||||
.emit_semaphore = NULL,
|
||||
.emit_vm_flush = gfx_v8_0_ring_emit_vm_flush,
|
||||
.emit_gds_switch = gfx_v8_0_ring_emit_gds_switch,
|
||||
.emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush,
|
||||
|
@ -5161,7 +5123,7 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = {
|
|||
.parse_cs = NULL,
|
||||
.emit_ib = gfx_v8_0_ring_emit_ib_compute,
|
||||
.emit_fence = gfx_v8_0_ring_emit_fence_compute,
|
||||
.emit_semaphore = gfx_v8_0_ring_emit_semaphore,
|
||||
.emit_semaphore = NULL,
|
||||
.emit_vm_flush = gfx_v8_0_ring_emit_vm_flush,
|
||||
.emit_gds_switch = gfx_v8_0_ring_emit_gds_switch,
|
||||
.emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush,
|
||||
|
|
|
@ -334,31 +334,6 @@ static void sdma_v2_4_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 se
|
|||
amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
|
||||
}
|
||||
|
||||
/**
|
||||
* sdma_v2_4_ring_emit_semaphore - emit a semaphore on the dma ring
|
||||
*
|
||||
* @ring: amdgpu_ring structure holding ring information
|
||||
* @semaphore: amdgpu semaphore object
|
||||
* @emit_wait: wait or signal semaphore
|
||||
*
|
||||
* Add a DMA semaphore packet to the ring wait on or signal
|
||||
* other rings (VI).
|
||||
*/
|
||||
static bool sdma_v2_4_ring_emit_semaphore(struct amdgpu_ring *ring,
|
||||
struct amdgpu_semaphore *semaphore,
|
||||
bool emit_wait)
|
||||
{
|
||||
u64 addr = semaphore->gpu_addr;
|
||||
u32 sig = emit_wait ? 0 : 1;
|
||||
|
||||
amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SEM) |
|
||||
SDMA_PKT_SEMAPHORE_HEADER_SIGNAL(sig));
|
||||
amdgpu_ring_write(ring, lower_32_bits(addr) & 0xfffffff8);
|
||||
amdgpu_ring_write(ring, upper_32_bits(addr));
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
/**
|
||||
* sdma_v2_4_gfx_stop - stop the gfx async dma engines
|
||||
*
|
||||
|
@ -1302,7 +1277,7 @@ static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = {
|
|||
.parse_cs = NULL,
|
||||
.emit_ib = sdma_v2_4_ring_emit_ib,
|
||||
.emit_fence = sdma_v2_4_ring_emit_fence,
|
||||
.emit_semaphore = sdma_v2_4_ring_emit_semaphore,
|
||||
.emit_semaphore = NULL,
|
||||
.emit_vm_flush = sdma_v2_4_ring_emit_vm_flush,
|
||||
.emit_hdp_flush = sdma_v2_4_ring_emit_hdp_flush,
|
||||
.test_ring = sdma_v2_4_ring_test_ring,
|
||||
|
|
|
@ -444,32 +444,6 @@ static void sdma_v3_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 se
|
|||
amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* sdma_v3_0_ring_emit_semaphore - emit a semaphore on the dma ring
|
||||
*
|
||||
* @ring: amdgpu_ring structure holding ring information
|
||||
* @semaphore: amdgpu semaphore object
|
||||
* @emit_wait: wait or signal semaphore
|
||||
*
|
||||
* Add a DMA semaphore packet to the ring wait on or signal
|
||||
* other rings (VI).
|
||||
*/
|
||||
static bool sdma_v3_0_ring_emit_semaphore(struct amdgpu_ring *ring,
|
||||
struct amdgpu_semaphore *semaphore,
|
||||
bool emit_wait)
|
||||
{
|
||||
u64 addr = semaphore->gpu_addr;
|
||||
u32 sig = emit_wait ? 0 : 1;
|
||||
|
||||
amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SEM) |
|
||||
SDMA_PKT_SEMAPHORE_HEADER_SIGNAL(sig));
|
||||
amdgpu_ring_write(ring, lower_32_bits(addr) & 0xfffffff8);
|
||||
amdgpu_ring_write(ring, upper_32_bits(addr));
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
/**
|
||||
* sdma_v3_0_gfx_stop - stop the gfx async dma engines
|
||||
*
|
||||
|
@ -1570,7 +1544,7 @@ static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = {
|
|||
.parse_cs = NULL,
|
||||
.emit_ib = sdma_v3_0_ring_emit_ib,
|
||||
.emit_fence = sdma_v3_0_ring_emit_fence,
|
||||
.emit_semaphore = sdma_v3_0_ring_emit_semaphore,
|
||||
.emit_semaphore = NULL,
|
||||
.emit_vm_flush = sdma_v3_0_ring_emit_vm_flush,
|
||||
.emit_hdp_flush = sdma_v3_0_ring_emit_hdp_flush,
|
||||
.test_ring = sdma_v3_0_ring_test_ring,
|
||||
|
|
|
@ -438,33 +438,6 @@ static void uvd_v4_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq
|
|||
amdgpu_ring_write(ring, 2);
|
||||
}
|
||||
|
||||
/**
|
||||
* uvd_v4_2_ring_emit_semaphore - emit semaphore command
|
||||
*
|
||||
* @ring: amdgpu_ring pointer
|
||||
* @semaphore: semaphore to emit commands for
|
||||
* @emit_wait: true if we should emit a wait command
|
||||
*
|
||||
* Emit a semaphore command (either wait or signal) to the UVD ring.
|
||||
*/
|
||||
static bool uvd_v4_2_ring_emit_semaphore(struct amdgpu_ring *ring,
|
||||
struct amdgpu_semaphore *semaphore,
|
||||
bool emit_wait)
|
||||
{
|
||||
uint64_t addr = semaphore->gpu_addr;
|
||||
|
||||
amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_ADDR_LOW, 0));
|
||||
amdgpu_ring_write(ring, (addr >> 3) & 0x000FFFFF);
|
||||
|
||||
amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_ADDR_HIGH, 0));
|
||||
amdgpu_ring_write(ring, (addr >> 23) & 0x000FFFFF);
|
||||
|
||||
amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CMD, 0));
|
||||
amdgpu_ring_write(ring, 0x80 | (emit_wait ? 1 : 0));
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
/**
|
||||
* uvd_v4_2_ring_test_ring - register write test
|
||||
*
|
||||
|
@ -882,7 +855,7 @@ static const struct amdgpu_ring_funcs uvd_v4_2_ring_funcs = {
|
|||
.parse_cs = amdgpu_uvd_ring_parse_cs,
|
||||
.emit_ib = uvd_v4_2_ring_emit_ib,
|
||||
.emit_fence = uvd_v4_2_ring_emit_fence,
|
||||
.emit_semaphore = uvd_v4_2_ring_emit_semaphore,
|
||||
.emit_semaphore = NULL,
|
||||
.test_ring = uvd_v4_2_ring_test_ring,
|
||||
.test_ib = uvd_v4_2_ring_test_ib,
|
||||
.insert_nop = amdgpu_ring_insert_nop,
|
||||
|
|
|
@ -482,33 +482,6 @@ static void uvd_v5_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq
|
|||
amdgpu_ring_write(ring, 2);
|
||||
}
|
||||
|
||||
/**
|
||||
* uvd_v5_0_ring_emit_semaphore - emit semaphore command
|
||||
*
|
||||
* @ring: amdgpu_ring pointer
|
||||
* @semaphore: semaphore to emit commands for
|
||||
* @emit_wait: true if we should emit a wait command
|
||||
*
|
||||
* Emit a semaphore command (either wait or signal) to the UVD ring.
|
||||
*/
|
||||
static bool uvd_v5_0_ring_emit_semaphore(struct amdgpu_ring *ring,
|
||||
struct amdgpu_semaphore *semaphore,
|
||||
bool emit_wait)
|
||||
{
|
||||
uint64_t addr = semaphore->gpu_addr;
|
||||
|
||||
amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_ADDR_LOW, 0));
|
||||
amdgpu_ring_write(ring, (addr >> 3) & 0x000FFFFF);
|
||||
|
||||
amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_ADDR_HIGH, 0));
|
||||
amdgpu_ring_write(ring, (addr >> 23) & 0x000FFFFF);
|
||||
|
||||
amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CMD, 0));
|
||||
amdgpu_ring_write(ring, 0x80 | (emit_wait ? 1 : 0));
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
/**
|
||||
* uvd_v5_0_ring_test_ring - register write test
|
||||
*
|
||||
|
@ -821,7 +794,7 @@ static const struct amdgpu_ring_funcs uvd_v5_0_ring_funcs = {
|
|||
.parse_cs = amdgpu_uvd_ring_parse_cs,
|
||||
.emit_ib = uvd_v5_0_ring_emit_ib,
|
||||
.emit_fence = uvd_v5_0_ring_emit_fence,
|
||||
.emit_semaphore = uvd_v5_0_ring_emit_semaphore,
|
||||
.emit_semaphore = NULL,
|
||||
.test_ring = uvd_v5_0_ring_test_ring,
|
||||
.test_ib = uvd_v5_0_ring_test_ib,
|
||||
.insert_nop = amdgpu_ring_insert_nop,
|
||||
|
|
|
@ -721,33 +721,6 @@ static void uvd_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq
|
|||
amdgpu_ring_write(ring, 2);
|
||||
}
|
||||
|
||||
/**
|
||||
* uvd_v6_0_ring_emit_semaphore - emit semaphore command
|
||||
*
|
||||
* @ring: amdgpu_ring pointer
|
||||
* @semaphore: semaphore to emit commands for
|
||||
* @emit_wait: true if we should emit a wait command
|
||||
*
|
||||
* Emit a semaphore command (either wait or signal) to the UVD ring.
|
||||
*/
|
||||
static bool uvd_v6_0_ring_emit_semaphore(struct amdgpu_ring *ring,
|
||||
struct amdgpu_semaphore *semaphore,
|
||||
bool emit_wait)
|
||||
{
|
||||
uint64_t addr = semaphore->gpu_addr;
|
||||
|
||||
amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_ADDR_LOW, 0));
|
||||
amdgpu_ring_write(ring, (addr >> 3) & 0x000FFFFF);
|
||||
|
||||
amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_ADDR_HIGH, 0));
|
||||
amdgpu_ring_write(ring, (addr >> 23) & 0x000FFFFF);
|
||||
|
||||
amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CMD, 0));
|
||||
amdgpu_ring_write(ring, 0x80 | (emit_wait ? 1 : 0));
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
/**
|
||||
* uvd_v6_0_ring_test_ring - register write test
|
||||
*
|
||||
|
@ -1062,7 +1035,7 @@ static const struct amdgpu_ring_funcs uvd_v6_0_ring_funcs = {
|
|||
.parse_cs = amdgpu_uvd_ring_parse_cs,
|
||||
.emit_ib = uvd_v6_0_ring_emit_ib,
|
||||
.emit_fence = uvd_v6_0_ring_emit_fence,
|
||||
.emit_semaphore = uvd_v6_0_ring_emit_semaphore,
|
||||
.emit_semaphore = NULL,
|
||||
.test_ring = uvd_v6_0_ring_test_ring,
|
||||
.test_ib = uvd_v6_0_ring_test_ib,
|
||||
.insert_nop = amdgpu_ring_insert_nop,
|
||||
|
|
|
@ -639,7 +639,7 @@ static const struct amdgpu_ring_funcs vce_v2_0_ring_funcs = {
|
|||
.parse_cs = amdgpu_vce_ring_parse_cs,
|
||||
.emit_ib = amdgpu_vce_ring_emit_ib,
|
||||
.emit_fence = amdgpu_vce_ring_emit_fence,
|
||||
.emit_semaphore = amdgpu_vce_ring_emit_semaphore,
|
||||
.emit_semaphore = NULL,
|
||||
.test_ring = amdgpu_vce_ring_test_ring,
|
||||
.test_ib = amdgpu_vce_ring_test_ib,
|
||||
.insert_nop = amdgpu_ring_insert_nop,
|
||||
|
|
|
@ -759,7 +759,7 @@ static const struct amdgpu_ring_funcs vce_v3_0_ring_funcs = {
|
|||
.parse_cs = amdgpu_vce_ring_parse_cs,
|
||||
.emit_ib = amdgpu_vce_ring_emit_ib,
|
||||
.emit_fence = amdgpu_vce_ring_emit_fence,
|
||||
.emit_semaphore = amdgpu_vce_ring_emit_semaphore,
|
||||
.emit_semaphore = NULL,
|
||||
.test_ring = amdgpu_vce_ring_test_ring,
|
||||
.test_ib = amdgpu_vce_ring_test_ib,
|
||||
.insert_nop = amdgpu_ring_insert_nop,
|
||||
|
|
Loading…
Reference in a new issue