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pinctrl: renesas: Updates for v5.14 (take two)

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- Add bias support for the R-Car H2, V2H, E2, V3M, and V3H, and
     RZ/G1C, RZ/G1H, and RZ/G1E SoCs.
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Merge tag 'renesas-pinctrl-for-v5.14-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel

pinctrl: renesas: Updates for v5.14 (take two)

  - Add bias support for the R-Car H2, V2H, E2, V3M, and V3H, and
    RZ/G1C, RZ/G1H, and RZ/G1E SoCs.
This commit is contained in:
Linus Walleij 2021-06-12 02:04:12 +02:00
commit 2f792ec782
6 changed files with 1844 additions and 80 deletions
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346
drivers/pinctrl/renesas/pfc-r8a77470.c
View file

@ -11,46 +11,56 @@
#include "sh_pfc.h"
#define CPU_ALL_GP(fn, sfx) \
PORT_GP_4(0, fn, sfx), \
PORT_GP_1(0, 4, fn, sfx), \
PORT_GP_CFG_1(0, 5, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
PORT_GP_CFG_1(0, 6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
PORT_GP_CFG_1(0, 7, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
PORT_GP_CFG_1(0, 8, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
PORT_GP_CFG_1(0, 9, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
PORT_GP_CFG_1(0, 10, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
PORT_GP_1(0, 11, fn, sfx), \
PORT_GP_1(0, 12, fn, sfx), \
PORT_GP_CFG_1(0, 13, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
PORT_GP_CFG_1(0, 14, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
PORT_GP_CFG_1(0, 15, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
PORT_GP_CFG_1(0, 16, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
PORT_GP_CFG_1(0, 17, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
PORT_GP_CFG_1(0, 18, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
PORT_GP_CFG_1(0, 19, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
PORT_GP_CFG_1(0, 20, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
PORT_GP_CFG_1(0, 21, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
PORT_GP_CFG_1(0, 22, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
PORT_GP_23(1, fn, sfx), \
PORT_GP_32(2, fn, sfx), \
PORT_GP_17(3, fn, sfx), \
PORT_GP_1(3, 27, fn, sfx), \
PORT_GP_1(3, 28, fn, sfx), \
PORT_GP_1(3, 29, fn, sfx), \
PORT_GP_14(4, fn, sfx), \
PORT_GP_CFG_1(4, 14, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
PORT_GP_CFG_1(4, 15, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
PORT_GP_CFG_1(4, 16, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
PORT_GP_CFG_1(4, 17, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
PORT_GP_CFG_1(4, 18, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
PORT_GP_CFG_1(4, 19, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
PORT_GP_1(4, 20, fn, sfx), \
PORT_GP_1(4, 21, fn, sfx), \
PORT_GP_1(4, 22, fn, sfx), \
PORT_GP_1(4, 23, fn, sfx), \
PORT_GP_1(4, 24, fn, sfx), \
PORT_GP_1(4, 25, fn, sfx), \
PORT_GP_32(5, fn, sfx)
PORT_GP_CFG_4(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(0, 4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(0, 5, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(0, 6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(0, 7, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(0, 8, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(0, 9, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(0, 10, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(0, 11, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(0, 12, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(0, 13, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(0, 14, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(0, 15, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(0, 16, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(0, 17, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(0, 18, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(0, 19, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(0, 20, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(0, 21, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(0, 22, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_23(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_32(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(3, 27, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(3, 28, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(3, 29, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_14(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(4, 14, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(4, 15, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(4, 16, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(4, 17, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(4, 18, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(4, 19, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(4, 20, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(4, 21, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(4, 22, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(4, 23, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(4, 24, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(4, 25, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_32(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP)
#define CPU_ALL_NOGP(fn) \
PIN_NOGP_CFG(ASEBRK_N_ACK, "ASEBRK#/ACK", fn, SH_PFC_PIN_CFG_PULL_DOWN), \
PIN_NOGP_CFG(NMI, "NMI", fn, SH_PFC_PIN_CFG_PULL_UP), \
PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, SH_PFC_PIN_CFG_PULL_UP), \
PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP), \
PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP), \
PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_PULL_UP), \
PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP), \
PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP)
enum {
PINMUX_RESERVED = 0,
@ -1121,8 +1131,17 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP17_27_24, VI0_VSYNC_N),
};
/*
* Pins not associated with a GPIO port.
*/
enum {
GP_ASSIGN_LAST(),
NOGP_ALL(),
};
static const struct sh_pfc_pin pinmux_pins[] = {
PINMUX_GPIO_GP_ALL(),
PINMUX_NOGP_ALL(),
};
/* - AVB -------------------------------------------------------------------- */
@ -3420,8 +3439,254 @@ static int r8a77470_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
return bit;
}
static const struct pinmux_bias_reg pinmux_bias_regs[] = {
{ PINMUX_BIAS_REG("PUPR0", 0xe6060100, "N/A", 0) {
/* PUPR0 pull-up pins */
[ 0] = RCAR_GP_PIN(1, 0), /* D0 */
[ 1] = RCAR_GP_PIN(0, 22), /* MMC0_D7 */
[ 2] = RCAR_GP_PIN(0, 21), /* MMC0_D6 */
[ 3] = RCAR_GP_PIN(0, 20), /* MMC0_D5 */
[ 4] = RCAR_GP_PIN(0, 19), /* MMC0_D4 */
[ 5] = RCAR_GP_PIN(0, 18), /* MMC0_D3 */
[ 6] = RCAR_GP_PIN(0, 17), /* MMC0_D2 */
[ 7] = RCAR_GP_PIN(0, 16), /* MMC0_D1 */
[ 8] = RCAR_GP_PIN(0, 15), /* MMC0_D0 */
[ 9] = RCAR_GP_PIN(0, 14), /* MMC0_CMD */
[10] = RCAR_GP_PIN(0, 13), /* MMC0_CLK */
[11] = RCAR_GP_PIN(0, 12), /* SD0_WP */
[12] = RCAR_GP_PIN(0, 11), /* SD0_CD */
[13] = RCAR_GP_PIN(0, 10), /* SD0_DAT3 */
[14] = RCAR_GP_PIN(0, 9), /* SD0_DAT2 */
[15] = RCAR_GP_PIN(0, 8), /* SD0_DAT1 */
[16] = RCAR_GP_PIN(0, 7), /* SD0_DAT0 */
[17] = RCAR_GP_PIN(0, 6), /* SD0_CMD */
[18] = RCAR_GP_PIN(0, 5), /* SD0_CLK */
[19] = RCAR_GP_PIN(0, 4), /* CLKOUT */
[20] = PIN_NMI, /* NMI */
[21] = RCAR_GP_PIN(0, 3), /* USB1_OVC */
[22] = RCAR_GP_PIN(0, 2), /* USB1_PWEN */
[23] = RCAR_GP_PIN(0, 1), /* USB0_OVC */
[24] = RCAR_GP_PIN(0, 0), /* USB0_PWEN */
[25] = SH_PFC_PIN_NONE,
[26] = PIN_TDO, /* TDO */
[27] = PIN_TDI, /* TDI */
[28] = PIN_TMS, /* TMS */
[29] = PIN_TCK, /* TCK */
[30] = PIN_TRST_N, /* TRST# */
[31] = PIN_PRESETOUT_N, /* PRESETOUT# */
} },
{ PINMUX_BIAS_REG("N/A", 0, "PUPR0", 0xe6060100) {
/* PUPR0 pull-down pins */
[ 0] = SH_PFC_PIN_NONE,
[ 1] = SH_PFC_PIN_NONE,
[ 2] = SH_PFC_PIN_NONE,
[ 3] = SH_PFC_PIN_NONE,
[ 4] = SH_PFC_PIN_NONE,
[ 5] = SH_PFC_PIN_NONE,
[ 6] = SH_PFC_PIN_NONE,
[ 7] = SH_PFC_PIN_NONE,
[ 8] = SH_PFC_PIN_NONE,
[ 9] = SH_PFC_PIN_NONE,
[10] = SH_PFC_PIN_NONE,
[11] = SH_PFC_PIN_NONE,
[12] = SH_PFC_PIN_NONE,
[13] = SH_PFC_PIN_NONE,
[14] = SH_PFC_PIN_NONE,
[15] = SH_PFC_PIN_NONE,
[16] = SH_PFC_PIN_NONE,
[17] = SH_PFC_PIN_NONE,
[18] = SH_PFC_PIN_NONE,
[19] = SH_PFC_PIN_NONE,
[20] = SH_PFC_PIN_NONE,
[21] = SH_PFC_PIN_NONE,
[22] = SH_PFC_PIN_NONE,
[23] = SH_PFC_PIN_NONE,
[24] = SH_PFC_PIN_NONE,
[25] = PIN_ASEBRK_N_ACK, /* ASEBRK#/ACK */
[26] = SH_PFC_PIN_NONE,
[27] = SH_PFC_PIN_NONE,
[28] = SH_PFC_PIN_NONE,
[29] = SH_PFC_PIN_NONE,
[30] = SH_PFC_PIN_NONE,
[31] = SH_PFC_PIN_NONE,
} },
{ PINMUX_BIAS_REG("PUPR1", 0xe6060104, "N/A", 0) {
[ 0] = RCAR_GP_PIN(2, 9), /* DU0_DG1 */
[ 1] = RCAR_GP_PIN(2, 8), /* DU0_DG0 */
[ 2] = RCAR_GP_PIN(2, 7), /* DU0_DR7 */
[ 3] = RCAR_GP_PIN(2, 6), /* DU0_DR6 */
[ 4] = RCAR_GP_PIN(2, 5), /* DU0_DR5 */
[ 5] = RCAR_GP_PIN(2, 4), /* DU0_DR4 */
[ 6] = RCAR_GP_PIN(2, 3), /* DU0_DR3 */
[ 7] = RCAR_GP_PIN(2, 2), /* DU0_DR2 */
[ 8] = RCAR_GP_PIN(2, 1), /* DU0_DR1 */
[ 9] = RCAR_GP_PIN(2, 0), /* DU0_DR0 */
[10] = RCAR_GP_PIN(1, 22), /* EX_WAIT0 */
[11] = RCAR_GP_PIN(1, 21), /* QSPI0_SSL */
[12] = RCAR_GP_PIN(1, 20), /* QSPI0_IO3 */
[13] = RCAR_GP_PIN(1, 19), /* QSPI0_IO2 */
[14] = RCAR_GP_PIN(1, 18), /* QSPI0_MISO/QSPI0_IO1 */
[15] = RCAR_GP_PIN(1, 17), /* QSPI0_MOSI/QSPI0_IO0 */
[16] = RCAR_GP_PIN(1, 16), /* QSPI0_SPCLK */
[17] = RCAR_GP_PIN(1, 15), /* D15 */
[18] = RCAR_GP_PIN(1, 14), /* D14 */
[19] = RCAR_GP_PIN(1, 13), /* D13 */
[20] = RCAR_GP_PIN(1, 12), /* D12 */
[21] = RCAR_GP_PIN(1, 11), /* D11 */
[22] = RCAR_GP_PIN(1, 10), /* D10 */
[23] = RCAR_GP_PIN(1, 9), /* D9 */
[24] = RCAR_GP_PIN(1, 8), /* D8 */
[25] = RCAR_GP_PIN(1, 7), /* D7 */
[26] = RCAR_GP_PIN(1, 6), /* D6 */
[27] = RCAR_GP_PIN(1, 5), /* D5 */
[28] = RCAR_GP_PIN(1, 4), /* D4 */
[29] = RCAR_GP_PIN(1, 3), /* D3 */
[30] = RCAR_GP_PIN(1, 2), /* D2 */
[31] = RCAR_GP_PIN(1, 1), /* D1 */
} },
{ PINMUX_BIAS_REG("PUPR2", 0xe6060108, "N/A", 0) {
[ 0] = RCAR_GP_PIN(3, 9), /* VI1_CLKENB */
[ 1] = RCAR_GP_PIN(3, 8), /* VI1_DATA7 */
[ 2] = RCAR_GP_PIN(3, 7), /* VI1_DATA6 */
[ 3] = RCAR_GP_PIN(3, 6), /* VI1_DATA5 */
[ 4] = RCAR_GP_PIN(3, 5), /* VI1_DATA4 */
[ 5] = RCAR_GP_PIN(3, 4), /* VI1_DATA3 */
[ 6] = RCAR_GP_PIN(3, 3), /* VI1_DATA2 */
[ 7] = RCAR_GP_PIN(3, 2), /* VI1_DATA1 */
[ 8] = RCAR_GP_PIN(3, 1), /* VI1_DATA0 */
[ 9] = RCAR_GP_PIN(3, 0), /* VI1_CLK */
[10] = RCAR_GP_PIN(2, 31), /* DU0_CDE */
[11] = RCAR_GP_PIN(2, 30), /* DU0_DISP */
[12] = RCAR_GP_PIN(2, 29), /* DU0_EXODDF/DU0_ODDF_DISP_CDE */
[13] = RCAR_GP_PIN(2, 28), /* DU0_EXVSYNC/DU0_VSYNC */
[14] = RCAR_GP_PIN(2, 27), /* DU0_EXHSYNC/DU0_HSYNC */
[15] = RCAR_GP_PIN(2, 26), /* DU0_DOTCLKOUT1 */
[16] = RCAR_GP_PIN(2, 25), /* DU0_DOTCLKOUT0 */
[17] = RCAR_GP_PIN(2, 24), /* DU0_DOTCLKIN */
[18] = RCAR_GP_PIN(2, 23), /* DU0_DB7 */
[19] = RCAR_GP_PIN(2, 22), /* DU0_DB6 */
[20] = RCAR_GP_PIN(2, 21), /* DU0_DB5 */
[21] = RCAR_GP_PIN(2, 20), /* DU0_DB4 */
[22] = RCAR_GP_PIN(2, 19), /* DU0_DB3 */
[23] = RCAR_GP_PIN(2, 18), /* DU0_DB2 */
[24] = RCAR_GP_PIN(2, 17), /* DU0_DB1 */
[25] = RCAR_GP_PIN(2, 16), /* DU0_DB0 */
[26] = RCAR_GP_PIN(2, 15), /* DU0_DG7 */
[27] = RCAR_GP_PIN(2, 14), /* DU0_DG6 */
[28] = RCAR_GP_PIN(2, 13), /* DU0_DG5 */
[29] = RCAR_GP_PIN(2, 12), /* DU0_DG4 */
[30] = RCAR_GP_PIN(2, 11), /* DU0_DG3 */
[31] = RCAR_GP_PIN(2, 10), /* DU0_DG2 */
} },
{ PINMUX_BIAS_REG("PUPR3", 0xe606010c, "N/A", 0) {
[ 0] = RCAR_GP_PIN(4, 21), /* SD2_WP */
[ 1] = RCAR_GP_PIN(4, 20), /* SD2_CD */
[ 2] = RCAR_GP_PIN(4, 19), /* SD2_DAT3 */
[ 3] = RCAR_GP_PIN(4, 18), /* SD2_DAT2 */
[ 4] = RCAR_GP_PIN(4, 17), /* SD2_DAT1 */
[ 5] = RCAR_GP_PIN(4, 16), /* SD2_DAT0 */
[ 6] = RCAR_GP_PIN(4, 15), /* SD2_CMD */
[ 7] = RCAR_GP_PIN(4, 14), /* SD2_CLK */
[ 8] = RCAR_GP_PIN(4, 13), /* HRTS1#_A */
[ 9] = RCAR_GP_PIN(4, 12), /* HCTS1#_A */
[10] = RCAR_GP_PIN(4, 11), /* HTX1_A */
[11] = RCAR_GP_PIN(4, 10), /* HRX1_A */
[12] = RCAR_GP_PIN(4, 9), /* MSIOF0_SS2_A */
[13] = RCAR_GP_PIN(4, 8), /* MSIOF0_SS1_A */
[14] = RCAR_GP_PIN(4, 7), /* MSIOF0_SYNC_A */
[15] = RCAR_GP_PIN(4, 6), /* MSIOF0_SCK_A */
[16] = RCAR_GP_PIN(4, 5), /* MSIOF0_TXD_A */
[17] = RCAR_GP_PIN(4, 4), /* MSIOF0_RXD_A */
[18] = RCAR_GP_PIN(4, 3), /* SDA1_A */
[19] = RCAR_GP_PIN(4, 2), /* SCL1_A */
[20] = RCAR_GP_PIN(4, 1), /* SDA0_A */
[21] = RCAR_GP_PIN(4, 0), /* SCL0_A */
[22] = RCAR_GP_PIN(3, 29), /* AVB_TXD5 */
[23] = RCAR_GP_PIN(3, 28), /* AVB_TXD4 */
[24] = RCAR_GP_PIN(3, 27), /* AVB_TXD3 */
[25] = RCAR_GP_PIN(3, 16), /* VI1_DATA11 */
[26] = RCAR_GP_PIN(3, 15), /* VI1_DATA10 */
[27] = RCAR_GP_PIN(3, 14), /* VI1_DATA9 */
[28] = RCAR_GP_PIN(3, 13), /* VI1_DATA8 */
[29] = RCAR_GP_PIN(3, 12), /* VI1_VSYNC# */
[30] = RCAR_GP_PIN(3, 11), /* VI1_HSYNC# */
[31] = RCAR_GP_PIN(3, 10), /* VI1_FIELD */
} },
{ PINMUX_BIAS_REG("PUPR4", 0xe6060110, "N/A", 0) {
[ 0] = RCAR_GP_PIN(5, 27), /* SSI_SDATA9_A */
[ 1] = RCAR_GP_PIN(5, 26), /* SSI_WS9_A */
[ 2] = RCAR_GP_PIN(5, 25), /* SSI_SCK9_A */
[ 3] = RCAR_GP_PIN(5, 24), /* SSI_SDATA2_A */
[ 4] = RCAR_GP_PIN(5, 23), /* SSI_WS2_A */
[ 5] = RCAR_GP_PIN(5, 22), /* SSI_SCK2_A */
[ 6] = RCAR_GP_PIN(5, 21), /* SSI_SDATA1_A */
[ 7] = RCAR_GP_PIN(5, 20), /* SSI_WS1_A */
[ 8] = RCAR_GP_PIN(5, 19), /* SSI_SDATA8_A */
[ 9] = RCAR_GP_PIN(5, 18), /* SSI_SCK1_A */
[10] = RCAR_GP_PIN(5, 17), /* SSI_SDATA4_A */
[11] = RCAR_GP_PIN(5, 16), /* SSI_WS4_A */
[12] = RCAR_GP_PIN(5, 15), /* SSI_SCK4_A */
[13] = RCAR_GP_PIN(5, 14), /* SSI_SDATA3 */
[14] = RCAR_GP_PIN(5, 13), /* SSI_WS34 */
[15] = RCAR_GP_PIN(5, 12), /* SSI_SCK34 */
[16] = RCAR_GP_PIN(5, 11), /* SSI_SDATA0_A */
[17] = RCAR_GP_PIN(5, 10), /* SSI_WS0129_A */
[18] = RCAR_GP_PIN(5, 9), /* SSI_SCK0129_A */
[19] = RCAR_GP_PIN(5, 8), /* SSI_SDATA7_A */
[20] = RCAR_GP_PIN(5, 7), /* SSI_WS78_A */
[21] = RCAR_GP_PIN(5, 6), /* SSI_SCK78_A */
[22] = RCAR_GP_PIN(5, 5), /* SSI_SDATA6_A */
[23] = RCAR_GP_PIN(5, 4), /* SSI_WS6_A */
[24] = RCAR_GP_PIN(5, 3), /* SSI_SCK6_A */
[25] = RCAR_GP_PIN(5, 2), /* SSI_SDATA5_A */
[26] = RCAR_GP_PIN(5, 1), /* SSI_WS5_A */
[27] = RCAR_GP_PIN(5, 0), /* SSI_SCK5_A */
[28] = RCAR_GP_PIN(4, 25), /* SDA2_A */
[29] = RCAR_GP_PIN(4, 24), /* SCL2_A */
[30] = RCAR_GP_PIN(4, 23), /* TX3_A */
[31] = RCAR_GP_PIN(4, 22), /* RX3_A */
} },
{ PINMUX_BIAS_REG("PUPR5", 0xe6060114, "N/A", 0) {
[ 0] = SH_PFC_PIN_NONE,
[ 1] = SH_PFC_PIN_NONE,
[ 2] = SH_PFC_PIN_NONE,
[ 3] = SH_PFC_PIN_NONE,
[ 4] = SH_PFC_PIN_NONE,
[ 5] = SH_PFC_PIN_NONE,
[ 6] = SH_PFC_PIN_NONE,
[ 7] = SH_PFC_PIN_NONE,
[ 8] = SH_PFC_PIN_NONE,
[ 9] = SH_PFC_PIN_NONE,
[10] = SH_PFC_PIN_NONE,
[11] = SH_PFC_PIN_NONE,
[12] = SH_PFC_PIN_NONE,
[13] = SH_PFC_PIN_NONE,
[14] = SH_PFC_PIN_NONE,
[15] = SH_PFC_PIN_NONE,
[16] = SH_PFC_PIN_NONE,
[17] = SH_PFC_PIN_NONE,
[18] = SH_PFC_PIN_NONE,
[19] = SH_PFC_PIN_NONE,
[20] = SH_PFC_PIN_NONE,
[21] = SH_PFC_PIN_NONE,
[22] = SH_PFC_PIN_NONE,
[23] = SH_PFC_PIN_NONE,
[24] = SH_PFC_PIN_NONE,
[25] = SH_PFC_PIN_NONE,
[26] = SH_PFC_PIN_NONE,
[27] = SH_PFC_PIN_NONE,
[28] = RCAR_GP_PIN(5, 31), /* AUDIO_CLKOUT_A */
[29] = RCAR_GP_PIN(5, 30), /* AUDIO_CLKC_A */
[30] = RCAR_GP_PIN(5, 29), /* AUDIO_CLKB_A */
[31] = RCAR_GP_PIN(5, 28), /* AUDIO_CLKA_A */
} },
{ /* sentinel */ }
};
static const struct sh_pfc_soc_operations r8a77470_pinmux_ops = {
.pin_to_pocctrl = r8a77470_pin_to_pocctrl,
.get_bias = rcar_pinmux_get_bias,
.set_bias = rcar_pinmux_set_bias,
};
#ifdef CONFIG_PINCTRL_PFC_R8A77470
@ -3440,6 +3705,7 @@ const struct sh_pfc_soc_info r8a77470_pinmux_info = {
.nr_functions = ARRAY_SIZE(pinmux_functions),
.cfg_regs = pinmux_config_regs,
.bias_regs = pinmux_bias_regs,
.pinmux_data = pinmux_data,
.pinmux_data_size = ARRAY_SIZE(pinmux_data),

301
drivers/pinctrl/renesas/pfc-r8a7790.c
View file

@ -21,18 +21,23 @@
* which case they support both 3.3V and 1.8V signalling.
*/
#define CPU_ALL_GP(fn, sfx) \
PORT_GP_32(0, fn, sfx), \
PORT_GP_30(1, fn, sfx), \
PORT_GP_30(2, fn, sfx), \
PORT_GP_CFG_32(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
PORT_GP_32(4, fn, sfx), \
PORT_GP_32(5, fn, sfx)
PORT_GP_CFG_32(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_30(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_30(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_32(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_32(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_32(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP)
#define CPU_ALL_NOGP(fn) \
PIN_NOGP_CFG(ASEBRK_N_ACK, "ASEBRK#/ACK", fn, SH_PFC_PIN_CFG_PULL_DOWN), \
PIN_NOGP(IIC0_SDA, "AF15", fn), \
PIN_NOGP(IIC0_SCL, "AG15", fn), \
PIN_NOGP(IIC3_SDA, "AH15", fn), \
PIN_NOGP(IIC3_SCL, "AJ15", fn)
PIN_NOGP(IIC3_SCL, "AJ15", fn), \
PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP), \
PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP), \
PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP), \
PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP)
enum {
PINMUX_RESERVED = 0,
@ -5992,6 +5997,284 @@ static int r8a7790_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *poc
return 31 - (pin & 0x1f);
}
static const struct pinmux_bias_reg pinmux_bias_regs[] = {
{ PINMUX_BIAS_REG("PUPR0", 0xe6060100, "N/A", 0) {
[ 0] = RCAR_GP_PIN(0, 16), /* A0 */
[ 1] = RCAR_GP_PIN(0, 17), /* A1 */
[ 2] = RCAR_GP_PIN(0, 18), /* A2 */
[ 3] = RCAR_GP_PIN(0, 19), /* A3 */
[ 4] = RCAR_GP_PIN(0, 20), /* A4 */
[ 5] = RCAR_GP_PIN(0, 21), /* A5 */
[ 6] = RCAR_GP_PIN(0, 22), /* A6 */
[ 7] = RCAR_GP_PIN(0, 23), /* A7 */
[ 8] = RCAR_GP_PIN(0, 24), /* A8 */
[ 9] = RCAR_GP_PIN(0, 25), /* A9 */
[10] = RCAR_GP_PIN(0, 26), /* A10 */
[11] = RCAR_GP_PIN(0, 27), /* A11 */
[12] = RCAR_GP_PIN(0, 28), /* A12 */
[13] = RCAR_GP_PIN(0, 29), /* A13 */
[14] = RCAR_GP_PIN(0, 30), /* A14 */
[15] = RCAR_GP_PIN(0, 31), /* A15 */
[16] = RCAR_GP_PIN(1, 0), /* A16 */
[17] = RCAR_GP_PIN(1, 1), /* A17 */
[18] = RCAR_GP_PIN(1, 2), /* A18 */
[19] = RCAR_GP_PIN(1, 3), /* A19 */
[20] = RCAR_GP_PIN(1, 4), /* A20 */
[21] = RCAR_GP_PIN(1, 5), /* A21 */
[22] = RCAR_GP_PIN(1, 6), /* A22 */
[23] = RCAR_GP_PIN(1, 7), /* A23 */
[24] = RCAR_GP_PIN(1, 8), /* A24 */
[25] = RCAR_GP_PIN(1, 9), /* A25 */
[26] = RCAR_GP_PIN(1, 12), /* EX_CS0# */
[27] = RCAR_GP_PIN(1, 13), /* EX_CS1# */
[28] = RCAR_GP_PIN(1, 14), /* EX_CS2# */
[29] = RCAR_GP_PIN(1, 15), /* EX_CS3# */
[30] = RCAR_GP_PIN(1, 16), /* EX_CS4# */
[31] = RCAR_GP_PIN(1, 17), /* EX_CS5# */
} },
{ PINMUX_BIAS_REG("PUPR1", 0xe6060104, "N/A", 0) {
/* PUPR1 pull-up pins */
[ 0] = RCAR_GP_PIN(1, 18), /* BS# */
[ 1] = RCAR_GP_PIN(1, 19), /* RD# */
[ 2] = RCAR_GP_PIN(1, 20), /* RD/WR# */
[ 3] = RCAR_GP_PIN(1, 21), /* WE0# */
[ 4] = RCAR_GP_PIN(1, 22), /* WE1# */
[ 5] = RCAR_GP_PIN(1, 23), /* EX_WAIT0 */
[ 6] = RCAR_GP_PIN(5, 24), /* AVS1 */
[ 7] = RCAR_GP_PIN(5, 25), /* AVS2 */
[ 8] = RCAR_GP_PIN(1, 10), /* CS0# */
[ 9] = RCAR_GP_PIN(1, 11), /* CS1#/A26 */
[10] = PIN_TRST_N, /* TRST# */
[11] = PIN_TCK, /* TCK */
[12] = PIN_TMS, /* TMS */
[13] = PIN_TDI, /* TDI */
[14] = SH_PFC_PIN_NONE,
[15] = SH_PFC_PIN_NONE,
[16] = RCAR_GP_PIN(0, 0), /* D0 */
[17] = RCAR_GP_PIN(0, 1), /* D1 */
[18] = RCAR_GP_PIN(0, 2), /* D2 */
[19] = RCAR_GP_PIN(0, 3), /* D3 */
[20] = RCAR_GP_PIN(0, 4), /* D4 */
[21] = RCAR_GP_PIN(0, 5), /* D5 */
[22] = RCAR_GP_PIN(0, 6), /* D6 */
[23] = RCAR_GP_PIN(0, 7), /* D7 */
[24] = RCAR_GP_PIN(0, 8), /* D8 */
[25] = RCAR_GP_PIN(0, 9), /* D9 */
[26] = RCAR_GP_PIN(0, 10), /* D10 */
[27] = RCAR_GP_PIN(0, 11), /* D11 */
[28] = RCAR_GP_PIN(0, 12), /* D12 */
[29] = RCAR_GP_PIN(0, 13), /* D13 */
[30] = RCAR_GP_PIN(0, 14), /* D14 */
[31] = RCAR_GP_PIN(0, 15), /* D15 */
} },
{ PINMUX_BIAS_REG("N/A", 0, "PUPR1", 0xe6060104) {
/* PUPR1 pull-down pins */
[ 0] = SH_PFC_PIN_NONE,
[ 1] = SH_PFC_PIN_NONE,
[ 2] = SH_PFC_PIN_NONE,
[ 3] = SH_PFC_PIN_NONE,
[ 4] = SH_PFC_PIN_NONE,
[ 5] = SH_PFC_PIN_NONE,
[ 6] = SH_PFC_PIN_NONE,
[ 7] = SH_PFC_PIN_NONE,
[ 8] = SH_PFC_PIN_NONE,
[ 9] = SH_PFC_PIN_NONE,
[10] = SH_PFC_PIN_NONE,
[11] = SH_PFC_PIN_NONE,
[12] = SH_PFC_PIN_NONE,
[13] = SH_PFC_PIN_NONE,
[14] = SH_PFC_PIN_NONE,
[15] = PIN_ASEBRK_N_ACK, /* ASEBRK#/ACK */
[16] = SH_PFC_PIN_NONE,
[17] = SH_PFC_PIN_NONE,
[18] = SH_PFC_PIN_NONE,
[19] = SH_PFC_PIN_NONE,
[20] = SH_PFC_PIN_NONE,
[21] = SH_PFC_PIN_NONE,
[22] = SH_PFC_PIN_NONE,
[23] = SH_PFC_PIN_NONE,
[24] = SH_PFC_PIN_NONE,
[25] = SH_PFC_PIN_NONE,
[26] = SH_PFC_PIN_NONE,
[27] = SH_PFC_PIN_NONE,
[28] = SH_PFC_PIN_NONE,
[29] = SH_PFC_PIN_NONE,
[30] = SH_PFC_PIN_NONE,
[31] = SH_PFC_PIN_NONE,
} },
{ PINMUX_BIAS_REG("PUPR2", 0xe6060108, "N/A", 0) {
[ 0] = RCAR_GP_PIN(5, 28), /* DU_DOTCLKIN2 */
[ 1] = SH_PFC_PIN_NONE,
[ 2] = SH_PFC_PIN_NONE,
[ 3] = SH_PFC_PIN_NONE,
[ 4] = SH_PFC_PIN_NONE,
[ 5] = RCAR_GP_PIN(2, 0), /* VI0_CLK */
[ 6] = RCAR_GP_PIN(2, 1), /* VI0_DATA0_VI0_B0 */
[ 7] = RCAR_GP_PIN(2, 2), /* VI0_DATA1_VI0_B1 */
[ 8] = RCAR_GP_PIN(2, 3), /* VI0_DATA2_VI0_B2 */
[ 9] = RCAR_GP_PIN(2, 4), /* VI0_DATA3_VI0_B3 */
[10] = RCAR_GP_PIN(2, 5), /* VI0_DATA4_VI0_B4 */
[11] = RCAR_GP_PIN(2, 6), /* VI0_DATA5_VI0_B5 */
[12] = RCAR_GP_PIN(2, 7), /* VI0_DATA6_VI0_B6 */
[13] = RCAR_GP_PIN(2, 8), /* VI0_DATA7_VI0_B7 */
[14] = RCAR_GP_PIN(2, 9), /* VI1_CLK */
[15] = RCAR_GP_PIN(2, 10), /* VI1_DATA0_VI1_B0 */
[16] = RCAR_GP_PIN(2, 11), /* VI1_DATA1_VI1_B1 */
[17] = RCAR_GP_PIN(2, 12), /* VI1_DATA2_VI1_B2 */
[18] = RCAR_GP_PIN(2, 13), /* VI1_DATA3_VI1_B3 */
[19] = RCAR_GP_PIN(2, 14), /* VI1_DATA4_VI1_B4 */
[20] = RCAR_GP_PIN(2, 15), /* VI1_DATA5_VI1_B5 */
[21] = RCAR_GP_PIN(2, 16), /* VI1_DATA6_VI1_B6 */
[22] = RCAR_GP_PIN(2, 17), /* VI1_DATA7_VI1_B7 */
[23] = RCAR_GP_PIN(5, 27), /* DU_DOTCLKIN1 */
[24] = SH_PFC_PIN_NONE,
[25] = SH_PFC_PIN_NONE,
[26] = SH_PFC_PIN_NONE,
[27] = RCAR_GP_PIN(4, 0), /* MLB_CLK */
[28] = RCAR_GP_PIN(4, 1), /* MLB_SIG */
[29] = RCAR_GP_PIN(4, 2), /* MLB_DAT */
[30] = SH_PFC_PIN_NONE,
[31] = RCAR_GP_PIN(5, 26), /* DU_DOTCLKIN0 */
} },
{ PINMUX_BIAS_REG("PUPR3", 0xe606010c, "N/A", 0) {
[ 0] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
[ 1] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
[ 2] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
[ 3] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */
[ 4] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */
[ 5] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */
[ 6] = RCAR_GP_PIN(3, 6), /* SD0_CD */
[ 7] = RCAR_GP_PIN(3, 7), /* SD0_WP */
[ 8] = RCAR_GP_PIN(3, 8), /* SD1_CLK */
[ 9] = RCAR_GP_PIN(3, 9), /* SD1_CMD */
[10] = RCAR_GP_PIN(3, 10), /* SD1_DAT0 */
[11] = RCAR_GP_PIN(3, 11), /* SD1_DAT1 */
[12] = RCAR_GP_PIN(3, 12), /* SD1_DAT2 */
[13] = RCAR_GP_PIN(3, 13), /* SD1_DAT3 */
[14] = RCAR_GP_PIN(3, 14), /* SD1_CD */
[15] = RCAR_GP_PIN(3, 15), /* SD1_WP */
[16] = RCAR_GP_PIN(3, 16), /* SD2_CLK */
[17] = RCAR_GP_PIN(3, 17), /* SD2_CMD */
[18] = RCAR_GP_PIN(3, 18), /* SD2_DAT0 */
[19] = RCAR_GP_PIN(3, 19), /* SD2_DAT1 */
[20] = RCAR_GP_PIN(3, 20), /* SD2_DAT2 */
[21] = RCAR_GP_PIN(3, 21), /* SD2_DAT3 */
[22] = RCAR_GP_PIN(3, 22), /* SD2_CD */
[23] = RCAR_GP_PIN(3, 23), /* SD2_WP */
[24] = RCAR_GP_PIN(3, 24), /* SD3_CLK */
[25] = RCAR_GP_PIN(3, 25), /* SD3_CMD */
[26] = RCAR_GP_PIN(3, 26), /* SD3_DAT0 */
[27] = RCAR_GP_PIN(3, 27), /* SD3_DAT1 */
[28] = RCAR_GP_PIN(3, 28), /* SD3_DAT2 */
[29] = RCAR_GP_PIN(3, 29), /* SD3_DAT3 */
[30] = RCAR_GP_PIN(3, 30), /* SD3_CD */
[31] = RCAR_GP_PIN(3, 31), /* SD3_WP */
} },
{ PINMUX_BIAS_REG("PUPR4", 0xe6060110, "N/A", 0) {
[ 0] = RCAR_GP_PIN(4, 3), /* SSI_SCK0129 */
[ 1] = RCAR_GP_PIN(4, 4), /* SSI_WS0129 */
[ 2] = RCAR_GP_PIN(4, 5), /* SSI_SDATA0 */
[ 3] = RCAR_GP_PIN(4, 6), /* SSI_SDATA1 */
[ 4] = RCAR_GP_PIN(4, 7), /* SSI_SDATA2 */
[ 5] = RCAR_GP_PIN(4, 8), /* SSI_SCK34 */
[ 6] = RCAR_GP_PIN(4, 9), /* SSI_WS34 */
[ 7] = RCAR_GP_PIN(4, 10), /* SSI_SDATA3 */
[ 8] = RCAR_GP_PIN(4, 11), /* SSI_SCK4 */
[ 9] = RCAR_GP_PIN(4, 12), /* SSI_WS4 */
[10] = RCAR_GP_PIN(4, 13), /* SSI_SDATA4 */
[11] = RCAR_GP_PIN(4, 14), /* SSI_SCK5 */
[12] = RCAR_GP_PIN(4, 15), /* SSI_WS5 */
[13] = RCAR_GP_PIN(4, 16), /* SSI_SDATA5 */
[14] = RCAR_GP_PIN(4, 17), /* SSI_SCK6 */
[15] = RCAR_GP_PIN(4, 18), /* SSI_WS6 */
[16] = RCAR_GP_PIN(4, 19), /* SSI_SDATA6 */
[17] = RCAR_GP_PIN(4, 20), /* SSI_SCK78 */
[18] = RCAR_GP_PIN(4, 21), /* SSI_WS78 */
[19] = RCAR_GP_PIN(4, 22), /* SSI_SDATA7 */
[20] = RCAR_GP_PIN(4, 23), /* SSI_SDATA8 */
[21] = RCAR_GP_PIN(4, 24), /* SSI_SDATA9 */
[22] = RCAR_GP_PIN(4, 25), /* AUDIO_CLKA */
[23] = RCAR_GP_PIN(4, 26), /* AUDIO_CLKB */
[24] = RCAR_GP_PIN(1, 24), /* DREQ0 */
[25] = RCAR_GP_PIN(1, 25), /* DACK0 */
[26] = RCAR_GP_PIN(1, 26), /* DREQ1 */
[27] = RCAR_GP_PIN(1, 27), /* DACK1 */
[28] = RCAR_GP_PIN(1, 28), /* DREQ2 */
[29] = RCAR_GP_PIN(1, 29), /* DACK2 */
[30] = RCAR_GP_PIN(2, 18), /* ETH_CRS_DV */
[31] = RCAR_GP_PIN(2, 19), /* ETH_RX_ER */
} },
{ PINMUX_BIAS_REG("PUPR5", 0xe6060114, "N/A", 0) {
[ 0] = RCAR_GP_PIN(4, 27), /* SCIFA0_SCK */
[ 1] = RCAR_GP_PIN(4, 28), /* SCIFA0_RXD */
[ 2] = RCAR_GP_PIN(4, 29), /* SCIFA0_TXD */
[ 3] = RCAR_GP_PIN(4, 30), /* SCIFA0_CTS# */
[ 4] = RCAR_GP_PIN(4, 31), /* SCIFA0_RTS# */
[ 5] = RCAR_GP_PIN(5, 0), /* SCIFA1_RXD */
[ 6] = RCAR_GP_PIN(5, 1), /* SCIFA1_TXD */
[ 7] = RCAR_GP_PIN(5, 2), /* SCIFA1_CTS# */
[ 8] = RCAR_GP_PIN(5, 3), /* SCIFA1_RTS# */
[ 9] = RCAR_GP_PIN(5, 4), /* SCIFA2_SCK */
[10] = RCAR_GP_PIN(5, 5), /* SCIFA2_RXD */
[11] = RCAR_GP_PIN(5, 6), /* SCIFA2_TXD */
[12] = RCAR_GP_PIN(5, 7), /* HSCK0 */
[13] = RCAR_GP_PIN(5, 8), /* HRX0 */
[14] = RCAR_GP_PIN(5, 9), /* HTX0 */
[15] = RCAR_GP_PIN(5, 10), /* HCTS0# */
[16] = RCAR_GP_PIN(5, 11), /* HRTS0# */
[17] = RCAR_GP_PIN(5, 12), /* MSIOF0_SCK */
[18] = RCAR_GP_PIN(5, 13), /* MSIOF0_SYNC */
[19] = RCAR_GP_PIN(5, 14), /* MSIOF0_SS1 */
[20] = RCAR_GP_PIN(5, 15), /* MSIOF0_TXD */
[21] = RCAR_GP_PIN(5, 16), /* MSIOF0_SS2 */
[22] = RCAR_GP_PIN(5, 17), /* MSIOF0_RXD */
[23] = RCAR_GP_PIN(5, 18), /* USB0_PWEN */
[24] = RCAR_GP_PIN(5, 19), /* USB0_OVC_VBUS */
[25] = RCAR_GP_PIN(5, 20), /* USB1_PWEN */
[26] = RCAR_GP_PIN(5, 21), /* USB1_OVC */
[27] = RCAR_GP_PIN(5, 22), /* USB2_PWEN */
[28] = RCAR_GP_PIN(5, 23), /* USB2_OVC */
[29] = RCAR_GP_PIN(2, 20), /* ETH_RXD0 */
[30] = RCAR_GP_PIN(2, 21), /* ETH_RXD1 */
[31] = RCAR_GP_PIN(2, 22), /* ETH_LINK */
} },
{ PINMUX_BIAS_REG("PUPR6", 0xe6060118, "N/A", 0) {
[ 0] = RCAR_GP_PIN(2, 23), /* ETH_REF_CLK */
[ 1] = RCAR_GP_PIN(2, 24), /* ETH_MDIO */
[ 2] = RCAR_GP_PIN(2, 25), /* ETH_TXD1 */
[ 3] = RCAR_GP_PIN(2, 26), /* ETH_TX_EN */
[ 4] = RCAR_GP_PIN(2, 27), /* ETH_MAGIC */
[ 5] = RCAR_GP_PIN(2, 28), /* ETH_TXD0 */
[ 6] = RCAR_GP_PIN(2, 29), /* ETH_MDC */
[ 7] = RCAR_GP_PIN(5, 29), /* PWM0 */
[ 8] = RCAR_GP_PIN(5, 30), /* PWM1 */
[ 9] = RCAR_GP_PIN(5, 31), /* PWM2 */
[10] = SH_PFC_PIN_NONE,
[11] = SH_PFC_PIN_NONE,
[12] = SH_PFC_PIN_NONE,
[13] = SH_PFC_PIN_NONE,
[14] = SH_PFC_PIN_NONE,
[15] = SH_PFC_PIN_NONE,
[16] = SH_PFC_PIN_NONE,
[17] = SH_PFC_PIN_NONE,
[18] = SH_PFC_PIN_NONE,
[19] = SH_PFC_PIN_NONE,
[20] = SH_PFC_PIN_NONE,
[21] = SH_PFC_PIN_NONE,
[22] = SH_PFC_PIN_NONE,
[23] = SH_PFC_PIN_NONE,
[24] = SH_PFC_PIN_NONE,
[25] = SH_PFC_PIN_NONE,
[26] = SH_PFC_PIN_NONE,
[27] = SH_PFC_PIN_NONE,
[28] = SH_PFC_PIN_NONE,
[29] = SH_PFC_PIN_NONE,
[30] = SH_PFC_PIN_NONE,
[31] = SH_PFC_PIN_NONE,
} },
{ /* sentinel */ }
};
static const struct soc_device_attribute r8a7790_tdsel[] = {
{ .soc_id = "r8a7790", .revision = "ES1.0" },
{ /* sentinel */ }
@ -6009,6 +6292,8 @@ static int r8a7790_pinmux_soc_init(struct sh_pfc *pfc)
static const struct sh_pfc_soc_operations r8a7790_pinmux_ops = {
.init = r8a7790_pinmux_soc_init,
.pin_to_pocctrl = r8a7790_pin_to_pocctrl,
.get_bias = rcar_pinmux_get_bias,
.set_bias = rcar_pinmux_set_bias,
};
#ifdef CONFIG_PINCTRL_PFC_R8A7742
@ -6027,6 +6312,7 @@ const struct sh_pfc_soc_info r8a7742_pinmux_info = {
.nr_functions = ARRAY_SIZE(pinmux_functions.common),
.cfg_regs = pinmux_config_regs,
.bias_regs = pinmux_bias_regs,
.pinmux_data = pinmux_data,
.pinmux_data_size = ARRAY_SIZE(pinmux_data),
@ -6051,6 +6337,7 @@ const struct sh_pfc_soc_info r8a7790_pinmux_info = {
ARRAY_SIZE(pinmux_functions.automotive),
.cfg_regs = pinmux_config_regs,
.bias_regs = pinmux_bias_regs,
.pinmux_data = pinmux_data,
.pinmux_data_size = ARRAY_SIZE(pinmux_data),

533
drivers/pinctrl/renesas/pfc-r8a7792.c
View file

@ -11,18 +11,29 @@
#include "sh_pfc.h"
#define CPU_ALL_GP(fn, sfx) \
PORT_GP_29(0, fn, sfx), \
PORT_GP_23(1, fn, sfx), \
PORT_GP_32(2, fn, sfx), \
PORT_GP_28(3, fn, sfx), \
PORT_GP_17(4, fn, sfx), \
PORT_GP_17(5, fn, sfx), \
PORT_GP_17(6, fn, sfx), \
PORT_GP_17(7, fn, sfx), \
PORT_GP_17(8, fn, sfx), \
PORT_GP_17(9, fn, sfx), \
PORT_GP_32(10, fn, sfx), \
PORT_GP_30(11, fn, sfx)
PORT_GP_CFG_29(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_23(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_32(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_28(3, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_17(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_17(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_17(6, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_17(7, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_17(8, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_17(9, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_32(10, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_30(11, fn, sfx, SH_PFC_PIN_CFG_PULL_UP)
#define CPU_ALL_NOGP(fn) \
PIN_NOGP_CFG(DU0_DOTCLKIN, "DU0_DOTCLKIN", fn, SH_PFC_PIN_CFG_PULL_UP), \
PIN_NOGP_CFG(DU0_DOTCLKOUT, "DU0_DOTCLKOUT", fn, SH_PFC_PIN_CFG_PULL_UP), \
PIN_NOGP_CFG(DU1_DOTCLKIN, "DU1_DOTCLKIN", fn, SH_PFC_PIN_CFG_PULL_UP), \
PIN_NOGP_CFG(DU1_DOTCLKOUT, "DU1_DOTCLKOUT", fn, SH_PFC_PIN_CFG_PULL_UP), \
PIN_NOGP_CFG(EDBGREQ, "EDBGREQ", fn, SH_PFC_PIN_CFG_PULL_DOWN), \
PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP), \
PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP), \
PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP), \
PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP)
enum {
PINMUX_RESERVED = 0,
@ -723,8 +734,17 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP7_20, AUDIO_CLKB),
};
/*
* Pins not associated with a GPIO port.
*/
enum {
GP_ASSIGN_LAST(),
NOGP_ALL(),
};
static const struct sh_pfc_pin pinmux_pins[] = {
PINMUX_GPIO_GP_ALL(),
PINMUX_NOGP_ALL(),
};
/* - AVB -------------------------------------------------------------------- */
@ -2779,8 +2799,496 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
{ },
};
static const struct pinmux_bias_reg pinmux_bias_regs[] = {
{ PINMUX_BIAS_REG("PUPR0", 0xe6060100, "N/A", 0) {
[ 0] = RCAR_GP_PIN(0, 0), /* DU0_DR0_DATA0 */
[ 1] = RCAR_GP_PIN(0, 1), /* DU0_DR1_DATA1 */
[ 2] = RCAR_GP_PIN(0, 2), /* DU0_DR2_Y4_DATA2 */
[ 3] = RCAR_GP_PIN(0, 3), /* DU0_DR3_Y5_DATA3 */
[ 4] = RCAR_GP_PIN(0, 4), /* DU0_DR4_Y6_DATA4 */
[ 5] = RCAR_GP_PIN(0, 5), /* DU0_DR5_Y7_DATA5 */
[ 6] = RCAR_GP_PIN(0, 6), /* DU0_DR6_Y8_DATA6 */
[ 7] = RCAR_GP_PIN(0, 7), /* DU0_DR7_Y9_DATA7 */
[ 8] = RCAR_GP_PIN(0, 8), /* DU0_DG0_DATA8 */
[ 9] = RCAR_GP_PIN(0, 9), /* DU0_DG1_DATA9 */
[10] = RCAR_GP_PIN(0, 10), /* DU0_DG2_C6_DATA10 */
[11] = RCAR_GP_PIN(0, 11), /* DU0_DG3_C7_DATA11 */
[12] = RCAR_GP_PIN(0, 12), /* DU0_DG4_Y0_DATA12 */
[13] = RCAR_GP_PIN(0, 13), /* DU0_DG5_Y1_DATA13 */
[14] = RCAR_GP_PIN(0, 14), /* DU0_DG6_Y2_DATA14 */
[15] = RCAR_GP_PIN(0, 15), /* DU0_DG7_Y3_DATA15 */
[16] = RCAR_GP_PIN(0, 16), /* DU0_DB0 */
[17] = RCAR_GP_PIN(0, 17), /* DU0_DB1 */
[18] = RCAR_GP_PIN(0, 18), /* DU0_DB2_C0 */
[19] = RCAR_GP_PIN(0, 19), /* DU0_DB3_C1 */
[20] = RCAR_GP_PIN(0, 20), /* DU0_DB4_C2 */
[21] = RCAR_GP_PIN(0, 21), /* DU0_DB5_C3 */
[22] = RCAR_GP_PIN(0, 22), /* DU0_DB6_C4 */
[23] = RCAR_GP_PIN(0, 23), /* DU0_DB7_C5 */
[24] = RCAR_GP_PIN(0, 24), /* DU0_EXHSYNC/DU0_HSYNC */
[25] = RCAR_GP_PIN(0, 25), /* DU0_EXVSYNC/DU0_VSYNC */
[26] = RCAR_GP_PIN(0, 26), /* DU0_EXODDF/DU0_ODDF_DISP_CDE */
[27] = RCAR_GP_PIN(0, 27), /* DU0_DISP */
[28] = RCAR_GP_PIN(0, 28), /* DU0_CDE */
[29] = SH_PFC_PIN_NONE,
[30] = SH_PFC_PIN_NONE,
[31] = SH_PFC_PIN_NONE,
} },
{ PINMUX_BIAS_REG("PUPR1", 0xe6060104, "N/A", 0) {
[ 0] = RCAR_GP_PIN(1, 0), /* DU1_DR2_Y4_DATA0 */
[ 1] = RCAR_GP_PIN(1, 1), /* DU1_DR3_Y5_DATA1 */
[ 2] = RCAR_GP_PIN(1, 2), /* DU1_DR4_Y6_DATA2 */
[ 3] = RCAR_GP_PIN(1, 3), /* DU1_DR5_Y7_DATA3 */
[ 4] = RCAR_GP_PIN(1, 4), /* DU1_DR6_DATA4 */
[ 5] = RCAR_GP_PIN(1, 5), /* DU1_DR7_DATA5 */
[ 6] = RCAR_GP_PIN(1, 6), /* DU1_DG2_C6_DATA6 */
[ 7] = RCAR_GP_PIN(1, 7), /* DU1_DG3_C7_DATA7 */
[ 8] = RCAR_GP_PIN(1, 8), /* DU1_DG4_Y0_DATA8 */
[ 9] = RCAR_GP_PIN(1, 9), /* DU1_DG5_Y1_DATA9 */
[10] = RCAR_GP_PIN(1, 10), /* DU1_DG6_Y2_DATA10 */
[11] = RCAR_GP_PIN(1, 11), /* DU1_DG7_Y3_DATA11 */
[12] = RCAR_GP_PIN(1, 12), /* DU1_DB2_C0_DATA12 */
[13] = RCAR_GP_PIN(1, 13), /* DU1_DB3_C1_DATA13 */
[14] = RCAR_GP_PIN(1, 14), /* DU1_DB4_C2_DATA14 */
[15] = RCAR_GP_PIN(1, 15), /* DU1_DB5_C3_DATA15 */
[16] = RCAR_GP_PIN(1, 16), /* DU1_DB6_C4 */
[17] = RCAR_GP_PIN(1, 17), /* DU1_DB7_C5 */
[18] = RCAR_GP_PIN(1, 18), /* DU1_EXHSYNC/DU1_HSYNC */
[19] = RCAR_GP_PIN(1, 19), /* DU1_EXVSYNC/DU1_VSYNC */
[20] = RCAR_GP_PIN(1, 20), /* DU1_EXODDF/DU1_ODDF_DISP_CDE */
[21] = RCAR_GP_PIN(1, 21), /* DU1_DISP */
[22] = RCAR_GP_PIN(1, 22), /* DU1_CDE */
[23] = SH_PFC_PIN_NONE,
[24] = SH_PFC_PIN_NONE,
[25] = SH_PFC_PIN_NONE,
[26] = SH_PFC_PIN_NONE,
[27] = SH_PFC_PIN_NONE,
[28] = SH_PFC_PIN_NONE,
[29] = SH_PFC_PIN_NONE,
[30] = SH_PFC_PIN_NONE,
[31] = SH_PFC_PIN_NONE,
} },
{ PINMUX_BIAS_REG("PUPR2", 0xe6060108, "N/A", 0) {
[ 0] = RCAR_GP_PIN(2, 0), /* D0 */
[ 1] = RCAR_GP_PIN(2, 1), /* D1 */
[ 2] = RCAR_GP_PIN(2, 2), /* D2 */
[ 3] = RCAR_GP_PIN(2, 3), /* D3 */
[ 4] = RCAR_GP_PIN(2, 4), /* D4 */
[ 5] = RCAR_GP_PIN(2, 5), /* D5 */
[ 6] = RCAR_GP_PIN(2, 6), /* D6 */
[ 7] = RCAR_GP_PIN(2, 7), /* D7 */
[ 8] = RCAR_GP_PIN(2, 8), /* D8 */
[ 9] = RCAR_GP_PIN(2, 9), /* D9 */
[10] = RCAR_GP_PIN(2, 10), /* D10 */
[11] = RCAR_GP_PIN(2, 11), /* D11 */
[12] = RCAR_GP_PIN(2, 12), /* D12 */
[13] = RCAR_GP_PIN(2, 13), /* D13 */
[14] = RCAR_GP_PIN(2, 14), /* D14 */
[15] = RCAR_GP_PIN(2, 15), /* D15 */
[16] = RCAR_GP_PIN(2, 16), /* A0 */
[17] = RCAR_GP_PIN(2, 17), /* A1 */
[18] = RCAR_GP_PIN(2, 18), /* A2 */
[19] = RCAR_GP_PIN(2, 19), /* A3 */
[20] = RCAR_GP_PIN(2, 20), /* A4 */
[21] = RCAR_GP_PIN(2, 21), /* A5 */
[22] = RCAR_GP_PIN(2, 22), /* A6 */
[23] = RCAR_GP_PIN(2, 23), /* A7 */
[24] = RCAR_GP_PIN(2, 24), /* A8 */
[25] = RCAR_GP_PIN(2, 25), /* A9 */
[26] = RCAR_GP_PIN(2, 26), /* A10 */
[27] = RCAR_GP_PIN(2, 27), /* A11 */
[28] = RCAR_GP_PIN(2, 28), /* A12 */
[29] = RCAR_GP_PIN(2, 29), /* A13 */
[30] = RCAR_GP_PIN(2, 30), /* A14 */
[31] = RCAR_GP_PIN(2, 31), /* A15 */
} },
{ PINMUX_BIAS_REG("PUPR3", 0xe606010c, "N/A", 0) {
[ 0] = RCAR_GP_PIN(3, 0), /* A16 */
[ 1] = RCAR_GP_PIN(3, 1), /* A17 */
[ 2] = RCAR_GP_PIN(3, 2), /* A18 */
[ 3] = RCAR_GP_PIN(3, 3), /* A19 */
[ 4] = RCAR_GP_PIN(3, 4), /* A20 */
[ 5] = RCAR_GP_PIN(3, 5), /* A21 */
[ 6] = RCAR_GP_PIN(3, 6), /* CS1#/A26 */
[ 7] = RCAR_GP_PIN(3, 7), /* EX_CS0# */
[ 8] = RCAR_GP_PIN(3, 8), /* EX_CS1# */
[ 9] = RCAR_GP_PIN(3, 9), /* EX_CS2# */
[10] = RCAR_GP_PIN(3, 10), /* EX_CS3# */
[11] = RCAR_GP_PIN(3, 11), /* EX_CS4# */
[12] = RCAR_GP_PIN(3, 12), /* EX_CS5# */
[13] = RCAR_GP_PIN(3, 13), /* BS# */
[14] = RCAR_GP_PIN(3, 14), /* RD# */
[15] = RCAR_GP_PIN(3, 15), /* RD/WR# */
[16] = RCAR_GP_PIN(3, 16), /* WE0# */
[17] = RCAR_GP_PIN(3, 17), /* WE1# */
[18] = RCAR_GP_PIN(3, 18), /* EX_WAIT0 */
[19] = RCAR_GP_PIN(3, 19), /* IRQ0 */
[20] = RCAR_GP_PIN(3, 20), /* IRQ1 */
[21] = RCAR_GP_PIN(3, 21), /* IRQ2 */
[22] = RCAR_GP_PIN(3, 22), /* IRQ3 */
[23] = RCAR_GP_PIN(3, 23), /* A22 */
[24] = RCAR_GP_PIN(3, 24), /* A23 */
[25] = RCAR_GP_PIN(3, 25), /* A24 */
[26] = RCAR_GP_PIN(3, 26), /* A25 */
[27] = RCAR_GP_PIN(3, 27), /* CS0# */
[28] = SH_PFC_PIN_NONE,
[29] = SH_PFC_PIN_NONE,
[30] = SH_PFC_PIN_NONE,
[31] = SH_PFC_PIN_NONE,
} },
{ PINMUX_BIAS_REG("PUPR4", 0xe6060110, "N/A", 0) {
[ 0] = RCAR_GP_PIN(4, 0), /* VI0_CLK */
[ 1] = RCAR_GP_PIN(4, 1), /* VI0_CLKENB */
[ 2] = RCAR_GP_PIN(4, 2), /* VI0_HSYNC# */
[ 3] = RCAR_GP_PIN(4, 3), /* VI0_VSYNC# */
[ 4] = RCAR_GP_PIN(4, 4), /* VI0_D0_B0_C0 */
[ 5] = RCAR_GP_PIN(4, 5), /* VI0_D1_B1_C1 */
[ 6] = RCAR_GP_PIN(4, 6), /* VI0_D2_B2_C2 */
[ 7] = RCAR_GP_PIN(4, 7), /* VI0_D3_B3_C3 */
[ 8] = RCAR_GP_PIN(4, 8), /* VI0_D4_B4_C4 */
[ 9] = RCAR_GP_PIN(4, 9), /* VI0_D5_B5_C5 */
[10] = RCAR_GP_PIN(4, 10), /* VI0_D6_B6_C6 */
[11] = RCAR_GP_PIN(4, 11), /* VI0_D7_B7_C7 */
[12] = RCAR_GP_PIN(4, 12), /* VI0_D8_G0_Y0 */
[13] = RCAR_GP_PIN(4, 13), /* VI0_D9_G1_Y1 */
[14] = RCAR_GP_PIN(4, 14), /* VI0_D10_G2_Y2 */
[15] = RCAR_GP_PIN(4, 15), /* VI0_D11_G3_Y3 */
[16] = RCAR_GP_PIN(4, 16), /* VI0_FIELD */
[17] = SH_PFC_PIN_NONE,
[18] = SH_PFC_PIN_NONE,
[19] = SH_PFC_PIN_NONE,
[20] = SH_PFC_PIN_NONE,
[21] = SH_PFC_PIN_NONE,
[22] = SH_PFC_PIN_NONE,
[23] = SH_PFC_PIN_NONE,
[24] = SH_PFC_PIN_NONE,
[25] = SH_PFC_PIN_NONE,
[26] = SH_PFC_PIN_NONE,
[27] = SH_PFC_PIN_NONE,
[28] = SH_PFC_PIN_NONE,
[29] = SH_PFC_PIN_NONE,
[30] = SH_PFC_PIN_NONE,
[31] = SH_PFC_PIN_NONE,
} },
{ PINMUX_BIAS_REG("PUPR5", 0xe6060114, "N/A", 0) {
[ 0] = RCAR_GP_PIN(5, 0), /* VI1_CLK */
[ 1] = RCAR_GP_PIN(5, 1), /* VI1_CLKENB */
[ 2] = RCAR_GP_PIN(5, 2), /* VI1_HSYNC# */
[ 3] = RCAR_GP_PIN(5, 3), /* VI1_VSYNC# */
[ 4] = RCAR_GP_PIN(5, 4), /* VI1_D0_B0_C0 */
[ 5] = RCAR_GP_PIN(5, 5), /* VI1_D1_B1_C1 */
[ 6] = RCAR_GP_PIN(5, 6), /* VI1_D2_B2_C2 */
[ 7] = RCAR_GP_PIN(5, 7), /* VI1_D3_B3_C3 */
[ 8] = RCAR_GP_PIN(5, 8), /* VI1_D4_B4_C4 */
[ 9] = RCAR_GP_PIN(5, 9), /* VI1_D5_B5_C5 */
[10] = RCAR_GP_PIN(5, 10), /* VI1_D6_B6_C6 */
[11] = RCAR_GP_PIN(5, 11), /* VI1_D7_B7_C7 */
[12] = RCAR_GP_PIN(5, 12), /* VI1_D8_G0_Y0 */
[13] = RCAR_GP_PIN(5, 13), /* VI1_D9_G1_Y1 */
[14] = RCAR_GP_PIN(5, 14), /* VI1_D10_G2_Y2 */
[15] = RCAR_GP_PIN(5, 15), /* VI1_D11_G3_Y3 */
[16] = RCAR_GP_PIN(5, 16), /* VI1_FIELD */
[17] = SH_PFC_PIN_NONE,
[18] = SH_PFC_PIN_NONE,
[19] = SH_PFC_PIN_NONE,
[20] = SH_PFC_PIN_NONE,
[21] = SH_PFC_PIN_NONE,
[22] = SH_PFC_PIN_NONE,
[23] = SH_PFC_PIN_NONE,
[24] = SH_PFC_PIN_NONE,
[25] = SH_PFC_PIN_NONE,
[26] = SH_PFC_PIN_NONE,
[27] = SH_PFC_PIN_NONE,
[28] = SH_PFC_PIN_NONE,
[29] = SH_PFC_PIN_NONE,
[30] = SH_PFC_PIN_NONE,
[31] = SH_PFC_PIN_NONE,
} },
{ PINMUX_BIAS_REG("PUPR6", 0xe6060118, "N/A", 0) {
[ 0] = RCAR_GP_PIN(6, 0), /* VI2_CLK */
[ 1] = RCAR_GP_PIN(6, 1), /* VI2_CLKENB */
[ 2] = RCAR_GP_PIN(6, 2), /* VI2_HSYNC# */
[ 3] = RCAR_GP_PIN(6, 3), /* VI2_VSYNC# */
[ 4] = RCAR_GP_PIN(6, 4), /* VI2_D0_C0 */
[ 5] = RCAR_GP_PIN(6, 5), /* VI2_D1_C1 */
[ 6] = RCAR_GP_PIN(6, 6), /* VI2_D2_C2 */
[ 7] = RCAR_GP_PIN(6, 7), /* VI2_D3_C3 */
[ 8] = RCAR_GP_PIN(6, 8), /* VI2_D4_C4 */
[ 9] = RCAR_GP_PIN(6, 9), /* VI2_D5_C5 */
[10] = RCAR_GP_PIN(6, 10), /* VI2_D6_C6 */
[11] = RCAR_GP_PIN(6, 11), /* VI2_D7_C7 */
[12] = RCAR_GP_PIN(6, 12), /* VI2_D8_Y0 */
[13] = RCAR_GP_PIN(6, 13), /* VI2_D9_Y1 */
[14] = RCAR_GP_PIN(6, 14), /* VI2_D10_Y2 */
[15] = RCAR_GP_PIN(6, 15), /* VI2_D11_Y3 */
[16] = RCAR_GP_PIN(6, 16), /* VI2_FIELD */
[17] = SH_PFC_PIN_NONE,
[18] = SH_PFC_PIN_NONE,
[19] = SH_PFC_PIN_NONE,
[20] = SH_PFC_PIN_NONE,
[21] = SH_PFC_PIN_NONE,
[22] = SH_PFC_PIN_NONE,
[23] = SH_PFC_PIN_NONE,
[24] = SH_PFC_PIN_NONE,
[25] = SH_PFC_PIN_NONE,
[26] = SH_PFC_PIN_NONE,
[27] = SH_PFC_PIN_NONE,
[28] = SH_PFC_PIN_NONE,
[29] = SH_PFC_PIN_NONE,
[30] = SH_PFC_PIN_NONE,
[31] = SH_PFC_PIN_NONE,
} },
{ PINMUX_BIAS_REG("PUPR7", 0xe606011c, "N/A", 0) {
[ 0] = RCAR_GP_PIN(7, 0), /* VI3_CLK */
[ 1] = RCAR_GP_PIN(7, 1), /* VI3_CLKENB */
[ 2] = RCAR_GP_PIN(7, 2), /* VI3_HSYNC# */
[ 3] = RCAR_GP_PIN(7, 3), /* VI3_VSYNC# */
[ 4] = RCAR_GP_PIN(7, 4), /* VI3_D0_C0 */
[ 5] = RCAR_GP_PIN(7, 5), /* VI3_D1_C1 */
[ 6] = RCAR_GP_PIN(7, 6), /* VI3_D2_C2 */
[ 7] = RCAR_GP_PIN(7, 7), /* VI3_D3_C3 */
[ 8] = RCAR_GP_PIN(7, 8), /* VI3_D4_C4 */
[ 9] = RCAR_GP_PIN(7, 9), /* VI3_D5_C5 */
[10] = RCAR_GP_PIN(7, 10), /* VI3_D6_C6 */
[11] = RCAR_GP_PIN(7, 11), /* VI3_D7_C7 */
[12] = RCAR_GP_PIN(7, 12), /* VI3_D8_Y0 */
[13] = RCAR_GP_PIN(7, 13), /* VI3_D9_Y1 */
[14] = RCAR_GP_PIN(7, 14), /* VI3_D10_Y2 */
[15] = RCAR_GP_PIN(7, 15), /* VI3_D11_Y3 */
[16] = RCAR_GP_PIN(7, 16), /* VI3_FIELD */
[17] = SH_PFC_PIN_NONE,
[18] = SH_PFC_PIN_NONE,
[19] = SH_PFC_PIN_NONE,
[20] = SH_PFC_PIN_NONE,
[21] = SH_PFC_PIN_NONE,
[22] = SH_PFC_PIN_NONE,
[23] = SH_PFC_PIN_NONE,
[24] = SH_PFC_PIN_NONE,
[25] = SH_PFC_PIN_NONE,
[26] = SH_PFC_PIN_NONE,
[27] = SH_PFC_PIN_NONE,
[28] = SH_PFC_PIN_NONE,
[29] = SH_PFC_PIN_NONE,
[30] = SH_PFC_PIN_NONE,
[31] = SH_PFC_PIN_NONE,
} },
{ PINMUX_BIAS_REG("PUPR8", 0xe6060120, "N/A", 0) {
[ 0] = RCAR_GP_PIN(8, 0), /* VI4_CLK */
[ 1] = RCAR_GP_PIN(8, 1), /* VI4_CLKENB */
[ 2] = RCAR_GP_PIN(8, 2), /* VI4_HSYNC# */
[ 3] = RCAR_GP_PIN(8, 3), /* VI4_VSYNC# */
[ 4] = RCAR_GP_PIN(8, 4), /* VI4_D0_C0 */
[ 5] = RCAR_GP_PIN(8, 5), /* VI4_D1_C1 */
[ 6] = RCAR_GP_PIN(8, 6), /* VI4_D2_C2 */
[ 7] = RCAR_GP_PIN(8, 7), /* VI4_D3_C3 */
[ 8] = RCAR_GP_PIN(8, 8), /* VI4_D4_C4 */
[ 9] = RCAR_GP_PIN(8, 9), /* VI4_D5_C5 */
[10] = RCAR_GP_PIN(8, 10), /* VI4_D6_C6 */
[11] = RCAR_GP_PIN(8, 11), /* VI4_D7_C7 */
[12] = RCAR_GP_PIN(8, 12), /* VI4_D8_Y0 */
[13] = RCAR_GP_PIN(8, 13), /* VI4_D9_Y1 */
[14] = RCAR_GP_PIN(8, 14), /* VI4_D10_Y2 */
[15] = RCAR_GP_PIN(8, 15), /* VI4_D11_Y3 */
[16] = RCAR_GP_PIN(8, 16), /* VI4_FIELD */
[17] = SH_PFC_PIN_NONE,
[18] = SH_PFC_PIN_NONE,
[19] = SH_PFC_PIN_NONE,
[20] = SH_PFC_PIN_NONE,
[21] = SH_PFC_PIN_NONE,
[22] = SH_PFC_PIN_NONE,
[23] = SH_PFC_PIN_NONE,
[24] = SH_PFC_PIN_NONE,
[25] = SH_PFC_PIN_NONE,
[26] = SH_PFC_PIN_NONE,
[27] = SH_PFC_PIN_NONE,
[28] = SH_PFC_PIN_NONE,
[29] = SH_PFC_PIN_NONE,
[30] = SH_PFC_PIN_NONE,
[31] = SH_PFC_PIN_NONE,
} },
{ PINMUX_BIAS_REG("PUPR9", 0xe6060124, "N/A", 0) {
[ 0] = RCAR_GP_PIN(9, 0), /* VI5_CLK */
[ 1] = RCAR_GP_PIN(9, 1), /* VI5_CLKENB */
[ 2] = RCAR_GP_PIN(9, 2), /* VI5_HSYNC# */
[ 3] = RCAR_GP_PIN(9, 3), /* VI5_VSYNC# */
[ 4] = RCAR_GP_PIN(9, 4), /* VI5_D0_C0 */
[ 5] = RCAR_GP_PIN(9, 5), /* VI5_D1_C1 */
[ 6] = RCAR_GP_PIN(9, 6), /* VI5_D2_C2 */
[ 7] = RCAR_GP_PIN(9, 7), /* VI5_D3_C3 */
[ 8] = RCAR_GP_PIN(9, 8), /* VI5_D4_C4 */
[ 9] = RCAR_GP_PIN(9, 9), /* VI5_D5_C5 */
[10] = RCAR_GP_PIN(9, 10), /* VI5_D6_C6 */
[11] = RCAR_GP_PIN(9, 11), /* VI5_D7_C7 */
[12] = RCAR_GP_PIN(9, 12), /* VI5_D8_Y0 */
[13] = RCAR_GP_PIN(9, 13), /* VI5_D9_Y1 */
[14] = RCAR_GP_PIN(9, 14), /* VI5_D10_Y2 */
[15] = RCAR_GP_PIN(9, 15), /* VI5_D11_Y3 */
[16] = RCAR_GP_PIN(9, 16), /* VI5_FIELD */
[17] = SH_PFC_PIN_NONE,
[18] = SH_PFC_PIN_NONE,
[19] = SH_PFC_PIN_NONE,
[20] = SH_PFC_PIN_NONE,
[21] = SH_PFC_PIN_NONE,
[22] = SH_PFC_PIN_NONE,
[23] = SH_PFC_PIN_NONE,
[24] = SH_PFC_PIN_NONE,
[25] = SH_PFC_PIN_NONE,
[26] = SH_PFC_PIN_NONE,
[27] = SH_PFC_PIN_NONE,
[28] = SH_PFC_PIN_NONE,
[29] = SH_PFC_PIN_NONE,
[30] = SH_PFC_PIN_NONE,
[31] = SH_PFC_PIN_NONE,
} },
{ PINMUX_BIAS_REG("PUPR10", 0xe6060128, "N/A", 0) {
[ 0] = RCAR_GP_PIN(10, 0), /* HSCK0 */
[ 1] = RCAR_GP_PIN(10, 1), /* HCTS0# */
[ 2] = RCAR_GP_PIN(10, 2), /* HRTS0# */
[ 3] = RCAR_GP_PIN(10, 3), /* HTX0 */
[ 4] = RCAR_GP_PIN(10, 4), /* HRX0 */
[ 5] = RCAR_GP_PIN(10, 5), /* HSCK1 */
[ 6] = RCAR_GP_PIN(10, 6), /* HRTS1# */
[ 7] = RCAR_GP_PIN(10, 7), /* HCTS1# */
[ 8] = RCAR_GP_PIN(10, 8), /* HTX1 */
[ 9] = RCAR_GP_PIN(10, 9), /* HRX1 */
[10] = RCAR_GP_PIN(10, 10), /* SCK0 */
[11] = RCAR_GP_PIN(10, 11), /* CTS0# */
[12] = RCAR_GP_PIN(10, 12), /* RTS0# */
[13] = RCAR_GP_PIN(10, 13), /* TX0 */
[14] = RCAR_GP_PIN(10, 14), /* RX0 */
[15] = RCAR_GP_PIN(10, 15), /* SCK1 */
[16] = RCAR_GP_PIN(10, 16), /* CTS1# */
[17] = RCAR_GP_PIN(10, 17), /* RTS1# */
[18] = RCAR_GP_PIN(10, 18), /* TX1 */
[19] = RCAR_GP_PIN(10, 19), /* RX1 */
[20] = RCAR_GP_PIN(10, 20), /* SCK2 */
[21] = RCAR_GP_PIN(10, 21), /* TX2 */
[22] = RCAR_GP_PIN(10, 22), /* RX2 */
[23] = RCAR_GP_PIN(10, 23), /* SCK3 */
[24] = RCAR_GP_PIN(10, 24), /* TX3 */
[25] = RCAR_GP_PIN(10, 25), /* RX3 */
[26] = RCAR_GP_PIN(10, 26), /* SCIF_CLK */
[27] = RCAR_GP_PIN(10, 27), /* CAN0_TX */
[28] = RCAR_GP_PIN(10, 28), /* CAN0_RX */
[29] = RCAR_GP_PIN(10, 29), /* CAN_CLK */
[30] = RCAR_GP_PIN(10, 30), /* CAN1_TX */
[31] = RCAR_GP_PIN(10, 31), /* CAN1_RX */
} },
{ PINMUX_BIAS_REG("PUPR11", 0xe606012c, "N/A", 0) {
[ 0] = RCAR_GP_PIN(11, 0), /* PWM0 */
[ 1] = RCAR_GP_PIN(11, 1), /* PWM1 */
[ 2] = RCAR_GP_PIN(11, 2), /* PWM2 */
[ 3] = RCAR_GP_PIN(11, 3), /* PWM3 */
[ 4] = RCAR_GP_PIN(11, 4), /* PWM4 */
[ 5] = RCAR_GP_PIN(11, 5), /* SD0_CLK */
[ 6] = RCAR_GP_PIN(11, 6), /* SD0_CMD */
[ 7] = RCAR_GP_PIN(11, 7), /* SD0_DAT0 */
[ 8] = RCAR_GP_PIN(11, 8), /* SD0_DAT1 */
[ 9] = RCAR_GP_PIN(11, 9), /* SD0_DAT2 */
[10] = RCAR_GP_PIN(11, 10), /* SD0_DAT3 */
[11] = RCAR_GP_PIN(11, 11), /* SD0_CD */
[12] = RCAR_GP_PIN(11, 12), /* SD0_WP */
[13] = RCAR_GP_PIN(11, 13), /* SSI_SCK3 */
[14] = RCAR_GP_PIN(11, 14), /* SSI_WS3 */
[15] = RCAR_GP_PIN(11, 15), /* SSI_SDATA3 */
[16] = RCAR_GP_PIN(11, 16), /* SSI_SCK4 */
[17] = RCAR_GP_PIN(11, 17), /* SSI_WS4 */
[18] = RCAR_GP_PIN(11, 18), /* SSI_SDATA4 */
[19] = RCAR_GP_PIN(11, 19), /* AUDIO_CLKOUT */
[20] = RCAR_GP_PIN(11, 20), /* AUDIO_CLKA */
[21] = RCAR_GP_PIN(11, 21), /* AUDIO_CLKB */
[22] = RCAR_GP_PIN(11, 22), /* ADICLK */
[23] = RCAR_GP_PIN(11, 23), /* ADICS_SAMP */
[24] = RCAR_GP_PIN(11, 24), /* ADIDATA */
[25] = RCAR_GP_PIN(11, 25), /* ADICHS0 */
[26] = RCAR_GP_PIN(11, 26), /* ADICHS1 */
[27] = RCAR_GP_PIN(11, 27), /* ADICHS2 */
[28] = RCAR_GP_PIN(11, 28), /* AVS1 */
[29] = RCAR_GP_PIN(11, 29), /* AVS2 */
[30] = SH_PFC_PIN_NONE,
[31] = SH_PFC_PIN_NONE,
} },
{ PINMUX_BIAS_REG("PUPR12", 0xe6060130, "N/A", 0) {
/* PUPR12 pull-up pins */
[ 0] = PIN_DU0_DOTCLKIN, /* DU0_DOTCLKIN */
[ 1] = PIN_DU0_DOTCLKOUT, /* DU0_DOTCLKOUT */
[ 2] = PIN_DU1_DOTCLKIN, /* DU1_DOTCLKIN */
[ 3] = PIN_DU1_DOTCLKOUT, /* DU1_DOTCLKOUT */
[ 4] = PIN_TRST_N, /* TRST# */
[ 5] = PIN_TCK, /* TCK */
[ 6] = PIN_TMS, /* TMS */
[ 7] = PIN_TDI, /* TDI */
[ 8] = SH_PFC_PIN_NONE,
[ 9] = SH_PFC_PIN_NONE,
[10] = SH_PFC_PIN_NONE,
[11] = SH_PFC_PIN_NONE,
[12] = SH_PFC_PIN_NONE,
[13] = SH_PFC_PIN_NONE,
[14] = SH_PFC_PIN_NONE,
[15] = SH_PFC_PIN_NONE,
[16] = SH_PFC_PIN_NONE,
[17] = SH_PFC_PIN_NONE,
[18] = SH_PFC_PIN_NONE,
[19] = SH_PFC_PIN_NONE,
[20] = SH_PFC_PIN_NONE,
[21] = SH_PFC_PIN_NONE,
[22] = SH_PFC_PIN_NONE,
[23] = SH_PFC_PIN_NONE,
[24] = SH_PFC_PIN_NONE,
[25] = SH_PFC_PIN_NONE,
[26] = SH_PFC_PIN_NONE,
[27] = SH_PFC_PIN_NONE,
[28] = SH_PFC_PIN_NONE,
[29] = SH_PFC_PIN_NONE,
[30] = SH_PFC_PIN_NONE,
[31] = SH_PFC_PIN_NONE,
} },
{ PINMUX_BIAS_REG("N/A", 0, "PUPR12", 0xe6060130) {
/* PUPR12 pull-down pins */
[ 0] = SH_PFC_PIN_NONE,
[ 1] = SH_PFC_PIN_NONE,
[ 2] = SH_PFC_PIN_NONE,
[ 3] = SH_PFC_PIN_NONE,
[ 4] = SH_PFC_PIN_NONE,
[ 5] = SH_PFC_PIN_NONE,
[ 6] = SH_PFC_PIN_NONE,
[ 7] = SH_PFC_PIN_NONE,
[ 8] = PIN_EDBGREQ, /* EDBGREQ */
[ 9] = SH_PFC_PIN_NONE,
[10] = SH_PFC_PIN_NONE,
[11] = SH_PFC_PIN_NONE,
[12] = SH_PFC_PIN_NONE,
[13] = SH_PFC_PIN_NONE,
[14] = SH_PFC_PIN_NONE,
[15] = SH_PFC_PIN_NONE,
[16] = SH_PFC_PIN_NONE,
[17] = SH_PFC_PIN_NONE,
[18] = SH_PFC_PIN_NONE,
[19] = SH_PFC_PIN_NONE,
[20] = SH_PFC_PIN_NONE,
[21] = SH_PFC_PIN_NONE,
[22] = SH_PFC_PIN_NONE,
[23] = SH_PFC_PIN_NONE,
[24] = SH_PFC_PIN_NONE,
[25] = SH_PFC_PIN_NONE,
[26] = SH_PFC_PIN_NONE,
[27] = SH_PFC_PIN_NONE,
[28] = SH_PFC_PIN_NONE,
[29] = SH_PFC_PIN_NONE,
[30] = SH_PFC_PIN_NONE,
[31] = SH_PFC_PIN_NONE,
} },
{ /* sentinel */ }
};
static const struct sh_pfc_soc_operations r8a7792_pinmux_ops = {
.get_bias = rcar_pinmux_get_bias,
.set_bias = rcar_pinmux_set_bias,
};
const struct sh_pfc_soc_info r8a7792_pinmux_info = {
.name = "r8a77920_pfc",
.ops = &r8a7792_pinmux_ops,
.unlock_reg = 0xe6060000, /* PMMR */
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
@ -2793,6 +3301,7 @@ const struct sh_pfc_soc_info r8a7792_pinmux_info = {
.nr_functions = ARRAY_SIZE(pinmux_functions),
.cfg_regs = pinmux_config_regs,
.bias_regs = pinmux_bias_regs,
.pinmux_data = pinmux_data,
.pinmux_data_size = ARRAY_SIZE(pinmux_data),

360
drivers/pinctrl/renesas/pfc-r8a7794.c
View file

@ -15,15 +15,66 @@
#include "sh_pfc.h"
#define CPU_ALL_GP(fn, sfx) \
PORT_GP_32(0, fn, sfx), \
PORT_GP_26(1, fn, sfx), \
PORT_GP_32(2, fn, sfx), \
PORT_GP_32(3, fn, sfx), \
PORT_GP_32(4, fn, sfx), \
PORT_GP_28(5, fn, sfx), \
PORT_GP_CFG_24(6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
PORT_GP_1(6, 24, fn, sfx), \
PORT_GP_1(6, 25, fn, sfx)
PORT_GP_CFG_32(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_26(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_32(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_32(3, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_32(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_7(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_1(5, 7, fn, sfx), \
PORT_GP_1(5, 8, fn, sfx), \
PORT_GP_1(5, 9, fn, sfx), \
PORT_GP_CFG_1(5, 10, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(5, 11, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(5, 12, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(5, 13, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(5, 14, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(5, 15, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(5, 16, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(5, 17, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(5, 18, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(5, 19, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(5, 20, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(5, 21, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(5, 22, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(5, 23, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_1(5, 24, fn, sfx), \
PORT_GP_1(5, 25, fn, sfx), \
PORT_GP_1(5, 26, fn, sfx), \
PORT_GP_1(5, 27, fn, sfx), \
PORT_GP_CFG_1(6, 0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
PORT_GP_CFG_1(6, 1, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(6, 2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(6, 3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(6, 4, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(6, 5, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(6, 6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(6, 7, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(6, 8, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
PORT_GP_CFG_1(6, 9, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(6, 10, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(6, 11, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(6, 12, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(6, 13, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(6, 14, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(6, 15, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(6, 16, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
PORT_GP_CFG_1(6, 17, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(6, 18, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(6, 19, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(6, 20, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(6, 21, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(6, 22, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(6, 23, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(6, 24, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(6, 25, fn, sfx, SH_PFC_PIN_CFG_PULL_UP)
#define CPU_ALL_NOGP(fn) \
PIN_NOGP_CFG(ASEBRK_N_ACK, "ASEBRK#/ACK", fn, SH_PFC_PIN_CFG_PULL_DOWN), \
PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP), \
PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP), \
PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP), \
PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP)
enum {
PINMUX_RESERVED = 0,
@ -1436,8 +1487,17 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP13_26_24, FMIN_E, SEL_DARC_4),
};
/*
* Pins not associated with a GPIO port.
*/
enum {
GP_ASSIGN_LAST(),
NOGP_ALL(),
};
static const struct sh_pfc_pin pinmux_pins[] = {
PINMUX_GPIO_GP_ALL(),
PINMUX_NOGP_ALL(),
};
/* - Audio Clock ------------------------------------------------------------ */
@ -5580,6 +5640,284 @@ static int r8a7794_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *poc
return -EINVAL;
}
static const struct pinmux_bias_reg pinmux_bias_regs[] = {
{ PINMUX_BIAS_REG("PUPR0", 0xe6060100, "N/A", 0) {
[ 0] = RCAR_GP_PIN(0, 0), /* D0 */
[ 1] = RCAR_GP_PIN(0, 1), /* D1 */
[ 2] = RCAR_GP_PIN(0, 2), /* D2 */
[ 3] = RCAR_GP_PIN(0, 3), /* D3 */
[ 4] = RCAR_GP_PIN(0, 4), /* D4 */
[ 5] = RCAR_GP_PIN(0, 5), /* D5 */
[ 6] = RCAR_GP_PIN(0, 6), /* D6 */
[ 7] = RCAR_GP_PIN(0, 7), /* D7 */
[ 8] = RCAR_GP_PIN(0, 8), /* D8 */
[ 9] = RCAR_GP_PIN(0, 9), /* D9 */
[10] = RCAR_GP_PIN(0, 10), /* D10 */
[11] = RCAR_GP_PIN(0, 11), /* D11 */
[12] = RCAR_GP_PIN(0, 12), /* D12 */
[13] = RCAR_GP_PIN(0, 13), /* D13 */
[14] = RCAR_GP_PIN(0, 14), /* D14 */
[15] = RCAR_GP_PIN(0, 15), /* D15 */
[16] = RCAR_GP_PIN(0, 16), /* A0 */
[17] = RCAR_GP_PIN(0, 17), /* A1 */
[18] = RCAR_GP_PIN(0, 18), /* A2 */
[19] = RCAR_GP_PIN(0, 19), /* A3 */
[20] = RCAR_GP_PIN(0, 20), /* A4 */
[21] = RCAR_GP_PIN(0, 21), /* A5 */
[22] = RCAR_GP_PIN(0, 22), /* A6 */
[23] = RCAR_GP_PIN(0, 23), /* A7 */
[24] = RCAR_GP_PIN(0, 24), /* A8 */
[25] = RCAR_GP_PIN(0, 25), /* A9 */
[26] = RCAR_GP_PIN(0, 26), /* A10 */
[27] = RCAR_GP_PIN(0, 27), /* A11 */
[28] = RCAR_GP_PIN(0, 28), /* A12 */
[29] = RCAR_GP_PIN(0, 29), /* A13 */
[30] = RCAR_GP_PIN(0, 30), /* A14 */
[31] = RCAR_GP_PIN(0, 31), /* A15 */
} },
{ PINMUX_BIAS_REG("PUPR1", 0xe6060104, "N/A", 0) {
/* PUPR1 pull-up pins */
[ 0] = RCAR_GP_PIN(1, 0), /* A16 */
[ 1] = RCAR_GP_PIN(1, 1), /* A17 */
[ 2] = RCAR_GP_PIN(1, 2), /* A18 */
[ 3] = RCAR_GP_PIN(1, 3), /* A19 */
[ 4] = RCAR_GP_PIN(1, 4), /* A20 */
[ 5] = RCAR_GP_PIN(1, 5), /* A21 */
[ 6] = RCAR_GP_PIN(1, 6), /* A22 */
[ 7] = RCAR_GP_PIN(1, 7), /* A23 */
[ 8] = RCAR_GP_PIN(1, 8), /* A24 */
[ 9] = RCAR_GP_PIN(1, 9), /* A25 */
[10] = RCAR_GP_PIN(1, 10), /* CS0# */
[11] = RCAR_GP_PIN(1, 12), /* EX_CS0# */
[12] = RCAR_GP_PIN(1, 14), /* EX_CS2# */
[13] = RCAR_GP_PIN(1, 16), /* EX_CS4# */
[14] = RCAR_GP_PIN(1, 18), /* BS# */
[15] = RCAR_GP_PIN(1, 19), /* RD# */
[16] = RCAR_GP_PIN(1, 20), /* RD/WR# */
[17] = RCAR_GP_PIN(1, 21), /* WE0# */
[18] = RCAR_GP_PIN(1, 22), /* WE1# */
[19] = RCAR_GP_PIN(1, 23), /* EX_WAIT0 */
[20] = RCAR_GP_PIN(1, 24), /* DREQ0# */
[21] = RCAR_GP_PIN(1, 25), /* DACK0 */
[22] = PIN_TRST_N, /* TRST# */
[23] = PIN_TCK, /* TCK */
[24] = PIN_TMS, /* TMS */
[25] = PIN_TDI, /* TDI */
[26] = RCAR_GP_PIN(1, 11), /* CS1#/A26 */
[27] = RCAR_GP_PIN(1, 13), /* EX_CS1# */
[28] = RCAR_GP_PIN(1, 15), /* EX_CS3# */
[29] = RCAR_GP_PIN(1, 17), /* EX_CS5# */
[30] = SH_PFC_PIN_NONE,
[31] = SH_PFC_PIN_NONE,
} },
{ PINMUX_BIAS_REG("N/A", 0, "PUPR1", 0xe6060104) {
/* PUPR1 pull-down pins */
[ 0] = SH_PFC_PIN_NONE,
[ 1] = SH_PFC_PIN_NONE,
[ 2] = SH_PFC_PIN_NONE,
[ 3] = SH_PFC_PIN_NONE,
[ 4] = SH_PFC_PIN_NONE,
[ 5] = SH_PFC_PIN_NONE,
[ 6] = SH_PFC_PIN_NONE,
[ 7] = SH_PFC_PIN_NONE,
[ 8] = SH_PFC_PIN_NONE,
[ 9] = SH_PFC_PIN_NONE,
[10] = SH_PFC_PIN_NONE,
[11] = SH_PFC_PIN_NONE,
[12] = SH_PFC_PIN_NONE,
[13] = SH_PFC_PIN_NONE,
[14] = SH_PFC_PIN_NONE,
[15] = SH_PFC_PIN_NONE,
[16] = SH_PFC_PIN_NONE,
[17] = SH_PFC_PIN_NONE,
[18] = SH_PFC_PIN_NONE,
[19] = SH_PFC_PIN_NONE,
[20] = SH_PFC_PIN_NONE,
[21] = SH_PFC_PIN_NONE,
[22] = SH_PFC_PIN_NONE,
[23] = SH_PFC_PIN_NONE,
[24] = SH_PFC_PIN_NONE,
[25] = SH_PFC_PIN_NONE,
[26] = SH_PFC_PIN_NONE,
[27] = SH_PFC_PIN_NONE,
[28] = SH_PFC_PIN_NONE,
[29] = SH_PFC_PIN_NONE,
[30] = PIN_ASEBRK_N_ACK, /* ASEBRK#/ACK */
[31] = SH_PFC_PIN_NONE,
} },
{ PINMUX_BIAS_REG("PUPR2", 0xe6060108, "N/A", 0) {
[ 0] = RCAR_GP_PIN(2, 0), /* DU0_DR0 */
[ 1] = RCAR_GP_PIN(2, 1), /* DU0_DR1 */
[ 2] = RCAR_GP_PIN(2, 2), /* DU0_DR2 */
[ 3] = RCAR_GP_PIN(2, 3), /* DU0_DR3 */
[ 4] = RCAR_GP_PIN(2, 4), /* DU0_DR4 */
[ 5] = RCAR_GP_PIN(2, 5), /* DU0_DR5 */
[ 6] = RCAR_GP_PIN(2, 6), /* DU0_DR6 */
[ 7] = RCAR_GP_PIN(2, 7), /* DU0_DR7 */
[ 8] = RCAR_GP_PIN(2, 8), /* DU0_DG0 */
[ 9] = RCAR_GP_PIN(2, 9), /* DU0_DG1 */
[10] = RCAR_GP_PIN(2, 10), /* DU0_DG2 */
[11] = RCAR_GP_PIN(2, 11), /* DU0_DG3 */
[12] = RCAR_GP_PIN(2, 12), /* DU0_DG4 */
[13] = RCAR_GP_PIN(2, 13), /* DU0_DG5 */
[14] = RCAR_GP_PIN(2, 14), /* DU0_DG6 */
[15] = RCAR_GP_PIN(2, 15), /* DU0_DG7 */
[16] = RCAR_GP_PIN(2, 16), /* DU0_DB0 */
[17] = RCAR_GP_PIN(2, 17), /* DU0_DB1 */
[18] = RCAR_GP_PIN(2, 18), /* DU0_DB2 */
[19] = RCAR_GP_PIN(2, 19), /* DU0_DB3 */
[20] = RCAR_GP_PIN(2, 20), /* DU0_DB4 */
[21] = RCAR_GP_PIN(2, 21), /* DU0_DB5 */
[22] = RCAR_GP_PIN(2, 22), /* DU0_DB6 */
[23] = RCAR_GP_PIN(2, 23), /* DU0_DB7 */
[24] = RCAR_GP_PIN(2, 24), /* DU0_DOTCLKIN */
[25] = RCAR_GP_PIN(2, 25), /* DU0_DOTCLKOUT0 */
[26] = RCAR_GP_PIN(2, 26), /* DU0_DOTCLKOUT1 */
[27] = RCAR_GP_PIN(2, 27), /* DU0_EXHSYNC/DU0_HSYNC */
[28] = RCAR_GP_PIN(2, 28), /* DU0_EXVSYNC/DU0_VSYNC */
[29] = RCAR_GP_PIN(2, 29), /* DU0_EXODDF/DU0_ODDF_DISP_CDE */
[30] = RCAR_GP_PIN(2, 30), /* DU0_DISP */
[31] = RCAR_GP_PIN(2, 31), /* DU0_CDE */
} },
{ PINMUX_BIAS_REG("PUPR3", 0xe606010c, "N/A", 0) {
[ 0] = RCAR_GP_PIN(3, 2), /* VI0_DATA1_VI0_B1 */
[ 1] = RCAR_GP_PIN(3, 3), /* VI0_DATA2_VI0_B2 */
[ 2] = RCAR_GP_PIN(3, 4), /* VI0_DATA3_VI0_B3 */
[ 3] = RCAR_GP_PIN(3, 5), /* VI0_DATA4_VI0_B4 */
[ 4] = RCAR_GP_PIN(3, 6), /* VI0_DATA5_VI0_B5 */
[ 5] = RCAR_GP_PIN(3, 7), /* VI0_DATA6_VI0_B6 */
[ 6] = RCAR_GP_PIN(3, 8), /* VI0_DATA7_VI0_B7 */
[ 7] = RCAR_GP_PIN(3, 9), /* VI0_CLKENB */
[ 8] = RCAR_GP_PIN(3, 10), /* VI0_FIELD */
[ 9] = RCAR_GP_PIN(3, 11), /* VI0_HSYNC# */
[10] = RCAR_GP_PIN(3, 12), /* VI0_VSYNC# */
[11] = RCAR_GP_PIN(3, 13), /* ETH_MDIO */
[12] = RCAR_GP_PIN(3, 14), /* ETH_CRS_DV */
[13] = RCAR_GP_PIN(3, 15), /* ETH_RX_ER */
[14] = RCAR_GP_PIN(3, 16), /* ETH_RXD0 */
[15] = RCAR_GP_PIN(3, 17), /* ETH_RXD1 */
[16] = RCAR_GP_PIN(3, 18), /* ETH_LINK */
[17] = RCAR_GP_PIN(3, 19), /* ETH_REF_CLK */
[18] = RCAR_GP_PIN(3, 20), /* ETH_TXD1 */
[19] = RCAR_GP_PIN(3, 21), /* ETH_TX_EN */
[20] = RCAR_GP_PIN(3, 22), /* ETH_MAGIC */
[21] = RCAR_GP_PIN(3, 23), /* ETH_TXD0 */
[22] = RCAR_GP_PIN(3, 24), /* ETH_MDC */
[23] = RCAR_GP_PIN(3, 25), /* HSCIF0_HRX */
[24] = RCAR_GP_PIN(3, 26), /* HSCIF0_HTX */
[25] = RCAR_GP_PIN(3, 27), /* HSCIF0_HCTS# */
[26] = RCAR_GP_PIN(3, 28), /* HSCIF0_HRTS# */
[27] = RCAR_GP_PIN(3, 29), /* HSCIF0_HSCK */
[28] = RCAR_GP_PIN(3, 30), /* I2C0_SCL */
[29] = RCAR_GP_PIN(3, 31), /* I2C0_SDA */
[30] = RCAR_GP_PIN(4, 0), /* I2C1_SCL */
[31] = RCAR_GP_PIN(4, 1), /* I2C1_SDA */
} },
{ PINMUX_BIAS_REG("PUPR4", 0xe6060110, "N/A", 0) {
[ 0] = RCAR_GP_PIN(4, 2), /* MSIOF0_RXD */
[ 1] = RCAR_GP_PIN(4, 3), /* MSIOF0_TXD */
[ 2] = RCAR_GP_PIN(4, 4), /* MSIOF0_SCK */
[ 3] = RCAR_GP_PIN(4, 5), /* MSIOF0_SYNC */
[ 4] = RCAR_GP_PIN(4, 6), /* MSIOF0_SS1 */
[ 5] = RCAR_GP_PIN(4, 7), /* MSIOF0_SS2 */
[ 6] = RCAR_GP_PIN(4, 8), /* HSCIF1_HRX */
[ 7] = RCAR_GP_PIN(4, 9), /* HSCIF1_HTX */
[ 8] = RCAR_GP_PIN(4, 10), /* HSCIF1_HSCK */
[ 9] = RCAR_GP_PIN(4, 11), /* HSCIF1_HCTS# */
[10] = RCAR_GP_PIN(4, 12), /* HSCIF1_HRTS# */
[11] = RCAR_GP_PIN(4, 13), /* SCIF1_SCK */
[12] = RCAR_GP_PIN(4, 14), /* SCIF1_RXD */
[13] = RCAR_GP_PIN(4, 15), /* SCIF1_TXD */
[14] = RCAR_GP_PIN(4, 16), /* SCIF2_RXD */
[15] = RCAR_GP_PIN(4, 17), /* SCIF2_TXD */
[16] = RCAR_GP_PIN(4, 18), /* SCIF2_SCK */
[17] = RCAR_GP_PIN(4, 19), /* SCIF3_SCK */
[18] = RCAR_GP_PIN(4, 20), /* SCIF3_RXD */
[19] = RCAR_GP_PIN(4, 21), /* SCIF3_TXD */
[20] = RCAR_GP_PIN(4, 22), /* I2C2_SCL */
[21] = RCAR_GP_PIN(4, 23), /* I2C2_SDA */
[22] = RCAR_GP_PIN(4, 24), /* SSI_SCK5 */
[23] = RCAR_GP_PIN(4, 25), /* SSI_WS5 */
[24] = RCAR_GP_PIN(4, 26), /* SSI_SDATA5 */
[25] = RCAR_GP_PIN(4, 27), /* SSI_SCK6 */
[26] = RCAR_GP_PIN(4, 28), /* SSI_WS6 */
[27] = RCAR_GP_PIN(4, 29), /* SSI_SDATA6 */
[28] = RCAR_GP_PIN(4, 30), /* SSI_SCK78 */
[29] = RCAR_GP_PIN(4, 31), /* SSI_WS78 */
[30] = RCAR_GP_PIN(5, 0), /* SSI_SDATA7 */
[31] = RCAR_GP_PIN(5, 1), /* SSI_SCK0129 */
} },
{ PINMUX_BIAS_REG("PUPR5", 0xe6060114, "N/A", 0) {
[ 0] = RCAR_GP_PIN(5, 2), /* SSI_WS0129 */
[ 1] = RCAR_GP_PIN(5, 3), /* SSI_SDATA0 */
[ 2] = RCAR_GP_PIN(5, 4), /* SSI_SCK34 */
[ 3] = RCAR_GP_PIN(5, 5), /* SSI_WS34 */
[ 4] = RCAR_GP_PIN(5, 6), /* SSI_SDATA3 */
[ 5] = SH_PFC_PIN_NONE,
[ 6] = SH_PFC_PIN_NONE,
[ 7] = SH_PFC_PIN_NONE,
[ 8] = RCAR_GP_PIN(5, 10), /* SSI_SDATA8 */
[ 9] = RCAR_GP_PIN(5, 11), /* SSI_SCK1 */
[10] = RCAR_GP_PIN(5, 12), /* SSI_WS1 */
[11] = RCAR_GP_PIN(5, 13), /* SSI_SDATA1 */
[12] = RCAR_GP_PIN(5, 14), /* SSI_SCK2 */
[13] = RCAR_GP_PIN(5, 15), /* SSI_WS2 */
[14] = RCAR_GP_PIN(5, 16), /* SSI_SDATA2 */
[15] = RCAR_GP_PIN(5, 17), /* SSI_SCK9 */
[16] = RCAR_GP_PIN(5, 18), /* SSI_WS9 */
[17] = RCAR_GP_PIN(5, 19), /* SSI_SDATA9 */
[18] = RCAR_GP_PIN(5, 20), /* AUDIO_CLKA */
[19] = RCAR_GP_PIN(5, 21), /* AUDIO_CLKB */
[20] = RCAR_GP_PIN(5, 22), /* AUDIO_CLKC */
[21] = RCAR_GP_PIN(5, 23), /* AUDIO_CLKOUT */
[22] = RCAR_GP_PIN(3, 0), /* VI0_CLK */
[23] = RCAR_GP_PIN(3, 1), /* VI0_DATA0_VI0_B0 */
[24] = SH_PFC_PIN_NONE,
[25] = SH_PFC_PIN_NONE,
[26] = SH_PFC_PIN_NONE,
[27] = SH_PFC_PIN_NONE,
[28] = SH_PFC_PIN_NONE,
[29] = SH_PFC_PIN_NONE,
[30] = SH_PFC_PIN_NONE,
[31] = SH_PFC_PIN_NONE,
} },
{ PINMUX_BIAS_REG("PUPR6", 0xe6060118, "N/A", 0) {
[ 0] = RCAR_GP_PIN(6, 1), /* SD0_CMD */
[ 1] = RCAR_GP_PIN(6, 2), /* SD0_DATA0 */
[ 2] = RCAR_GP_PIN(6, 3), /* SD0_DATA1 */
[ 3] = RCAR_GP_PIN(6, 4), /* SD0_DATA2 */
[ 4] = RCAR_GP_PIN(6, 5), /* SD0_DATA3 */
[ 5] = RCAR_GP_PIN(6, 6), /* SD0_CD */
[ 6] = RCAR_GP_PIN(6, 7), /* SD0_WP */
[ 7] = RCAR_GP_PIN(6, 9), /* SD1_CMD */
[ 8] = RCAR_GP_PIN(6, 10), /* SD1_DATA0 */
[ 9] = RCAR_GP_PIN(6, 11), /* SD1_DATA1 */
[10] = RCAR_GP_PIN(6, 12), /* SD1_DATA2 */
[11] = RCAR_GP_PIN(6, 13), /* SD1_DATA3 */
[12] = RCAR_GP_PIN(6, 14), /* SD1_CD */
[13] = RCAR_GP_PIN(6, 15), /* SD1_WP */
[14] = SH_PFC_PIN_NONE,
[15] = RCAR_GP_PIN(6, 17), /* MMC_CMD */
[16] = RCAR_GP_PIN(6, 18), /* MMC_D0 */
[17] = RCAR_GP_PIN(6, 19), /* MMC_D1 */
[18] = RCAR_GP_PIN(6, 20), /* MMC_D2 */
[19] = RCAR_GP_PIN(6, 21), /* MMC_D3 */
[20] = RCAR_GP_PIN(6, 22), /* MMC_D4 */
[21] = RCAR_GP_PIN(6, 23), /* MMC_D5 */
[22] = RCAR_GP_PIN(6, 24), /* MMC_D6 */
[23] = RCAR_GP_PIN(6, 25), /* MMC_D7 */
[24] = SH_PFC_PIN_NONE,
[25] = SH_PFC_PIN_NONE,
[26] = SH_PFC_PIN_NONE,
[27] = SH_PFC_PIN_NONE,
[28] = SH_PFC_PIN_NONE,
[29] = SH_PFC_PIN_NONE,
[30] = SH_PFC_PIN_NONE,
[31] = SH_PFC_PIN_NONE,
} },
{ /* sentinel */ }
};
static const struct soc_device_attribute r8a7794_tdsel[] = {
{ .soc_id = "r8a7794", .revision = "ES1.0" },
{ /* sentinel */ }
@ -5597,6 +5935,8 @@ static int r8a7794_pinmux_soc_init(struct sh_pfc *pfc)
static const struct sh_pfc_soc_operations r8a7794_pinmux_ops = {
.init = r8a7794_pinmux_soc_init,
.pin_to_pocctrl = r8a7794_pin_to_pocctrl,
.get_bias = rcar_pinmux_get_bias,
.set_bias = rcar_pinmux_set_bias,
};
#ifdef CONFIG_PINCTRL_PFC_R8A7745
@ -5615,6 +5955,7 @@ const struct sh_pfc_soc_info r8a7745_pinmux_info = {
.nr_functions = ARRAY_SIZE(pinmux_functions),
.cfg_regs = pinmux_config_regs,
.bias_regs = pinmux_bias_regs,
.pinmux_data = pinmux_data,
.pinmux_data_size = ARRAY_SIZE(pinmux_data),
@ -5637,6 +5978,7 @@ const struct sh_pfc_soc_info r8a7794_pinmux_info = {
.nr_functions = ARRAY_SIZE(pinmux_functions),
.cfg_regs = pinmux_config_regs,
.bias_regs = pinmux_bias_regs,
.pinmux_data = pinmux_data,
.pinmux_data_size = ARRAY_SIZE(pinmux_data),

175
drivers/pinctrl/renesas/pfc-r8a77970.c
View file

@ -19,12 +19,23 @@
#include "sh_pfc.h"
#define CPU_ALL_GP(fn, sfx) \
PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
PORT_GP_28(1, fn, sfx), \
PORT_GP_CFG_17(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
PORT_GP_6(4, fn, sfx), \
PORT_GP_15(5, fn, sfx)
PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PORT_GP_CFG_28(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PORT_GP_CFG_17(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PORT_GP_CFG_6(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PORT_GP_CFG_15(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN)
#define CPU_ALL_NOGP(fn) \
PIN_NOGP_CFG(DU_DOTCLKIN, "DU_DOTCLKIN", fn, SH_PFC_PIN_CFG_PULL_DOWN), \
PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_DOWN), \
PIN_NOGP_CFG(FSCLKST_N, "FSCLKST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP), \
PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP), \
PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP), \
PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP)
/*
* F_() : just information
* FM() : macro for FN_xxx / xxx_MARK
@ -718,8 +729,17 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP8_27_24, DIGRF_CLKEN_OUT),
};
/*
* Pins not associated with a GPIO port.
*/
enum {
GP_ASSIGN_LAST(),
NOGP_ALL(),
};
static const struct sh_pfc_pin pinmux_pins[] = {
PINMUX_GPIO_GP_ALL(),
PINMUX_NOGP_ALL(),
};
/* - AVB0 ------------------------------------------------------------------- */
@ -2496,8 +2516,150 @@ static int r8a77970_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
return -EINVAL;
}
static const struct pinmux_bias_reg pinmux_bias_regs[] = {
{ PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
[ 0] = RCAR_GP_PIN(0, 0), /* DU_DR2 */
[ 1] = RCAR_GP_PIN(0, 1), /* DU_DR3 */
[ 2] = RCAR_GP_PIN(0, 2), /* DU_DR4 */
[ 3] = RCAR_GP_PIN(0, 3), /* DU_DR5 */
[ 4] = RCAR_GP_PIN(0, 4), /* DU_DR6 */
[ 5] = RCAR_GP_PIN(0, 5), /* DU_DR7 */
[ 6] = RCAR_GP_PIN(0, 6), /* DU_DG2 */
[ 7] = RCAR_GP_PIN(0, 7), /* DU_DG3 */
[ 8] = RCAR_GP_PIN(0, 8), /* DU_DG4 */
[ 9] = RCAR_GP_PIN(0, 9), /* DU_DG5 */
[10] = RCAR_GP_PIN(0, 10), /* DU_DG6 */
[11] = RCAR_GP_PIN(0, 11), /* DU_DG7 */
[12] = RCAR_GP_PIN(0, 12), /* DU_DB2 */
[13] = RCAR_GP_PIN(0, 13), /* DU_DB3 */
[14] = RCAR_GP_PIN(0, 14), /* DU_DB4 */
[15] = RCAR_GP_PIN(0, 15), /* DU_DB5 */
[16] = RCAR_GP_PIN(0, 16), /* DU_DB6 */
[17] = RCAR_GP_PIN(0, 17), /* DU_DB7 */
[18] = RCAR_GP_PIN(0, 18), /* DU_DOTCLKOUT */
[19] = RCAR_GP_PIN(0, 19), /* DU_EXHSYNC/DU_HSYNC */
[20] = RCAR_GP_PIN(0, 20), /* DU_EXVSYNC/DU_VSYNC */
[21] = RCAR_GP_PIN(0, 21), /* DU_EXODDF/DU_ODDF/DISP/CDE */
[22] = PIN_DU_DOTCLKIN, /* DU_DOTCLKIN */
[23] = PIN_PRESETOUT_N, /* PRESETOUT# */
[24] = PIN_EXTALR, /* EXTALR */
[25] = PIN_FSCLKST_N, /* FSCLKST# */
[26] = RCAR_GP_PIN(1, 0), /* IRQ0 */
[27] = PIN_TRST_N, /* TRST# */
[28] = PIN_TCK, /* TCK */
[29] = PIN_TMS, /* TMS */
[30] = PIN_TDI, /* TDI */
[31] = RCAR_GP_PIN(2, 0), /* VI0_CLK */
} },
{ PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
[ 0] = RCAR_GP_PIN(2, 1), /* VI0_CLKENB */
[ 1] = RCAR_GP_PIN(2, 2), /* VI0_HSYNC# */
[ 2] = RCAR_GP_PIN(2, 3), /* VI0_VSYNC# */
[ 3] = RCAR_GP_PIN(2, 4), /* VI0_DATA0 */
[ 4] = RCAR_GP_PIN(2, 5), /* VI0_DATA1 */
[ 5] = RCAR_GP_PIN(2, 6), /* VI0_DATA2 */
[ 6] = RCAR_GP_PIN(2, 7), /* VI0_DATA3 */
[ 7] = RCAR_GP_PIN(2, 8), /* VI0_DATA4 */
[ 8] = RCAR_GP_PIN(2, 9), /* VI0_DATA5 */
[ 9] = RCAR_GP_PIN(2, 10), /* VI0_DATA6 */
[10] = RCAR_GP_PIN(2, 11), /* VI0_DATA7 */
[11] = RCAR_GP_PIN(2, 12), /* VI0_DATA8 */
[12] = RCAR_GP_PIN(2, 13), /* VI0_DATA9 */
[13] = RCAR_GP_PIN(2, 14), /* VI0_DATA10 */
[14] = RCAR_GP_PIN(2, 15), /* VI0_DATA11 */
[15] = RCAR_GP_PIN(2, 16), /* VI0_FIELD */
[16] = RCAR_GP_PIN(3, 0), /* VI1_CLK */
[17] = RCAR_GP_PIN(3, 1), /* VI1_CLKENB */
[18] = RCAR_GP_PIN(3, 2), /* VI1_HSYNC# */
[19] = RCAR_GP_PIN(3, 3), /* VI1_VSYNC# */
[20] = RCAR_GP_PIN(3, 4), /* VI1_DATA0 */
[21] = RCAR_GP_PIN(3, 5), /* VI1_DATA1 */
[22] = RCAR_GP_PIN(3, 6), /* VI1_DATA2 */
[23] = RCAR_GP_PIN(3, 7), /* VI1_DATA3 */
[24] = RCAR_GP_PIN(3, 8), /* VI1_DATA4 */
[25] = RCAR_GP_PIN(3, 9), /* VI1_DATA5 */
[26] = RCAR_GP_PIN(3, 10), /* VI1_DATA6 */
[27] = RCAR_GP_PIN(3, 11), /* VI1_DATA7 */
[28] = RCAR_GP_PIN(3, 12), /* VI1_DATA8 */
[29] = RCAR_GP_PIN(3, 13), /* VI1_DATA9 */
[30] = RCAR_GP_PIN(3, 14), /* VI1_DATA10 */
[31] = RCAR_GP_PIN(3, 15), /* VI1_DATA11 */
} },
{ PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
[ 0] = RCAR_GP_PIN(3, 16), /* VI1_FIELD */
[ 1] = RCAR_GP_PIN(4, 0), /* SCL0 */
[ 2] = RCAR_GP_PIN(4, 1), /* SDA0 */
[ 3] = RCAR_GP_PIN(4, 2), /* SCL1 */
[ 4] = RCAR_GP_PIN(4, 3), /* SDA1 */
[ 5] = RCAR_GP_PIN(4, 4), /* SCL2 */
[ 6] = RCAR_GP_PIN(4, 5), /* SDA2 */
[ 7] = RCAR_GP_PIN(1, 1), /* AVB0_RX_CTL */
[ 8] = RCAR_GP_PIN(1, 2), /* AVB0_RXC */
[ 9] = RCAR_GP_PIN(1, 3), /* AVB0_RD0 */
[10] = RCAR_GP_PIN(1, 4), /* AVB0_RD1 */
[11] = RCAR_GP_PIN(1, 5), /* AVB0_RD2 */
[12] = RCAR_GP_PIN(1, 6), /* AVB0_RD3 */
[13] = RCAR_GP_PIN(1, 7), /* AVB0_TX_CTL */
[14] = RCAR_GP_PIN(1, 8), /* AVB0_TXC */
[15] = RCAR_GP_PIN(1, 9), /* AVB0_TD0 */
[16] = RCAR_GP_PIN(1, 10), /* AVB0_TD1 */
[17] = RCAR_GP_PIN(1, 11), /* AVB0_TD2 */
[18] = RCAR_GP_PIN(1, 12), /* AVB0_TD3 */
[19] = RCAR_GP_PIN(1, 13), /* AVB0_TXCREFCLK */
[20] = RCAR_GP_PIN(1, 14), /* AVB0_MDIO */
[21] = RCAR_GP_PIN(1, 15), /* AVB0_MDC */
[22] = RCAR_GP_PIN(1, 16), /* AVB0_MAGIC */
[23] = RCAR_GP_PIN(1, 17), /* AVB0_PHY_INT */
[24] = RCAR_GP_PIN(1, 18), /* AVB0_LINK */
[25] = RCAR_GP_PIN(1, 19), /* AVB0_AVTP_MATCH */
[26] = RCAR_GP_PIN(1, 20), /* AVB0_AVTP_CAPTURE */
[27] = RCAR_GP_PIN(1, 21), /* CANFD0_TX_A */
[28] = RCAR_GP_PIN(1, 22), /* CANFD0_RX_A */
[29] = RCAR_GP_PIN(1, 23), /* CANFD1_TX */
[30] = RCAR_GP_PIN(1, 24), /* CANFD1_RX */
[31] = RCAR_GP_PIN(1, 25), /* CANFD_CLK */
} },
{ PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
[ 0] = RCAR_GP_PIN(5, 0), /* QSPI0_SPCLK */
[ 1] = RCAR_GP_PIN(5, 1), /* QSPI0_MOSI_IO0 */
[ 2] = RCAR_GP_PIN(5, 2), /* QSPI0_MISO_IO1 */
[ 3] = RCAR_GP_PIN(5, 3), /* QSPI0_IO2 */
[ 4] = RCAR_GP_PIN(5, 4), /* QSPI0_IO3 */
[ 5] = RCAR_GP_PIN(5, 5), /* QSPI0_SSL */
[ 6] = RCAR_GP_PIN(5, 6), /* QSPI1_SPCLK */
[ 7] = RCAR_GP_PIN(5, 7), /* QSPI1_MOSI_IO0 */
[ 8] = RCAR_GP_PIN(5, 8), /* QSPI1_MISO_IO1 */
[ 9] = RCAR_GP_PIN(5, 9), /* QSPI1_IO2 */
[10] = RCAR_GP_PIN(5, 10), /* QSPI1_IO3 */
[11] = RCAR_GP_PIN(5, 11), /* QSPI1_SSL */
[12] = RCAR_GP_PIN(5, 12), /* RPC_RESET# */
[13] = RCAR_GP_PIN(5, 13), /* RPC_WP# */
[14] = RCAR_GP_PIN(5, 14), /* RPC_INT# */
[15] = RCAR_GP_PIN(1, 26), /* DIGRF_CLKIN */
[16] = RCAR_GP_PIN(1, 27), /* DIGRF_CLKOUT */
[17] = SH_PFC_PIN_NONE,
[18] = SH_PFC_PIN_NONE,
[19] = SH_PFC_PIN_NONE,
[20] = SH_PFC_PIN_NONE,
[21] = SH_PFC_PIN_NONE,
[22] = SH_PFC_PIN_NONE,
[23] = SH_PFC_PIN_NONE,
[24] = SH_PFC_PIN_NONE,
[25] = SH_PFC_PIN_NONE,
[26] = SH_PFC_PIN_NONE,
[27] = SH_PFC_PIN_NONE,
[28] = SH_PFC_PIN_NONE,
[29] = SH_PFC_PIN_NONE,
[30] = SH_PFC_PIN_NONE,
[31] = SH_PFC_PIN_NONE,
} },
{ /* sentinel */ }
};
static const struct sh_pfc_soc_operations pinmux_ops = {
.pin_to_pocctrl = r8a77970_pin_to_pocctrl,
.get_bias = rcar_pinmux_get_bias,
.set_bias = rcar_pinmux_set_bias,
};
const struct sh_pfc_soc_info r8a77970_pinmux_info = {
@ -2515,6 +2677,7 @@ const struct sh_pfc_soc_info r8a77970_pinmux_info = {
.nr_functions = ARRAY_SIZE(pinmux_functions),
.cfg_regs = pinmux_config_regs,
.bias_regs = pinmux_bias_regs,
.ioctrl_regs = pinmux_ioctrl_regs,
.pinmux_data = pinmux_data,

209
drivers/pinctrl/renesas/pfc-r8a77980.c
View file

@ -19,12 +19,23 @@
#include "sh_pfc.h"
#define CPU_ALL_GP(fn, sfx) \
PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
PORT_GP_28(1, fn, sfx), \
PORT_GP_CFG_30(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
PORT_GP_25(4, fn, sfx), \
PORT_GP_15(5, fn, sfx)
PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PORT_GP_CFG_28(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PORT_GP_CFG_30(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PORT_GP_CFG_25(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PORT_GP_CFG_15(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN)
#define CPU_ALL_NOGP(fn) \
PIN_NOGP_CFG(DCUTCK_LPDCLK, "DCUTCK_LPDCLK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PIN_NOGP_CFG(DCUTDI_LPDI, "DCUTDI_LPDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PIN_NOGP_CFG(DCUTMS, "DCUTMS", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PIN_NOGP_CFG(DCUTRST_N, "DCUTRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PIN_NOGP_CFG(DU_DOTCLKIN, "DU_DOTCLKIN", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PIN_NOGP_CFG(FSCLKST, "FSCLKST", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PIN_NOGP_CFG(FSCLKST_N, "FSCLKST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN)
/*
* F_() : just information
@ -830,8 +841,17 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP10_19_16, FSO_TOE_N),
};
/*
* Pins not associated with a GPIO port.
*/
enum {
GP_ASSIGN_LAST(),
NOGP_ALL(),
};
static const struct sh_pfc_pin pinmux_pins[] = {
PINMUX_GPIO_GP_ALL(),
PINMUX_NOGP_ALL(),
};
/* - AVB -------------------------------------------------------------------- */
@ -2945,8 +2965,184 @@ static int r8a77980_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
return -EINVAL;
}
static const struct pinmux_bias_reg pinmux_bias_regs[] = {
{ PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
[ 0] = RCAR_GP_PIN(0, 0), /* DU_DR2 */
[ 1] = RCAR_GP_PIN(0, 1), /* DU_DR3 */
[ 2] = RCAR_GP_PIN(0, 2), /* DU_DR4 */
[ 3] = RCAR_GP_PIN(0, 3), /* DU_DR5 */
[ 4] = RCAR_GP_PIN(0, 4), /* DU_DR6 */
[ 5] = RCAR_GP_PIN(0, 5), /* DU_DR7 */
[ 6] = RCAR_GP_PIN(0, 6), /* DU_DG2 */
[ 7] = RCAR_GP_PIN(0, 7), /* DU_DG3 */
[ 8] = RCAR_GP_PIN(0, 8), /* DU_DG4 */
[ 9] = RCAR_GP_PIN(0, 9), /* DU_DG5 */
[10] = RCAR_GP_PIN(0, 10), /* DU_DG6 */
[11] = RCAR_GP_PIN(0, 11), /* DU_DG7 */
[12] = RCAR_GP_PIN(0, 12), /* DU_DB2 */
[13] = RCAR_GP_PIN(0, 13), /* DU_DB3 */
[14] = RCAR_GP_PIN(0, 14), /* DU_DB4 */
[15] = RCAR_GP_PIN(0, 15), /* DU_DB5 */
[16] = RCAR_GP_PIN(0, 16), /* DU_DB6 */
[17] = RCAR_GP_PIN(0, 17), /* DU_DB7 */
[18] = RCAR_GP_PIN(0, 18), /* DU_DOTCLKOUT */
[19] = RCAR_GP_PIN(0, 19), /* DU_EXHSYNC/DU_HSYNC */
[20] = RCAR_GP_PIN(0, 20), /* DU_EXVSYNC/DU_VSYNC */
[21] = RCAR_GP_PIN(0, 21), /* DU_EXODDF/DU_ODDF/DISP/CDE */
[22] = SH_PFC_PIN_NONE,
[23] = SH_PFC_PIN_NONE,
[24] = PIN_DU_DOTCLKIN, /* DU_DOTCLKIN */
[25] = SH_PFC_PIN_NONE,
[26] = PIN_PRESETOUT_N, /* PRESETOUT# */
[27] = SH_PFC_PIN_NONE,
[28] = SH_PFC_PIN_NONE,
[29] = SH_PFC_PIN_NONE,
[30] = PIN_EXTALR, /* EXTALR */
[31] = PIN_FSCLKST_N, /* FSCLKST# */
} },
{ PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
[ 0] = PIN_FSCLKST, /* FSCLKST */
[ 1] = SH_PFC_PIN_NONE,
[ 2] = RCAR_GP_PIN(1, 0), /* IRQ0 */
[ 3] = PIN_DCUTRST_N, /* DCUTRST# */
[ 4] = PIN_DCUTCK_LPDCLK, /* DCUTCK_LPDCLK */
[ 5] = PIN_DCUTMS, /* DCUTMS */
[ 6] = PIN_DCUTDI_LPDI, /* DCUTDI_LPDI */
[ 7] = SH_PFC_PIN_NONE,
[ 8] = RCAR_GP_PIN(2, 0), /* VI0_CLK */
[ 9] = RCAR_GP_PIN(2, 1), /* VI0_CLKENB */
[10] = RCAR_GP_PIN(2, 2), /* VI0_HSYNC# */
[11] = RCAR_GP_PIN(2, 3), /* VI0_VSYNC# */
[12] = RCAR_GP_PIN(2, 4), /* VI0_DATA0 */
[13] = RCAR_GP_PIN(2, 5), /* VI0_DATA1 */
[14] = RCAR_GP_PIN(2, 6), /* VI0_DATA2 */
[15] = RCAR_GP_PIN(2, 7), /* VI0_DATA3 */
[16] = RCAR_GP_PIN(2, 8), /* VI0_DATA4 */
[17] = RCAR_GP_PIN(2, 9), /* VI0_DATA5 */
[18] = RCAR_GP_PIN(2, 10), /* VI0_DATA6 */
[19] = RCAR_GP_PIN(2, 11), /* VI0_DATA7 */
[20] = RCAR_GP_PIN(2, 12), /* VI0_DATA8 */
[21] = RCAR_GP_PIN(2, 13), /* VI0_DATA9 */
[22] = RCAR_GP_PIN(2, 14), /* VI0_DATA10 */
[23] = RCAR_GP_PIN(2, 15), /* VI0_DATA11 */
[24] = RCAR_GP_PIN(2, 16), /* VI0_FIELD */
[25] = RCAR_GP_PIN(3, 0), /* VI1_CLK */
[26] = RCAR_GP_PIN(3, 1), /* VI1_CLKENB */
[27] = RCAR_GP_PIN(3, 2), /* VI1_HSYNC# */
[28] = RCAR_GP_PIN(3, 3), /* VI1_VSYNC# */
[29] = RCAR_GP_PIN(3, 4), /* VI1_DATA0 */
[30] = RCAR_GP_PIN(3, 5), /* VI1_DATA1 */
[31] = RCAR_GP_PIN(3, 6), /* VI1_DATA2 */
} },
{ PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
[ 0] = RCAR_GP_PIN(3, 7), /* VI1_DATA3 */
[ 1] = RCAR_GP_PIN(3, 8), /* VI1_DATA4 */
[ 2] = RCAR_GP_PIN(3, 9), /* VI1_DATA5 */
[ 3] = RCAR_GP_PIN(3, 10), /* VI1_DATA6 */
[ 4] = RCAR_GP_PIN(3, 11), /* VI1_DATA7 */
[ 5] = RCAR_GP_PIN(3, 12), /* VI1_DATA8 */
[ 6] = RCAR_GP_PIN(3, 13), /* VI1_DATA9 */
[ 7] = RCAR_GP_PIN(3, 14), /* VI1_DATA10 */
[ 8] = RCAR_GP_PIN(3, 15), /* VI1_DATA11 */
[ 9] = RCAR_GP_PIN(3, 16), /* VI1_FIELD */
[10] = RCAR_GP_PIN(4, 0), /* SCL0 */
[11] = RCAR_GP_PIN(4, 1), /* SDA0 */
[12] = RCAR_GP_PIN(4, 2), /* SCL1 */
[13] = RCAR_GP_PIN(4, 3), /* SDA1 */
[14] = RCAR_GP_PIN(4, 4), /* SCL2 */
[15] = RCAR_GP_PIN(4, 5), /* SDA2 */
[16] = RCAR_GP_PIN(1, 1), /* AVB_RX_CTL */
[17] = RCAR_GP_PIN(1, 2), /* AVB_RXC */
[18] = RCAR_GP_PIN(1, 3), /* AVB_RD0 */
[19] = RCAR_GP_PIN(1, 4), /* AVB_RD1 */
[20] = RCAR_GP_PIN(1, 5), /* AVB_RD2 */
[21] = RCAR_GP_PIN(1, 6), /* AVB_RD3 */
[22] = RCAR_GP_PIN(1, 7), /* AVB_TX_CTL */
[23] = RCAR_GP_PIN(1, 8), /* AVB_TXC */
[24] = RCAR_GP_PIN(1, 9), /* AVB_TD0 */
[25] = RCAR_GP_PIN(1, 10), /* AVB_TD1 */
[26] = RCAR_GP_PIN(1, 11), /* AVB_TD2 */
[27] = RCAR_GP_PIN(1, 12), /* AVB_TD3 */
[28] = RCAR_GP_PIN(1, 13), /* AVB_TXCREFCLK */
[29] = RCAR_GP_PIN(1, 14), /* AVB_MDIO */
[30] = RCAR_GP_PIN(1, 15), /* AVB_MDC */
[31] = RCAR_GP_PIN(1, 16), /* AVB_MAGIC */
} },
{ PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
[ 0] = RCAR_GP_PIN(1, 17), /* AVB_PHY_INT */
[ 1] = RCAR_GP_PIN(1, 18), /* AVB_LINK */
[ 2] = RCAR_GP_PIN(1, 19), /* AVB_AVTP_MATCH */
[ 3] = RCAR_GP_PIN(1, 20), /* AVTP_CAPTURE */
[ 4] = RCAR_GP_PIN(4, 6), /* GETHER_RX_CTL */
[ 5] = RCAR_GP_PIN(4, 7), /* GETHER_RXC */
[ 6] = RCAR_GP_PIN(4, 8), /* GETHER_RD0 */
[ 7] = RCAR_GP_PIN(4, 9), /* GETHER_RD1 */
[ 8] = RCAR_GP_PIN(4, 10), /* GETHER_RD2 */
[ 9] = RCAR_GP_PIN(4, 11), /* GETHER_RD3 */
[10] = RCAR_GP_PIN(4, 12), /* GETHER_TX_CTL */
[11] = RCAR_GP_PIN(4, 13), /* GETHER_TXC */
[12] = RCAR_GP_PIN(4, 14), /* GETHER_TD0 */
[13] = RCAR_GP_PIN(4, 15), /* GETHER_TD1 */
[14] = RCAR_GP_PIN(4, 16), /* GETHER_TD2 */
[15] = RCAR_GP_PIN(4, 17), /* GETHER_TD3 */
[16] = RCAR_GP_PIN(4, 18), /* GETHER_TXCREFCLK */
[17] = RCAR_GP_PIN(4, 19), /* GETHER_TXCREFCLK_MEGA */
[18] = RCAR_GP_PIN(4, 20), /* GETHER_MDIO_A */
[19] = RCAR_GP_PIN(4, 21), /* GETHER_MDC_A */
[20] = RCAR_GP_PIN(4, 22), /* GETHER_MAGIC */
[21] = RCAR_GP_PIN(4, 23), /* GETHER_PHY_INT_A */
[22] = RCAR_GP_PIN(4, 24), /* GETHER_LINK_A */
[23] = RCAR_GP_PIN(1, 21), /* CANFD0_TX_A */
[24] = RCAR_GP_PIN(1, 22), /* CANFD0_RX_A */
[25] = RCAR_GP_PIN(1, 23), /* CANFD1_TX */
[26] = RCAR_GP_PIN(1, 24), /* CANFD1_RX */
[27] = RCAR_GP_PIN(1, 25), /* CAN_CLK_A */
[28] = RCAR_GP_PIN(5, 0), /* QSPI0_SPCLK */
[29] = RCAR_GP_PIN(5, 1), /* QSPI0_MOSI_IO0 */
[30] = RCAR_GP_PIN(5, 2), /* QSPI0_MISO_IO1 */
[31] = RCAR_GP_PIN(5, 3), /* QSPI0_IO2 */
} },
{ PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
[ 0] = RCAR_GP_PIN(5, 4), /* QSPI0_IO3 */
[ 1] = RCAR_GP_PIN(5, 5), /* QSPI0_SSL */
[ 2] = RCAR_GP_PIN(5, 6), /* QSPI1_SPCLK */
[ 3] = RCAR_GP_PIN(5, 7), /* QSPI1_MOSI_IO0 */
[ 4] = RCAR_GP_PIN(5, 8), /* QSPI1_MISO_IO1 */
[ 5] = RCAR_GP_PIN(5, 9), /* QSPI1_IO2 */
[ 6] = RCAR_GP_PIN(5, 10), /* QSPI1_IO3 */
[ 7] = RCAR_GP_PIN(5, 11), /* QSPI1_SSL */
[ 8] = RCAR_GP_PIN(5, 12), /* RPC_RESET# */
[ 9] = RCAR_GP_PIN(5, 13), /* RPC_WP# */
[10] = RCAR_GP_PIN(5, 14), /* RPC_INT# */
[11] = RCAR_GP_PIN(1, 26), /* DIGRF_CLKIN */
[12] = RCAR_GP_PIN(1, 27), /* DIGRF_CLKOUT */
[13] = RCAR_GP_PIN(2, 17), /* IRQ4 */
[14] = RCAR_GP_PIN(2, 18), /* IRQ5 */
[15] = RCAR_GP_PIN(2, 25), /* SCL3 */
[16] = RCAR_GP_PIN(2, 26), /* SDA3 */
[17] = RCAR_GP_PIN(2, 19), /* MSIOF0_RXD */
[18] = RCAR_GP_PIN(2, 20), /* MSIOF0_TXD */
[19] = RCAR_GP_PIN(2, 21), /* MSIOF0_SCK */
[20] = RCAR_GP_PIN(2, 22), /* MSIOF0_SYNC */
[21] = RCAR_GP_PIN(2, 23), /* MSIOF0_SS1 */
[22] = RCAR_GP_PIN(2, 24), /* MSIOF0_SS2 */
[23] = RCAR_GP_PIN(2, 27), /* FSO_CFE_0# */
[24] = RCAR_GP_PIN(2, 28), /* FSO_CFE_1# */
[25] = RCAR_GP_PIN(2, 29), /* FSO_TOE# */
[26] = SH_PFC_PIN_NONE,
[27] = SH_PFC_PIN_NONE,
[28] = SH_PFC_PIN_NONE,
[29] = SH_PFC_PIN_NONE,
[30] = SH_PFC_PIN_NONE,
[31] = SH_PFC_PIN_NONE,
} },
{ /* sentinel */ }
};
static const struct sh_pfc_soc_operations pinmux_ops = {
.pin_to_pocctrl = r8a77980_pin_to_pocctrl,
.get_bias = rcar_pinmux_get_bias,
.set_bias = rcar_pinmux_set_bias,
};
const struct sh_pfc_soc_info r8a77980_pinmux_info = {
@ -2964,6 +3160,7 @@ const struct sh_pfc_soc_info r8a77980_pinmux_info = {
.nr_functions = ARRAY_SIZE(pinmux_functions),
.cfg_regs = pinmux_config_regs,
.bias_regs = pinmux_bias_regs,
.ioctrl_regs = pinmux_ioctrl_regs,
.pinmux_data = pinmux_data,