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ARM: dts: Group omap3 CM_CLKSEL_WKUP clocks
The clksel related registers on omap3 cause unique_unit_address and node_name_chars_strict warnings with the W=1 or W=2 make flags enabled. With the clock drivers updated, we can now avoid most of these warnings by grouping the TI component clocks using the TI clksel binding, and with the use of clock-output-names property to avoid non-standard node names for the clocks. Signed-off-by: Tony Lindgren <tony@atomide.com>
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23347c90e2
commit
2f7c426df6
2 changed files with 37 additions and 22 deletions
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@ -168,13 +168,20 @@ dpll5_m2_d20_ck: dpll5_m2_d20_ck {
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clock-div = <20>;
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};
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usim_mux_fck: usim_mux_fck@c40 {
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#clock-cells = <0>;
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compatible = "ti,composite-mux-clock";
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clocks = <&sys_ck>, <&sys_d2_ck>, <&omap_96m_d2_fck>, <&omap_96m_d4_fck>, <&omap_96m_d8_fck>, <&omap_96m_d10_fck>, <&dpll5_m2_d4_ck>, <&dpll5_m2_d8_ck>, <&dpll5_m2_d16_ck>, <&dpll5_m2_d20_ck>;
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ti,bit-shift = <3>;
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reg = <0x0c40>;
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ti,index-starts-at-one;
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clock@c40 {
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compatible = "ti,clksel";
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reg = <0xc40>;
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#clock-cells = <2>;
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#address-cells = <0>;
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usim_mux_fck: clock-usim-mux-fck {
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#clock-cells = <0>;
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compatible = "ti,composite-mux-clock";
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clock-output-names = "usim_mux_fck";
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clocks = <&sys_ck>, <&sys_d2_ck>, <&omap_96m_d2_fck>, <&omap_96m_d4_fck>, <&omap_96m_d8_fck>, <&omap_96m_d10_fck>, <&dpll5_m2_d4_ck>, <&dpll5_m2_d8_ck>, <&dpll5_m2_d16_ck>, <&dpll5_m2_d20_ck>;
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ti,bit-shift = <3>;
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ti,index-starts-at-one;
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};
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};
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usim_fck: usim_fck {
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@ -617,14 +617,29 @@ gpt11_mux_fck: clock-gpt11-mux-fck {
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};
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};
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rm_ick: rm_ick@c40 {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&l4_ick>;
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ti,bit-shift = <1>;
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ti,max-div = <3>;
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reg = <0x0c40>;
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ti,index-starts-at-one;
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/* CM_CLKSEL_WKUP */
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clock@c40 {
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compatible = "ti,clksel";
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reg = <0xc40>;
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#clock-cells = <2>;
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#address-cells = <0>;
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rm_ick: clock-rm-ick {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clock-output-names = "rm_ick";
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clocks = <&l4_ick>;
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ti,bit-shift = <1>;
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ti,max-div = <3>;
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ti,index-starts-at-one;
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};
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gpt1_mux_fck: clock-gpt1-mux-fck {
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#clock-cells = <0>;
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compatible = "ti,composite-mux-clock";
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clock-output-names = "gpt1_mux_fck";
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clocks = <&omap_32k_fck>, <&sys_ck>;
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};
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};
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/* CM_FCLKEN1_CORE */
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@ -1053,13 +1068,6 @@ wdt2_fck: clock-wdt2-fck {
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};
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};
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gpt1_mux_fck: gpt1_mux_fck@c40 {
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#clock-cells = <0>;
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compatible = "ti,composite-mux-clock";
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clocks = <&omap_32k_fck>, <&sys_ck>;
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reg = <0x0c40>;
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};
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gpt1_fck: gpt1_fck {
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#clock-cells = <0>;
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compatible = "ti,composite-clock";
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