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perf/x86/intel: Add support for PEBSv3 profiling
PEBSv3 is the same as the existing PEBSv2 used on Haswell, but it adds a new TSC field. Add support to the generic PEBS handler to handle the new format, and overwrite the perf time stamp using the new native_sched_clock_from_tsc(). Right now the time stamp is just slightly more accurate, as it is nearer the actual event trigger point. With the PEBS threshold > 1 patchkit it will be much more accurate, avoid the problems with MMAP mismatches earlier. The accurate time stamping is only implemented for the default trace clock for now. v2: Use _skl prefix. Check for default clock_id. Signed-off-by: Andi Kleen <ak@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: eranian@google.com Link: http://lkml.kernel.org/r/1431285767-27027-3-git-send-email-andi@firstfloor.org Signed-off-by: Ingo Molnar <mingo@kernel.org>
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1 changed files with 33 additions and 3 deletions
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@ -224,6 +224,19 @@ union hsw_tsx_tuning {
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#define PEBS_HSW_TSX_FLAGS 0xff00000000ULL
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/* Same as HSW, plus TSC */
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struct pebs_record_skl {
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u64 flags, ip;
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u64 ax, bx, cx, dx;
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u64 si, di, bp, sp;
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u64 r8, r9, r10, r11;
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u64 r12, r13, r14, r15;
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u64 status, dla, dse, lat;
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u64 real_ip, tsx_tuning;
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u64 tsc;
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};
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void init_debug_store_on_cpu(int cpu)
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{
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struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
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@ -885,7 +898,7 @@ static int intel_pmu_pebs_fixup_ip(struct pt_regs *regs)
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return 0;
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}
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static inline u64 intel_hsw_weight(struct pebs_record_hsw *pebs)
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static inline u64 intel_hsw_weight(struct pebs_record_skl *pebs)
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{
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if (pebs->tsx_tuning) {
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union hsw_tsx_tuning tsx = { .value = pebs->tsx_tuning };
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@ -894,7 +907,7 @@ static inline u64 intel_hsw_weight(struct pebs_record_hsw *pebs)
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return 0;
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}
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static inline u64 intel_hsw_transaction(struct pebs_record_hsw *pebs)
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static inline u64 intel_hsw_transaction(struct pebs_record_skl *pebs)
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{
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u64 txn = (pebs->tsx_tuning & PEBS_HSW_TSX_FLAGS) >> 32;
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@ -918,7 +931,7 @@ static void setup_pebs_sample_data(struct perf_event *event,
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* unconditionally access the 'extra' entries.
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*/
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struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
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struct pebs_record_hsw *pebs = __pebs;
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struct pebs_record_skl *pebs = __pebs;
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u64 sample_type;
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int fll, fst, dsrc;
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int fl = event->hw.flags;
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@ -1016,6 +1029,16 @@ static void setup_pebs_sample_data(struct perf_event *event,
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data->txn = intel_hsw_transaction(pebs);
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}
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/*
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* v3 supplies an accurate time stamp, so we use that
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* for the time stamp.
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*
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* We can only do this for the default trace clock.
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*/
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if (x86_pmu.intel_cap.pebs_format >= 3 &&
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event->attr.use_clockid == 0)
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data->time = native_sched_clock_from_tsc(pebs->tsc);
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if (has_branch_stack(event))
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data->br_stack = &cpuc->lbr_stack;
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}
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@ -1245,6 +1268,13 @@ void __init intel_ds_init(void)
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x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
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break;
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case 3:
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pr_cont("PEBS fmt3%c, ", pebs_type);
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x86_pmu.pebs_record_size =
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sizeof(struct pebs_record_skl);
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x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
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break;
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default:
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printk(KERN_CONT "no PEBS fmt%d%c, ", format, pebs_type);
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x86_pmu.pebs = 0;
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