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i2c: designware: Add driver support for Wangxun 10Gb NIC
Wangxun 10Gb ethernet chip is connected to Designware I2C, to communicate with SFP. Introduce the property "wx,i2c-snps-model" to match device data for Wangxun in software node case. Since IO resource was mapped on the ethernet driver, add a model quirk to get regmap from parent device. The exists IP limitations are dealt as workarounds: - IP does not support interrupt mode, it works on polling mode. - Additionally set FIFO depth address the chip issue. Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com> Reviewed-by: Piotr Raczynski <piotr.raczynski@intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Signed-off-by: Wolfram Sang <wsa@kernel.org>
This commit is contained in:
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4f5d68c859
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2f8d1ed793
4 changed files with 111 additions and 5 deletions
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@ -575,6 +575,14 @@ int i2c_dw_set_fifo_size(struct dw_i2c_dev *dev)
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unsigned int param;
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unsigned int param;
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int ret;
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int ret;
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/* DW_IC_COMP_PARAM_1 not implement for IP issue */
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if ((dev->flags & MODEL_MASK) == MODEL_WANGXUN_SP) {
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dev->tx_fifo_depth = TXGBE_TX_FIFO_DEPTH;
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dev->rx_fifo_depth = TXGBE_RX_FIFO_DEPTH;
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return 0;
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}
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/*
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/*
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* Try to detect the FIFO depth if not set by interface driver,
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* Try to detect the FIFO depth if not set by interface driver,
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* the depth could be from 2 to 256 from HW spec.
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* the depth could be from 2 to 256 from HW spec.
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@ -303,6 +303,7 @@ struct dw_i2c_dev {
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#define MODEL_MSCC_OCELOT BIT(8)
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#define MODEL_MSCC_OCELOT BIT(8)
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#define MODEL_BAIKAL_BT1 BIT(9)
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#define MODEL_BAIKAL_BT1 BIT(9)
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#define MODEL_AMD_NAVI_GPU BIT(10)
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#define MODEL_AMD_NAVI_GPU BIT(10)
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#define MODEL_WANGXUN_SP BIT(11)
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#define MODEL_MASK GENMASK(11, 8)
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#define MODEL_MASK GENMASK(11, 8)
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/*
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/*
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@ -312,6 +313,9 @@ struct dw_i2c_dev {
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#define AMD_UCSI_INTR_REG 0x474
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#define AMD_UCSI_INTR_REG 0x474
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#define AMD_UCSI_INTR_EN 0xd
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#define AMD_UCSI_INTR_EN 0xd
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#define TXGBE_TX_FIFO_DEPTH 4
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#define TXGBE_RX_FIFO_DEPTH 0
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struct i2c_dw_semaphore_callbacks {
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struct i2c_dw_semaphore_callbacks {
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int (*probe)(struct dw_i2c_dev *dev);
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int (*probe)(struct dw_i2c_dev *dev);
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void (*remove)(struct dw_i2c_dev *dev);
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void (*remove)(struct dw_i2c_dev *dev);
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@ -354,6 +354,68 @@ static int amd_i2c_dw_xfer_quirk(struct i2c_adapter *adap, struct i2c_msg *msgs,
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return 0;
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return 0;
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}
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}
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static int i2c_dw_poll_tx_empty(struct dw_i2c_dev *dev)
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{
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u32 val;
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return regmap_read_poll_timeout(dev->map, DW_IC_RAW_INTR_STAT, val,
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val & DW_IC_INTR_TX_EMPTY,
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100, 1000);
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}
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static int i2c_dw_poll_rx_full(struct dw_i2c_dev *dev)
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{
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u32 val;
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return regmap_read_poll_timeout(dev->map, DW_IC_RAW_INTR_STAT, val,
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val & DW_IC_INTR_RX_FULL,
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100, 1000);
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}
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static int txgbe_i2c_dw_xfer_quirk(struct i2c_adapter *adap, struct i2c_msg *msgs,
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int num_msgs)
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{
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struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
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int msg_idx, buf_len, data_idx, ret;
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unsigned int val, stop = 0;
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u8 *buf;
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dev->msgs = msgs;
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dev->msgs_num = num_msgs;
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i2c_dw_xfer_init(dev);
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regmap_write(dev->map, DW_IC_INTR_MASK, 0);
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for (msg_idx = 0; msg_idx < num_msgs; msg_idx++) {
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buf = msgs[msg_idx].buf;
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buf_len = msgs[msg_idx].len;
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for (data_idx = 0; data_idx < buf_len; data_idx++) {
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if (msg_idx == num_msgs - 1 && data_idx == buf_len - 1)
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stop |= BIT(9);
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if (msgs[msg_idx].flags & I2C_M_RD) {
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regmap_write(dev->map, DW_IC_DATA_CMD, 0x100 | stop);
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ret = i2c_dw_poll_rx_full(dev);
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if (ret)
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return ret;
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regmap_read(dev->map, DW_IC_DATA_CMD, &val);
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buf[data_idx] = val;
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} else {
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ret = i2c_dw_poll_tx_empty(dev);
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if (ret)
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return ret;
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regmap_write(dev->map, DW_IC_DATA_CMD,
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buf[data_idx] | stop);
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}
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}
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}
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return num_msgs;
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}
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/*
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/*
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* Initiate (and continue) low level master read/write transaction.
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* Initiate (and continue) low level master read/write transaction.
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* This function is only called from i2c_dw_isr, and pumping i2c_msg
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* This function is only called from i2c_dw_isr, and pumping i2c_msg
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@ -559,13 +621,19 @@ i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
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pm_runtime_get_sync(dev->dev);
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pm_runtime_get_sync(dev->dev);
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/*
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/*
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* Initiate I2C message transfer when AMD NAVI GPU card is enabled,
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* Initiate I2C message transfer when polling mode is enabled,
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* As it is polling based transfer mechanism, which does not support
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* As it is polling based transfer mechanism, which does not support
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* interrupt based functionalities of existing DesignWare driver.
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* interrupt based functionalities of existing DesignWare driver.
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*/
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*/
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if ((dev->flags & MODEL_MASK) == MODEL_AMD_NAVI_GPU) {
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switch (dev->flags & MODEL_MASK) {
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case MODEL_AMD_NAVI_GPU:
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ret = amd_i2c_dw_xfer_quirk(adap, msgs, num);
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ret = amd_i2c_dw_xfer_quirk(adap, msgs, num);
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goto done_nolock;
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goto done_nolock;
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case MODEL_WANGXUN_SP:
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ret = txgbe_i2c_dw_xfer_quirk(adap, msgs, num);
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goto done_nolock;
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default:
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break;
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}
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}
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reinit_completion(&dev->cmd_complete);
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reinit_completion(&dev->cmd_complete);
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@ -848,7 +916,7 @@ static int i2c_dw_init_recovery_info(struct dw_i2c_dev *dev)
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return 0;
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return 0;
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}
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}
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static int amd_i2c_adap_quirk(struct dw_i2c_dev *dev)
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static int i2c_dw_poll_adap_quirk(struct dw_i2c_dev *dev)
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{
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{
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struct i2c_adapter *adap = &dev->adapter;
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struct i2c_adapter *adap = &dev->adapter;
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int ret;
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int ret;
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@ -862,6 +930,17 @@ static int amd_i2c_adap_quirk(struct dw_i2c_dev *dev)
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return ret;
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return ret;
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}
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}
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static bool i2c_dw_is_model_poll(struct dw_i2c_dev *dev)
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{
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switch (dev->flags & MODEL_MASK) {
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case MODEL_AMD_NAVI_GPU:
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case MODEL_WANGXUN_SP:
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return true;
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default:
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return false;
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}
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}
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int i2c_dw_probe_master(struct dw_i2c_dev *dev)
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int i2c_dw_probe_master(struct dw_i2c_dev *dev)
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{
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{
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struct i2c_adapter *adap = &dev->adapter;
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struct i2c_adapter *adap = &dev->adapter;
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@ -917,8 +996,8 @@ int i2c_dw_probe_master(struct dw_i2c_dev *dev)
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adap->dev.parent = dev->dev;
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adap->dev.parent = dev->dev;
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i2c_set_adapdata(adap, dev);
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i2c_set_adapdata(adap, dev);
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if ((dev->flags & MODEL_MASK) == MODEL_AMD_NAVI_GPU)
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if (i2c_dw_is_model_poll(dev))
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return amd_i2c_adap_quirk(dev);
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return i2c_dw_poll_adap_quirk(dev);
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if (dev->flags & ACCESS_NO_IRQ_SUSPEND) {
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if (dev->flags & ACCESS_NO_IRQ_SUSPEND) {
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irq_flags = IRQF_NO_SUSPEND;
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irq_flags = IRQF_NO_SUSPEND;
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@ -168,6 +168,15 @@ static inline int dw_i2c_of_configure(struct platform_device *pdev)
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}
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}
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#endif
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#endif
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static int txgbe_i2c_request_regs(struct dw_i2c_dev *dev)
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{
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dev->map = dev_get_regmap(dev->dev->parent, NULL);
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if (!dev->map)
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return -ENODEV;
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return 0;
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}
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static void dw_i2c_plat_pm_cleanup(struct dw_i2c_dev *dev)
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static void dw_i2c_plat_pm_cleanup(struct dw_i2c_dev *dev)
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{
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{
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pm_runtime_disable(dev->dev);
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pm_runtime_disable(dev->dev);
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@ -185,6 +194,9 @@ static int dw_i2c_plat_request_regs(struct dw_i2c_dev *dev)
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case MODEL_BAIKAL_BT1:
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case MODEL_BAIKAL_BT1:
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ret = bt1_i2c_request_regs(dev);
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ret = bt1_i2c_request_regs(dev);
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break;
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break;
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case MODEL_WANGXUN_SP:
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ret = txgbe_i2c_request_regs(dev);
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break;
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default:
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default:
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dev->base = devm_platform_ioremap_resource(pdev, 0);
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dev->base = devm_platform_ioremap_resource(pdev, 0);
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ret = PTR_ERR_OR_ZERO(dev->base);
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ret = PTR_ERR_OR_ZERO(dev->base);
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@ -277,6 +289,9 @@ static int dw_i2c_plat_probe(struct platform_device *pdev)
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return -ENOMEM;
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return -ENOMEM;
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dev->flags = (uintptr_t)device_get_match_data(&pdev->dev);
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dev->flags = (uintptr_t)device_get_match_data(&pdev->dev);
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if (device_property_present(&pdev->dev, "wx,i2c-snps-model"))
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dev->flags = MODEL_WANGXUN_SP;
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dev->dev = &pdev->dev;
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dev->dev = &pdev->dev;
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dev->irq = irq;
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dev->irq = irq;
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platform_set_drvdata(pdev, dev);
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platform_set_drvdata(pdev, dev);
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