powerpc/perf: Add Power8 cache & TLB events
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This commit is contained in:
Michael Ellerman
Benjamin Herrenschmidt
parent
3b830c824a
commit
2fdd313f54
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@ -25,6 +25,37 @@
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#define PM_BRU_FIN 0x10068
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#define PM_BR_MPRED_CMPL 0x400f6
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/* All L1 D cache load references counted at finish, gated by reject */
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#define PM_LD_REF_L1 0x100ee
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/* Load Missed L1 */
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#define PM_LD_MISS_L1 0x3e054
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/* Store Missed L1 */
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#define PM_ST_MISS_L1 0x300f0
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/* L1 cache data prefetches */
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#define PM_L1_PREF 0x0d8b8
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/* Instruction fetches from L1 */
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#define PM_INST_FROM_L1 0x04080
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/* Demand iCache Miss */
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#define PM_L1_ICACHE_MISS 0x200fd
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/* Instruction Demand sectors wriittent into IL1 */
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#define PM_L1_DEMAND_WRITE 0x0408c
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/* Instruction prefetch written into IL1 */
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#define PM_IC_PREF_WRITE 0x0408e
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/* The data cache was reloaded from local core's L3 due to a demand load */
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#define PM_DATA_FROM_L3 0x4c042
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/* Demand LD - L3 Miss (not L2 hit and not L3 hit) */
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#define PM_DATA_FROM_L3MISS 0x300fe
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/* All successful D-side store dispatches for this thread */
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#define PM_L2_ST 0x17080
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/* All successful D-side store dispatches for this thread that were L2 Miss */
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#define PM_L2_ST_MISS 0x17082
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/* Total HW L3 prefetches(Load+store) */
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#define PM_L3_PREF_ALL 0x4e052
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/* Data PTEG reload */
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#define PM_DTLB_MISS 0x300fc
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/* ITLB Reloaded */
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#define PM_ITLB_MISS 0x400fc
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/*
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* Raw event encoding for POWER8:
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@ -557,6 +588,8 @@ static int power8_generic_events[] = {
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[PERF_COUNT_HW_INSTRUCTIONS] = PM_INST_CMPL,
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[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = PM_BRU_FIN,
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[PERF_COUNT_HW_BRANCH_MISSES] = PM_BR_MPRED_CMPL,
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[PERF_COUNT_HW_CACHE_REFERENCES] = PM_LD_REF_L1,
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[PERF_COUNT_HW_CACHE_MISSES] = PM_LD_MISS_L1,
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};
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static u64 power8_bhrb_filter_map(u64 branch_sample_type)
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@ -596,6 +629,116 @@ static void power8_config_bhrb(u64 pmu_bhrb_filter)
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mtspr(SPRN_MMCRA, (mfspr(SPRN_MMCRA) | pmu_bhrb_filter));
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}
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#define C(x) PERF_COUNT_HW_CACHE_##x
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/*
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* Table of generalized cache-related events.
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* 0 means not supported, -1 means nonsensical, other values
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* are event codes.
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*/
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static int power8_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
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[ C(L1D) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = PM_LD_REF_L1,
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[ C(RESULT_MISS) ] = PM_LD_MISS_L1,
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = 0,
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[ C(RESULT_MISS) ] = PM_ST_MISS_L1,
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = PM_L1_PREF,
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[ C(RESULT_MISS) ] = 0,
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},
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},
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[ C(L1I) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = PM_INST_FROM_L1,
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[ C(RESULT_MISS) ] = PM_L1_ICACHE_MISS,
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = PM_L1_DEMAND_WRITE,
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[ C(RESULT_MISS) ] = -1,
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = PM_IC_PREF_WRITE,
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[ C(RESULT_MISS) ] = 0,
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},
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},
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[ C(LL) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = PM_DATA_FROM_L3,
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[ C(RESULT_MISS) ] = PM_DATA_FROM_L3MISS,
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = PM_L2_ST,
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[ C(RESULT_MISS) ] = PM_L2_ST_MISS,
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = PM_L3_PREF_ALL,
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[ C(RESULT_MISS) ] = 0,
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},
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},
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[ C(DTLB) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = 0,
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[ C(RESULT_MISS) ] = PM_DTLB_MISS,
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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},
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[ C(ITLB) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = 0,
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[ C(RESULT_MISS) ] = PM_ITLB_MISS,
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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},
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[ C(BPU) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = PM_BRU_FIN,
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[ C(RESULT_MISS) ] = PM_BR_MPRED_CMPL,
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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},
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[ C(NODE) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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},
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};
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#undef C
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static struct power_pmu power8_pmu = {
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.name = "POWER8",
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.n_counter = 6,
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@ -611,6 +754,7 @@ static struct power_pmu power8_pmu = {
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.flags = PPMU_HAS_SSLOT | PPMU_HAS_SIER | PPMU_BHRB | PPMU_EBB,
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.n_generic = ARRAY_SIZE(power8_generic_events),
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.generic_events = power8_generic_events,
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.cache_events = &power8_cache_events,
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.attr_groups = power8_pmu_attr_groups,
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.bhrb_nr = 32,
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};
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