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[PATCH] x86: when L3 is present show its size in /proc/cpuinfo
The code that prints the cache size assumes that L3 always lives in chipset and is shared across CPUs. Which is not really true. I think all the cachesizes reported by cpuid are in the processor itself. The attached patch changes the code to reflect that. Signed-off-by: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
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1 changed files with 1 additions and 7 deletions
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@ -278,13 +278,7 @@ unsigned int __devinit init_intel_cacheinfo(struct cpuinfo_x86 *c)
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if ( l3 )
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printk(KERN_INFO "CPU: L3 cache: %dK\n", l3);
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/*
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* This assumes the L3 cache is shared; it typically lives in
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* the northbridge. The L1 caches are included by the L2
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* cache, and so should not be included for the purpose of
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* SMP switching weights.
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*/
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c->x86_cache_size = l2 ? l2 : (l1i+l1d);
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c->x86_cache_size = l3 ? l3 : (l2 ? l2 : (l1i+l1d));
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}
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return l2;
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