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arm64: dts: Add DDR memory controller for Layerscape SoCs

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Add DDR memory controller nodes to enable EDAC driver.

Signed-off-by: York Sun <york.sun@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
York Sun 2016-08-09 14:59:39 -07:00 committed by Shawn Guo
parent 29b4817d40
commit 30062fb0b3
2 changed files with 21 additions and 0 deletions
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7
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
View file

@ -247,6 +247,13 @@ esdhc: esdhc@1560000 {
bus-width = <4>;
};
ddr: memory-controller@1080000 {
compatible = "fsl,qoriq-memory-controller";
reg = <0x0 0x1080000 0x0 0x1000>;
interrupts = <0 144 0x4>;
big-endian;
};
dspi0: dspi@2100000 {
compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
#address-cells = <1>;

14
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
View file

@ -715,4 +715,18 @@ ccn@4000000 {
interrupts = <0 12 4>;
};
};
ddr1: memory-controller@1080000 {
compatible = "fsl,qoriq-memory-controller";
reg = <0x0 0x1080000 0x0 0x1000>;
interrupts = <0 17 0x4>;
little-endian;
};
ddr2: memory-controller@1090000 {
compatible = "fsl,qoriq-memory-controller";
reg = <0x0 0x1090000 0x0 0x1000>;
interrupts = <0 18 0x4>;
little-endian;
};
};