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ath5k: Extend get_default_sifs/slot_time
* Extend get_default_sifs/slot_time to include timings for turbo half and quarter rate modes. * AR5210 code for now uses timings already on core clock units instead of usecs so rename them (we 'll clean it up later). Signed-off-by: Nick Kossifidis <mickflemm@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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25ddfa1957
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3017fcab41
3 changed files with 68 additions and 24 deletions
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@ -226,16 +226,16 @@
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#define AR5K_INIT_USEC 39
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#define AR5K_INIT_USEC_TURBO 79
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#define AR5K_INIT_USEC_32 31
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#define AR5K_INIT_SLOT_TIME 396
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#define AR5K_INIT_SLOT_TIME_TURBO 480
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#define AR5K_INIT_SLOT_TIME_CLOCK 396
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#define AR5K_INIT_SLOT_TIME_TURBO_CLOCK 480
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#define AR5K_INIT_ACK_CTS_TIMEOUT 1024
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#define AR5K_INIT_ACK_CTS_TIMEOUT_TURBO 0x08000800
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#define AR5K_INIT_PROG_IFS 920
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#define AR5K_INIT_PROG_IFS_TURBO 960
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#define AR5K_INIT_EIFS 3440
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#define AR5K_INIT_EIFS_TURBO 6880
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#define AR5K_INIT_SIFS 560
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#define AR5K_INIT_SIFS_TURBO 480
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#define AR5K_INIT_SIFS_CLOCK 560
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#define AR5K_INIT_SIFS_TURBO_CLOCK 480
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#define AR5K_INIT_SH_RETRY 10
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#define AR5K_INIT_LG_RETRY AR5K_INIT_SH_RETRY
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#define AR5K_INIT_SSH_RETRY 32
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@ -251,6 +251,22 @@
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(AR5K_INIT_PROG_IFS_TURBO) \
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)
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/* Slot time */
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#define AR5K_INIT_SLOT_TIME_TURBO 6
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#define AR5K_INIT_SLOT_TIME_DEFAULT 9
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#define AR5K_INIT_SLOT_TIME_HALF_RATE 13
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#define AR5K_INIT_SLOT_TIME_QUARTER_RATE 21
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#define AR5K_INIT_SLOT_TIME_B 20
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#define AR5K_SLOT_TIME_MAX 0xffff
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/* SIFS */
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#define AR5K_INIT_SIFS_TURBO 6
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/* XXX: 8 from initvals 10 from standard */
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#define AR5K_INIT_SIFS_DEFAULT_BG 8
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#define AR5K_INIT_SIFS_DEFAULT_A 16
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#define AR5K_INIT_SIFS_HALF_RATE 32
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#define AR5K_INIT_SIFS_QUARTER_RATE 64
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/* Rx latency for 5 and 10MHz operation (max ?) */
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#define AR5K_INIT_RX_LAT_MAX 63
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/* Tx latencies from initvals (5212 only but no problem
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@ -43,14 +43,27 @@
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static unsigned int ath5k_hw_get_default_slottime(struct ath5k_hw *ah)
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{
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struct ieee80211_channel *channel = ah->ah_current_channel;
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unsigned int slot_time;
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if (channel->hw_value & CHANNEL_TURBO)
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return 6; /* both turbo modes */
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switch (ah->ah_bwmode) {
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case AR5K_BWMODE_40MHZ:
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slot_time = AR5K_INIT_SLOT_TIME_TURBO;
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break;
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case AR5K_BWMODE_10MHZ:
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slot_time = AR5K_INIT_SLOT_TIME_HALF_RATE;
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break;
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case AR5K_BWMODE_5MHZ:
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slot_time = AR5K_INIT_SLOT_TIME_QUARTER_RATE;
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break;
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case AR5K_BWMODE_DEFAULT:
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slot_time = AR5K_INIT_SLOT_TIME_DEFAULT;
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default:
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if (channel->hw_value & CHANNEL_CCK)
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slot_time = AR5K_INIT_SLOT_TIME_B;
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break;
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}
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if (channel->hw_value & CHANNEL_CCK)
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return 20; /* 802.11b */
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return 9; /* 802.11 a/g */
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return slot_time;
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}
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/**
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@ -58,17 +71,30 @@ static unsigned int ath5k_hw_get_default_slottime(struct ath5k_hw *ah)
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*
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* @ah: The &struct ath5k_hw
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*/
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static unsigned int ath5k_hw_get_default_sifs(struct ath5k_hw *ah)
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unsigned int ath5k_hw_get_default_sifs(struct ath5k_hw *ah)
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{
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struct ieee80211_channel *channel = ah->ah_current_channel;
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unsigned int sifs;
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if (channel->hw_value & CHANNEL_TURBO)
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return 8; /* both turbo modes */
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switch (ah->ah_bwmode) {
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case AR5K_BWMODE_40MHZ:
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sifs = AR5K_INIT_SIFS_TURBO;
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break;
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case AR5K_BWMODE_10MHZ:
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sifs = AR5K_INIT_SIFS_HALF_RATE;
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break;
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case AR5K_BWMODE_5MHZ:
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sifs = AR5K_INIT_SIFS_QUARTER_RATE;
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break;
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case AR5K_BWMODE_DEFAULT:
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sifs = AR5K_INIT_SIFS_DEFAULT_BG;
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default:
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if (channel->hw_value & CHANNEL_5GHZ)
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sifs = AR5K_INIT_SIFS_DEFAULT_A;
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break;
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}
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if (channel->hw_value & CHANNEL_5GHZ)
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return 16; /* 802.11a */
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return 10; /* 802.11 b/g */
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return sifs;
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}
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/**
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@ -297,7 +297,8 @@ int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue)
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/* Set Slot time */
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ath5k_hw_reg_write(ah, (ah->ah_bwmode == AR5K_BWMODE_40MHZ) ?
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AR5K_INIT_SLOT_TIME_TURBO : AR5K_INIT_SLOT_TIME,
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AR5K_INIT_SLOT_TIME_TURBO_CLOCK :
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AR5K_INIT_SLOT_TIME_CLOCK,
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AR5K_SLOT_TIME);
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/* Set ACK_CTS timeout */
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ath5k_hw_reg_write(ah, (ah->ah_bwmode == AR5K_BWMODE_40MHZ) ?
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@ -306,15 +307,16 @@ int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue)
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/* Set IFS0 */
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if (ah->ah_bwmode == AR5K_BWMODE_40MHZ) {
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ath5k_hw_reg_write(ah, ((AR5K_INIT_SIFS_TURBO +
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tq->tqi_aifs * AR5K_INIT_SLOT_TIME_TURBO) <<
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AR5K_IFS0_DIFS_S) | AR5K_INIT_SIFS_TURBO,
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ath5k_hw_reg_write(ah, ((AR5K_INIT_SIFS_TURBO_CLOCK +
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tq->tqi_aifs * AR5K_INIT_SLOT_TIME_TURBO_CLOCK)
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<< AR5K_IFS0_DIFS_S) |
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AR5K_INIT_SIFS_TURBO_CLOCK,
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AR5K_IFS0);
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} else {
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ath5k_hw_reg_write(ah, ((AR5K_INIT_SIFS +
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tq->tqi_aifs * AR5K_INIT_SLOT_TIME) <<
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ath5k_hw_reg_write(ah, ((AR5K_INIT_SIFS_CLOCK +
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tq->tqi_aifs * AR5K_INIT_SLOT_TIME_CLOCK) <<
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AR5K_IFS0_DIFS_S) |
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AR5K_INIT_SIFS, AR5K_IFS0);
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AR5K_INIT_SIFS_CLOCK, AR5K_IFS0);
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}
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/* Set IFS1 */
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