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arm64: dts: qcom: sm8250: camss: Add CAMSS block definition

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Adds a CAMSS definition block.

Co-developed-by: Julian Grahsl <jgrahsl@snap.com>
Signed-off-by: Julian Grahsl <jgrahsl@snap.com>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220415164655.1679628-3-bryan.odonoghue@linaro.org
This commit is contained in:
Bryan O'Donoghue 2022-04-15 17:46:54 +01:00 committed by Bjorn Andersson
parent ca79a997f2
commit 30325603b9
1 changed files with 153 additions and 0 deletions
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153
arch/arm64/boot/dts/qcom/sm8250.dtsi
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@ -3150,6 +3150,159 @@ videocc: clock-controller@abf0000 {
#power-domain-cells = <1>;
};
camss: camss@ac6a000 {
compatible = "qcom,sm8250-camss";
status = "disabled";
reg = <0 0xac6a000 0 0x2000>,
<0 0xac6c000 0 0x2000>,
<0 0xac6e000 0 0x1000>,
<0 0xac70000 0 0x1000>,
<0 0xac72000 0 0x1000>,
<0 0xac74000 0 0x1000>,
<0 0xacb4000 0 0xd000>,
<0 0xacc3000 0 0xd000>,
<0 0xacd9000 0 0x2200>,
<0 0xacdb200 0 0x2200>;
reg-names = "csiphy0",
"csiphy1",
"csiphy2",
"csiphy3",
"csiphy4",
"csiphy5",
"vfe0",
"vfe1",
"vfe_lite0",
"vfe_lite1";
interrupts = <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "csiphy0",
"csiphy1",
"csiphy2",
"csiphy3",
"csiphy4",
"csiphy5",
"csid0",
"csid1",
"csid2",
"csid3",
"vfe0",
"vfe1",
"vfe_lite0",
"vfe_lite1";
power-domains = <&camcc IFE_0_GDSC>,
<&camcc IFE_1_GDSC>,
<&camcc TITAN_TOP_GDSC>;
clocks = <&gcc GCC_CAMERA_AHB_CLK>,
<&gcc GCC_CAMERA_HF_AXI_CLK>,
<&gcc GCC_CAMERA_SF_AXI_CLK>,
<&camcc CAM_CC_CAMNOC_AXI_CLK>,
<&camcc CAM_CC_CAMNOC_AXI_CLK_SRC>,
<&camcc CAM_CC_CORE_AHB_CLK>,
<&camcc CAM_CC_CPAS_AHB_CLK>,
<&camcc CAM_CC_CSIPHY0_CLK>,
<&camcc CAM_CC_CSI0PHYTIMER_CLK>,
<&camcc CAM_CC_CSIPHY1_CLK>,
<&camcc CAM_CC_CSI1PHYTIMER_CLK>,
<&camcc CAM_CC_CSIPHY2_CLK>,
<&camcc CAM_CC_CSI2PHYTIMER_CLK>,
<&camcc CAM_CC_CSIPHY3_CLK>,
<&camcc CAM_CC_CSI3PHYTIMER_CLK>,
<&camcc CAM_CC_CSIPHY4_CLK>,
<&camcc CAM_CC_CSI4PHYTIMER_CLK>,
<&camcc CAM_CC_CSIPHY5_CLK>,
<&camcc CAM_CC_CSI5PHYTIMER_CLK>,
<&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
<&camcc CAM_CC_IFE_0_AHB_CLK>,
<&camcc CAM_CC_IFE_0_AXI_CLK>,
<&camcc CAM_CC_IFE_0_CLK>,
<&camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
<&camcc CAM_CC_IFE_0_CSID_CLK>,
<&camcc CAM_CC_IFE_0_AREG_CLK>,
<&camcc CAM_CC_IFE_1_AHB_CLK>,
<&camcc CAM_CC_IFE_1_AXI_CLK>,
<&camcc CAM_CC_IFE_1_CLK>,
<&camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
<&camcc CAM_CC_IFE_1_CSID_CLK>,
<&camcc CAM_CC_IFE_1_AREG_CLK>,
<&camcc CAM_CC_IFE_LITE_AHB_CLK>,
<&camcc CAM_CC_IFE_LITE_AXI_CLK>,
<&camcc CAM_CC_IFE_LITE_CLK>,
<&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
<&camcc CAM_CC_IFE_LITE_CSID_CLK>;
clock-names = "cam_ahb_clk",
"cam_hf_axi",
"cam_sf_axi",
"camnoc_axi",
"camnoc_axi_src",
"core_ahb",
"cpas_ahb",
"csiphy0",
"csiphy0_timer",
"csiphy1",
"csiphy1_timer",
"csiphy2",
"csiphy2_timer",
"csiphy3",
"csiphy3_timer",
"csiphy4",
"csiphy4_timer",
"csiphy5",
"csiphy5_timer",
"slow_ahb_src",
"vfe0_ahb",
"vfe0_axi",
"vfe0",
"vfe0_cphy_rx",
"vfe0_csid",
"vfe0_areg",
"vfe1_ahb",
"vfe1_axi",
"vfe1",
"vfe1_cphy_rx",
"vfe1_csid",
"vfe1_areg",
"vfe_lite_ahb",
"vfe_lite_axi",
"vfe_lite",
"vfe_lite_cphy_rx",
"vfe_lite_csid";
iommus = <&apps_smmu 0x800 0x400>,
<&apps_smmu 0x801 0x400>,
<&apps_smmu 0x840 0x400>,
<&apps_smmu 0x841 0x400>,
<&apps_smmu 0xc00 0x400>,
<&apps_smmu 0xc01 0x400>,
<&apps_smmu 0xc40 0x400>,
<&apps_smmu 0xc41 0x400>;
interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_CAMERA_CFG>,
<&mmss_noc MASTER_CAMNOC_HF &mc_virt SLAVE_EBI_CH0>,
<&mmss_noc MASTER_CAMNOC_SF &mc_virt SLAVE_EBI_CH0>,
<&mmss_noc MASTER_CAMNOC_ICP &mc_virt SLAVE_EBI_CH0>;
interconnect-names = "cam_ahb",
"cam_hf_0_mnoc",
"cam_sf_0_mnoc",
"cam_sf_icp_mnoc";
};
camcc: clock-controller@ad00000 {
compatible = "qcom,sm8250-camcc";
reg = <0 0x0ad00000 0 0x10000>;