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arm64: kexec: Use dcache ops macros instead of open-coding
kexec does dcache maintenance when it re-writes all memory. Our dcache_by_line_op macro depends on reading the sanitized DminLine from memory. Kexec may have overwritten this, so open-codes the sequence. dcache_by_line_op is a whole set of macros, it uses dcache_line_size which uses read_ctr for the sanitsed DminLine. Reading the DminLine is the first thing the dcache_by_line_op does. Rename dcache_by_line_op dcache_by_myline_op and take DminLine as an argument. Kexec can now use the slightly smaller macro. This makes up-coming changes to the dcache maintenance easier on the eye. Code generated by the existing callers is unchanged. Suggested-by: James Morse <james.morse@arm.com> Signed-off-by: Pasha Tatashin <pasha.tatashin@soleen.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Link: https://lore.kernel.org/r/20210930143113.1502553-7-pasha.tatashin@soleen.com Signed-off-by: Will Deacon <will@kernel.org>
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2 changed files with 26 additions and 17 deletions
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@ -405,19 +405,19 @@ alternative_endif
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/*
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* Macro to perform a data cache maintenance for the interval
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* [start, end)
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* [start, end) with dcache line size explicitly provided.
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*
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* op: operation passed to dc instruction
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* domain: domain used in dsb instruciton
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* start: starting virtual address of the region
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* end: end virtual address of the region
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* linesz: dcache line size
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* fixup: optional label to branch to on user fault
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* Corrupts: start, end, tmp1, tmp2
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* Corrupts: start, end, tmp
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*/
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.macro dcache_by_line_op op, domain, start, end, tmp1, tmp2, fixup
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dcache_line_size \tmp1, \tmp2
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sub \tmp2, \tmp1, #1
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bic \start, \start, \tmp2
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.macro dcache_by_myline_op op, domain, start, end, linesz, tmp, fixup
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sub \tmp, \linesz, #1
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bic \start, \start, \tmp
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.Ldcache_op\@:
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.ifc \op, cvau
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__dcache_op_workaround_clean_cache \op, \start
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@ -436,7 +436,7 @@ alternative_endif
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.endif
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.endif
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.endif
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add \start, \start, \tmp1
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add \start, \start, \linesz
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cmp \start, \end
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b.lo .Ldcache_op\@
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dsb \domain
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@ -444,6 +444,22 @@ alternative_endif
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_cond_extable .Ldcache_op\@, \fixup
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.endm
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/*
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* Macro to perform a data cache maintenance for the interval
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* [start, end)
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*
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* op: operation passed to dc instruction
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* domain: domain used in dsb instruciton
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* start: starting virtual address of the region
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* end: end virtual address of the region
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* fixup: optional label to branch to on user fault
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* Corrupts: start, end, tmp1, tmp2
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*/
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.macro dcache_by_line_op op, domain, start, end, tmp1, tmp2, fixup
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dcache_line_size \tmp1, \tmp2
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dcache_by_myline_op \op, \domain, \start, \end, \tmp1, \tmp2, \fixup
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.endm
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/*
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* Macro to perform an instruction cache maintenance for the interval
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* [start, end)
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@ -41,16 +41,9 @@ SYM_CODE_START(arm64_relocate_new_kernel)
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tbz x16, IND_SOURCE_BIT, .Ltest_indirection
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/* Invalidate dest page to PoC. */
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mov x2, x13
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add x20, x2, #PAGE_SIZE
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sub x1, x15, #1
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bic x2, x2, x1
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2: dc ivac, x2
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add x2, x2, x15
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cmp x2, x20
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b.lo 2b
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dsb sy
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mov x2, x13
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add x1, x2, #PAGE_SIZE
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dcache_by_myline_op ivac, sy, x2, x1, x15, x20
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copy_page x13, x12, x1, x2, x3, x4, x5, x6, x7, x8
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b .Lnext
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.Ltest_indirection:
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