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net: hns3: fix sending pfc frames after reset issue

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[ Upstream commit f14db07064 ]

To prevent the system from abnormally sending PFC frames after an
abnormal reset. The hns3 driver notifies the firmware to disable pfc
before reset.

Fixes: 35d93a3004 ("net: hns3: adjust the process of PF reset")
Signed-off-by: Jijie Shao <shaojijie@huawei.com>
Signed-off-by: Hao Lan <lanhao@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Jijie Shao 2023-05-12 18:00:12 +08:00 committed by Greg Kroah-Hartman
parent d1bcc60687
commit 304e5cb77e
3 changed files with 16 additions and 8 deletions
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15
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
View file

@ -6688,12 +6688,15 @@ static void hclge_ae_stop(struct hnae3_handle *handle)
/* If it is not PF reset or FLR, the firmware will disable the MAC,
* so it only need to stop phy here.
*/
if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) &&
hdev->reset_type != HNAE3_FUNC_RESET &&
hdev->reset_type != HNAE3_FLR_RESET) {
hclge_mac_stop_phy(hdev);
hclge_update_link_status(hdev);
return;
if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) {
hclge_pfc_pause_en_cfg(hdev, HCLGE_PFC_TX_RX_DISABLE,
HCLGE_PFC_DISABLE);
if (hdev->reset_type != HNAE3_FUNC_RESET &&
hdev->reset_type != HNAE3_FLR_RESET) {
hclge_mac_stop_phy(hdev);
hclge_update_link_status(hdev);
return;
}
}
for (i = 0; i < handle->kinfo.num_tqps; i++)

4
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c
View file

@ -170,8 +170,8 @@ int hclge_mac_pause_en_cfg(struct hclge_dev *hdev, bool tx, bool rx)
return hclge_cmd_send(&hdev->hw, &desc, 1);
}
static int hclge_pfc_pause_en_cfg(struct hclge_dev *hdev, u8 tx_rx_bitmap,
u8 pfc_bitmap)
int hclge_pfc_pause_en_cfg(struct hclge_dev *hdev, u8 tx_rx_bitmap,
u8 pfc_bitmap)
{
struct hclge_desc desc;
struct hclge_pfc_en_cmd *pfc = (struct hclge_pfc_en_cmd *)desc.data;

5
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h
View file

@ -109,6 +109,9 @@ struct hclge_bp_to_qs_map_cmd {
u32 rsvd1;
};
#define HCLGE_PFC_DISABLE 0
#define HCLGE_PFC_TX_RX_DISABLE 0
struct hclge_pfc_en_cmd {
u8 tx_rx_en_bitmap;
u8 pri_en_bitmap;
@ -150,6 +153,8 @@ void hclge_tm_schd_info_update(struct hclge_dev *hdev, u8 num_tc);
void hclge_tm_pfc_info_update(struct hclge_dev *hdev);
int hclge_tm_dwrr_cfg(struct hclge_dev *hdev);
int hclge_tm_init_hw(struct hclge_dev *hdev, bool init);
int hclge_pfc_pause_en_cfg(struct hclge_dev *hdev, u8 tx_rx_bitmap,
u8 pfc_bitmap);
int hclge_mac_pause_en_cfg(struct hclge_dev *hdev, bool tx, bool rx);
int hclge_pause_addr_cfg(struct hclge_dev *hdev, const u8 *mac_addr);
int hclge_pfc_rx_stats_get(struct hclge_dev *hdev, u64 *stats);