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dma: tegra: implement suspend/resume callbacks
Implement suspend/resume callbacks to store APB DMA channel's register on suspend and restore APB DMA channel's register on resume. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
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1 changed files with 65 additions and 0 deletions
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@ -30,6 +30,7 @@
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/pm.h>
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#include <linux/pm_runtime.h>
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#include <linux/slab.h>
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#include <linux/clk/tegra.h>
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@ -199,6 +200,7 @@ struct tegra_dma_channel {
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/* Channel-slave specific configuration */
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struct dma_slave_config dma_sconfig;
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struct tegra_dma_channel_regs channel_reg;
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};
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/* tegra_dma: Tegra DMA specific information */
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@ -1440,11 +1442,74 @@ static int tegra_dma_runtime_resume(struct device *dev)
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return 0;
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}
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#ifdef CONFIG_PM_SLEEP
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static int tegra_dma_pm_suspend(struct device *dev)
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{
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struct tegra_dma *tdma = dev_get_drvdata(dev);
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int i;
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int ret;
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/* Enable clock before accessing register */
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ret = tegra_dma_runtime_resume(dev);
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if (ret < 0)
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return ret;
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tdma->reg_gen = tdma_read(tdma, TEGRA_APBDMA_GENERAL);
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for (i = 0; i < tdma->chip_data->nr_channels; i++) {
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struct tegra_dma_channel *tdc = &tdma->channels[i];
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struct tegra_dma_channel_regs *ch_reg = &tdc->channel_reg;
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ch_reg->csr = tdc_read(tdc, TEGRA_APBDMA_CHAN_CSR);
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ch_reg->ahb_ptr = tdc_read(tdc, TEGRA_APBDMA_CHAN_AHBPTR);
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ch_reg->apb_ptr = tdc_read(tdc, TEGRA_APBDMA_CHAN_APBPTR);
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ch_reg->ahb_seq = tdc_read(tdc, TEGRA_APBDMA_CHAN_AHBSEQ);
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ch_reg->apb_seq = tdc_read(tdc, TEGRA_APBDMA_CHAN_APBSEQ);
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}
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/* Disable clock */
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tegra_dma_runtime_suspend(dev);
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return 0;
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}
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static int tegra_dma_pm_resume(struct device *dev)
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{
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struct tegra_dma *tdma = dev_get_drvdata(dev);
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int i;
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int ret;
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/* Enable clock before accessing register */
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ret = tegra_dma_runtime_resume(dev);
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if (ret < 0)
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return ret;
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tdma_write(tdma, TEGRA_APBDMA_GENERAL, tdma->reg_gen);
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tdma_write(tdma, TEGRA_APBDMA_CONTROL, 0);
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tdma_write(tdma, TEGRA_APBDMA_IRQ_MASK_SET, 0xFFFFFFFFul);
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for (i = 0; i < tdma->chip_data->nr_channels; i++) {
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struct tegra_dma_channel *tdc = &tdma->channels[i];
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struct tegra_dma_channel_regs *ch_reg = &tdc->channel_reg;
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tdc_write(tdc, TEGRA_APBDMA_CHAN_APBSEQ, ch_reg->apb_seq);
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tdc_write(tdc, TEGRA_APBDMA_CHAN_APBPTR, ch_reg->apb_ptr);
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tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBSEQ, ch_reg->ahb_seq);
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tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBPTR, ch_reg->ahb_ptr);
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tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR,
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(ch_reg->csr & ~TEGRA_APBDMA_CSR_ENB));
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}
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/* Disable clock */
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tegra_dma_runtime_suspend(dev);
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return 0;
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}
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#endif
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static const struct dev_pm_ops tegra_dma_dev_pm_ops = {
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#ifdef CONFIG_PM_RUNTIME
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.runtime_suspend = tegra_dma_runtime_suspend,
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.runtime_resume = tegra_dma_runtime_resume,
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#endif
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SET_SYSTEM_SLEEP_PM_OPS(tegra_dma_pm_suspend, tegra_dma_pm_resume)
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};
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static struct platform_driver tegra_dmac_driver = {
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