arm64: dts: imx: add imx8qm mek support
The i.MX8QuadMax is a Dual (2x) Cortex-A72 and Quad (4x) Cortex-A53 proccessor with powerful graphic and multimedia features. This patch adds i.MX8QuadMax MEK board support. Note that MX8QM needs a special workaround for TLB flush due to a SoC errata, otherwise there may be random crash if enable both clusters of A72 and A53. As the errata workaround is still not in mainline, so we disable A72 cluster first for MX8QM MEK. Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: devicetree@vger.kernel.org Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Dong Aisheng
Shawn Guo
parent
f2180be18a
commit
307fd14d4b
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@ -60,6 +60,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mq-pico-pi.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mq-thor96.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-rmb3.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-zest.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8qxp-ai_ml.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-eval-v3.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb
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@ -0,0 +1,144 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2018-2019 NXP
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* Dong Aisheng <aisheng.dong@nxp.com>
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*/
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/dts-v1/;
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#include "imx8qm.dtsi"
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/ {
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model = "Freescale i.MX8QM MEK";
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compatible = "fsl,imx8qm-mek", "fsl,imx8qm";
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chosen {
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stdout-path = &lpuart0;
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};
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cpus {
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/delete-node/ cpu-map;
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/delete-node/ cpu@100;
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/delete-node/ cpu@101;
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};
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memory@80000000 {
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device_type = "memory";
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reg = <0x00000000 0x80000000 0 0x40000000>;
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};
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reg_usdhc2_vmmc: usdhc2-vmmc {
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compatible = "regulator-fixed";
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regulator-name = "SD1_SPWR";
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regulator-min-microvolt = <3000000>;
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regulator-max-microvolt = <3000000>;
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gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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};
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&lpuart0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lpuart0>;
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status = "okay";
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};
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&fec1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec1>;
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phy-mode = "rgmii-id";
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phy-handle = <ðphy0>;
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fsl,magic-packet;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <0>;
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};
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ethphy1: ethernet-phy@1 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <1>;
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};
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};
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};
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&usdhc1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc1>;
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bus-width = <8>;
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no-sd;
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no-sdio;
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non-removable;
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status = "okay";
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};
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&usdhc2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc2>;
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bus-width = <4>;
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vmmc-supply = <®_usdhc2_vmmc>;
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cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>;
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wp-gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>;
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status = "okay";
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};
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&iomuxc {
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pinctrl_fec1: fec1grp {
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fsl,pins = <
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IMX8QM_ENET0_MDC_CONN_ENET0_MDC 0x06000020
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IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020
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IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020
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IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020
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IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020
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IMX8QM_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020
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IMX8QM_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020
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IMX8QM_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020
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IMX8QM_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020
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IMX8QM_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020
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IMX8QM_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020
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IMX8QM_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020
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IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020
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IMX8QM_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020
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>;
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};
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pinctrl_lpuart0: lpuart0grp {
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fsl,pins = <
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IMX8QM_UART0_RX_DMA_UART0_RX 0x06000020
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IMX8QM_UART0_TX_DMA_UART0_TX 0x06000020
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>;
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};
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pinctrl_usdhc1: usdhc1grp {
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fsl,pins = <
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IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
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IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
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IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
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IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
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IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
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IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
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IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
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IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
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IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
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IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
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IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041
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>;
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};
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pinctrl_usdhc2: usdhc2grp {
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fsl,pins = <
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IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041
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IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021
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IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021
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IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021
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IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021
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IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021
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IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
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>;
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};
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};
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