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mtd: nand: davinci: simplify error handling
There is not needed to use a lot of names for err handling. It complicates code support and reading. Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com> Reviewed-by: Taras Kondratiuk <taras@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
This commit is contained in:
parent
05103825fc
commit
30a3970cde
1 changed files with 17 additions and 29 deletions
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@ -615,8 +615,7 @@ static int nand_davinci_probe(struct platform_device *pdev)
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info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
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if (!info) {
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dev_err(&pdev->dev, "unable to allocate memory\n");
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ret = -ENOMEM;
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goto err_nomem;
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return -ENOMEM;
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}
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platform_set_drvdata(pdev, info);
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@ -625,20 +624,16 @@ static int nand_davinci_probe(struct platform_device *pdev)
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res2 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
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if (!res1 || !res2) {
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dev_err(&pdev->dev, "resource missing\n");
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ret = -EINVAL;
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goto err_nomem;
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return -EINVAL;
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}
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vaddr = devm_ioremap_resource(&pdev->dev, res1);
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if (IS_ERR(vaddr)) {
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ret = PTR_ERR(vaddr);
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goto err_ioremap;
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}
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if (IS_ERR(vaddr))
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return PTR_ERR(vaddr);
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base = devm_ioremap_resource(&pdev->dev, res2);
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if (IS_ERR(base)) {
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ret = PTR_ERR(base);
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goto err_ioremap;
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}
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if (IS_ERR(base))
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return PTR_ERR(base);
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info->dev = &pdev->dev;
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info->base = base;
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@ -705,7 +700,7 @@ static int nand_davinci_probe(struct platform_device *pdev)
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spin_unlock_irq(&davinci_nand_lock);
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if (ret == -EBUSY)
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goto err_ecc;
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return ret;
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info->chip.ecc.calculate = nand_davinci_calculate_4bit;
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info->chip.ecc.correct = nand_davinci_correct_4bit;
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@ -721,8 +716,7 @@ static int nand_davinci_probe(struct platform_device *pdev)
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info->chip.ecc.strength = pdata->ecc_bits;
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break;
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default:
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ret = -EINVAL;
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goto err_ecc;
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return -EINVAL;
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}
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info->chip.ecc.mode = ecc_mode;
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@ -730,7 +724,7 @@ static int nand_davinci_probe(struct platform_device *pdev)
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if (IS_ERR(info->clk)) {
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ret = PTR_ERR(info->clk);
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dev_dbg(&pdev->dev, "unable to get AEMIF clock, err %d\n", ret);
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goto err_clk;
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return ret;
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}
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ret = clk_prepare_enable(info->clk);
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@ -759,7 +753,7 @@ static int nand_davinci_probe(struct platform_device *pdev)
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info->core_chipsel);
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if (ret < 0) {
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dev_dbg(&pdev->dev, "NAND timing values setup fail\n");
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goto err_timing;
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goto err;
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}
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spin_lock_irq(&davinci_nand_lock);
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@ -775,7 +769,7 @@ static int nand_davinci_probe(struct platform_device *pdev)
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ret = nand_scan_ident(&info->mtd, pdata->mask_chipsel ? 2 : 1, NULL);
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if (ret < 0) {
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dev_dbg(&pdev->dev, "no NAND chip(s) found\n");
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goto err_scan;
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goto err;
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}
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/* Update ECC layout if needed ... for 1-bit HW ECC, the default
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@ -789,7 +783,7 @@ static int nand_davinci_probe(struct platform_device *pdev)
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if (!chunks || info->mtd.oobsize < 16) {
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dev_dbg(&pdev->dev, "too small\n");
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ret = -EINVAL;
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goto err_scan;
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goto err;
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}
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/* For small page chips, preserve the manufacturer's
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@ -820,7 +814,7 @@ static int nand_davinci_probe(struct platform_device *pdev)
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dev_warn(&pdev->dev, "no 4-bit ECC support yet "
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"for 4KiB-page NAND\n");
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ret = -EIO;
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goto err_scan;
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goto err;
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syndrome_done:
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info->chip.ecc.layout = &info->ecclayout;
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@ -828,7 +822,7 @@ static int nand_davinci_probe(struct platform_device *pdev)
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ret = nand_scan_tail(&info->mtd);
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if (ret < 0)
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goto err_scan;
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goto err;
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if (pdata->parts)
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ret = mtd_device_parse_register(&info->mtd, NULL, NULL,
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@ -841,7 +835,7 @@ static int nand_davinci_probe(struct platform_device *pdev)
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NULL, 0);
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}
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if (ret < 0)
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goto err_scan;
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goto err;
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val = davinci_nand_readl(info, NRCSR_OFFSET);
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dev_info(&pdev->dev, "controller rev. %d.%d\n",
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@ -849,8 +843,7 @@ static int nand_davinci_probe(struct platform_device *pdev)
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return 0;
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err_scan:
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err_timing:
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err:
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clk_disable_unprepare(info->clk);
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err_clk_enable:
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@ -858,11 +851,6 @@ static int nand_davinci_probe(struct platform_device *pdev)
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if (ecc_mode == NAND_ECC_HW_SYNDROME)
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ecc4_busy = false;
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spin_unlock_irq(&davinci_nand_lock);
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err_ecc:
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err_clk:
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err_ioremap:
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err_nomem:
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return ret;
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}
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