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drm/i915/dsc: use REG_BIT, REG_GENMASK, and friends for PPS0 and PPS1
Use the register helper macros for PPS0 and PPS1 register contents. Cc: Suraj Kandpal <suraj.kandpal@intel.com> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/0dfebe37a391a5ceb8bfae8e16383f1e5aef815d.1693933849.git.jani.nikula@intel.com
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051da77ed5
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2 changed files with 22 additions and 20 deletions
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@ -423,10 +423,10 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
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int vdsc_instances_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);
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/* PPS 0 */
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pps_val = DSC_PPS0_VER_MAJ | vdsc_cfg->dsc_version_minor <<
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DSC_PPS0_VER_MIN_SHIFT |
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vdsc_cfg->bits_per_component << DSC_PPS0_BPC_SHIFT |
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vdsc_cfg->line_buf_depth << DSC_PPS0_LINE_BUF_DEPTH_SHIFT;
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pps_val = DSC_PPS0_VER_MAJOR(1) |
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DSC_PPS0_VER_MINOR(vdsc_cfg->dsc_version_minor) |
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DSC_PPS0_BPC(vdsc_cfg->bits_per_component) |
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DSC_PPS0_LINE_BUF_DEPTH(vdsc_cfg->line_buf_depth);
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if (vdsc_cfg->dsc_version_minor == 2) {
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pps_val |= DSC_PPS0_ALT_ICH_SEL;
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if (vdsc_cfg->native_420)
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@ -857,9 +857,8 @@ static void intel_dsc_get_pps_config(struct intel_crtc_state *crtc_state)
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/* PPS 0 */
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pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 0);
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vdsc_cfg->bits_per_component = (pps_temp & DSC_PPS0_BPC_MASK) >> DSC_PPS0_BPC_SHIFT;
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vdsc_cfg->line_buf_depth =
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(pps_temp & DSC_PPS0_LINE_BUF_DEPTH_MASK) >> DSC_PPS0_LINE_BUF_DEPTH_SHIFT;
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vdsc_cfg->bits_per_component = REG_FIELD_GET(DSC_PPS0_BPC_MASK, pps_temp);
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vdsc_cfg->line_buf_depth = REG_FIELD_GET(DSC_PPS0_LINE_BUF_DEPTH_MASK, pps_temp);
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vdsc_cfg->block_pred_enable = pps_temp & DSC_PPS0_BLOCK_PREDICTION;
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vdsc_cfg->convert_rgb = pps_temp & DSC_PPS0_COLOR_SPACE_CONVERSION;
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vdsc_cfg->simple_422 = pps_temp & DSC_PPS0_422_ENABLE;
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@ -870,7 +869,7 @@ static void intel_dsc_get_pps_config(struct intel_crtc_state *crtc_state)
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/* PPS 1 */
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pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 1);
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vdsc_cfg->bits_per_pixel = pps_temp;
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vdsc_cfg->bits_per_pixel = REG_FIELD_GET(DSC_PPS1_BPP_MASK, pps_temp);
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if (vdsc_cfg->native_420)
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vdsc_cfg->bits_per_pixel >>= 1;
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@ -73,22 +73,25 @@
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#define ICL_DSC1_PPS(pipe, pps) _MMIO(_ICL_DSC1_PPS_0(pipe) + ((pps) * 4))
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/* PPS 0 */
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#define DSC_PPS0_NATIVE_422_ENABLE BIT(23)
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#define DSC_PPS0_NATIVE_420_ENABLE BIT(22)
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#define DSC_PPS0_ALT_ICH_SEL (1 << 20)
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#define DSC_PPS0_VBR_ENABLE (1 << 19)
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#define DSC_PPS0_422_ENABLE (1 << 18)
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#define DSC_PPS0_COLOR_SPACE_CONVERSION (1 << 17)
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#define DSC_PPS0_BLOCK_PREDICTION (1 << 16)
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#define DSC_PPS0_LINE_BUF_DEPTH_SHIFT 12
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#define DSC_PPS0_NATIVE_422_ENABLE REG_BIT(23)
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#define DSC_PPS0_NATIVE_420_ENABLE REG_BIT(22)
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#define DSC_PPS0_ALT_ICH_SEL REG_BIT(20)
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#define DSC_PPS0_VBR_ENABLE REG_BIT(19)
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#define DSC_PPS0_422_ENABLE REG_BIT(18)
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#define DSC_PPS0_COLOR_SPACE_CONVERSION REG_BIT(17)
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#define DSC_PPS0_BLOCK_PREDICTION REG_BIT(16)
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#define DSC_PPS0_LINE_BUF_DEPTH_MASK REG_GENMASK(15, 12)
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#define DSC_PPS0_BPC_SHIFT 8
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#define DSC_PPS0_LINE_BUF_DEPTH(depth) REG_FIELD_PREP(DSC_PPS0_LINE_BUF_DEPTH_MASK, depth)
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#define DSC_PPS0_BPC_MASK REG_GENMASK(11, 8)
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#define DSC_PPS0_VER_MIN_SHIFT 4
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#define DSC_PPS0_VER_MAJ (0x1 << 0)
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#define DSC_PPS0_BPC(bpc) REG_FIELD_PREP(DSC_PPS0_BPC_MASK, bpc)
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#define DSC_PPS0_VER_MINOR_MASK REG_GENMASK(7, 4)
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#define DSC_PPS0_VER_MINOR(minor) REG_FIELD_PREP(DSC_PPS0_VER_MINOR_MASK, minor)
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#define DSC_PPS0_VER_MAJOR_MASK REG_GENMASK(3, 0)
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#define DSC_PPS0_VER_MAJOR(major) REG_FIELD_PREP(DSC_PPS0_VER_MAJOR_MASK, major)
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/* PPS 1 */
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#define DSC_PPS1_BPP(bpp) ((bpp) << 0)
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#define DSC_PPS1_BPP_MASK REG_GENMASK(9, 0)
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#define DSC_PPS1_BPP(bpp) REG_FIELD_PREP(DSC_PPS1_BPP_MASK, bpp)
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/* PPS 2 */
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#define DSC_PPS2_PIC_WIDTH_MASK REG_GENMASK(31, 16)
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