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clk: qcom: clk-alpha-pll: Add support for lucid ole pll configure
Lucid ole pll has as extra RINGOSC_CAL_L field in L register in addition to the fields that are part of lucid evo pll, hence add support for lucid ole pll configure function to configure the ole plls. Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230707035744.22245-3-quic_jkona@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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2 changed files with 31 additions and 0 deletions
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@ -271,6 +271,7 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
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#define LUCID_EVO_ENABLE_VOTE_RUN BIT(25)
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#define LUCID_EVO_PLL_L_VAL_MASK GENMASK(15, 0)
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#define LUCID_EVO_PLL_CAL_L_VAL_SHIFT 16
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#define LUCID_OLE_PLL_RINGOSC_CAL_L_VAL_SHIFT 24
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/* ZONDA PLL specific */
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#define ZONDA_PLL_OUT_MASK 0xf
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@ -2119,6 +2120,34 @@ void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regma
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}
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EXPORT_SYMBOL_GPL(clk_lucid_evo_pll_configure);
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void clk_lucid_ole_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
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const struct alpha_pll_config *config)
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{
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u32 lval = config->l;
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lval |= TRION_PLL_CAL_VAL << LUCID_EVO_PLL_CAL_L_VAL_SHIFT;
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lval |= TRION_PLL_CAL_VAL << LUCID_OLE_PLL_RINGOSC_CAL_L_VAL_SHIFT;
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clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), lval);
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clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
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clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
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clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val);
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clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val);
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clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val);
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clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val);
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clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
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clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
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clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val);
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clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U2(pll), config->test_ctl_hi2_val);
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/* Disable PLL output */
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regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
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/* Set operation mode to STANDBY and de-assert the reset */
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regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
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regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
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}
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EXPORT_SYMBOL_GPL(clk_lucid_ole_pll_configure);
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static int alpha_pll_lucid_evo_enable(struct clk_hw *hw)
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{
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struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
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@ -199,6 +199,8 @@ void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
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const struct alpha_pll_config *config);
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void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
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const struct alpha_pll_config *config);
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void clk_lucid_ole_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
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const struct alpha_pll_config *config);
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void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
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const struct alpha_pll_config *config);
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void clk_stromer_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
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