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ARM: dts: exynos: Use standard arrays of generic PHYs for EHCI/OHCI devices
Move USB PHYs to a standard arrays for Exynos EHCI/OHCI devices. This resolves the conflict between Exynos EHCI/OHCI sub-nodes and generic USB device bindings. Once the Exynos EHCI/OHCI sub-nodes are removed, the boards can finally provide sub-nodes for the USB devices using generic USB device bindings. Suggested-by: Måns Rullgård <mans@mansr.com> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Link: https://lore.kernel.org/r/20190726081453.9456-4-m.szyprowski@samsung.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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214b606e90
commit
314de2f6b5
8 changed files with 22 additions and 79 deletions
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@ -380,23 +380,8 @@ ehci: ehci@12580000 {
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clocks = <&clock CLK_USB_HOST>;
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clock-names = "usbhost";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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phys = <&exynos_usbphy 1>;
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status = "disabled";
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};
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port@1 {
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reg = <1>;
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phys = <&exynos_usbphy 2>;
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status = "disabled";
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};
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port@2 {
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reg = <2>;
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phys = <&exynos_usbphy 3>;
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status = "disabled";
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};
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phys = <&exynos_usbphy 1>, <&exynos_usbphy 2>, <&exynos_usbphy 3>;
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phy-names = "host", "hsic0", "hsic1";
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};
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ohci: ohci@12590000 {
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@ -406,13 +391,8 @@ ohci: ohci@12590000 {
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clocks = <&clock CLK_USB_HOST>;
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clock-names = "usbhost";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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phys = <&exynos_usbphy 1>;
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status = "disabled";
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};
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phys = <&exynos_usbphy 1>;
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phy-names = "host";
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};
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gpu: gpu@13000000 {
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@ -204,9 +204,8 @@ &cpu0 {
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&ehci {
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status = "okay";
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port@0 {
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status = "okay";
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};
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phys = <&exynos_usbphy 1>;
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phy-names = "host";
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};
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&exynos_usbphy {
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@ -520,9 +519,6 @@ &mixer {
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&ohci {
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status = "okay";
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port@0 {
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status = "okay";
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};
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};
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&pinctrl_1 {
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@ -146,13 +146,8 @@ &ehci {
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/* In order to reset USB ethernet */
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samsung,vbus-gpio = <&gpc0 1 GPIO_ACTIVE_HIGH>;
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port@0 {
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status = "okay";
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};
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port@2 {
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status = "okay";
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};
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phys = <&exynos_usbphy 1>, <&exynos_usbphy 3>;
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phy-names = "host", "hsic1";
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};
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&exynos_usbphy {
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@ -105,12 +105,8 @@ &usb3503 {
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};
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&ehci {
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port@1 {
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status = "okay";
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};
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port@2 {
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status = "okay";
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};
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phys = <&exynos_usbphy 2>, <&exynos_usbphy 3>;
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phy-names = "hsic0", "hsic1";
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};
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&sound {
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@ -72,9 +72,8 @@ &buck8_reg {
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};
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&ehci {
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port@1 {
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status = "okay";
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};
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phys = <&exynos_usbphy 2>;
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phy-names = "hsic0";
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};
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&mshc_0 {
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@ -88,13 +88,8 @@ &exynos_usbphy {
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&ehci {
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samsung,vbus-gpio = <&gpx3 5 1>;
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status = "okay";
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port@1 {
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status = "okay";
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};
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port@2 {
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status = "okay";
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};
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phys = <&exynos_usbphy 2>, <&exynos_usbphy 3>;
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phy-names = "hsic0", "hsic1";
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};
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&fimd {
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@ -617,12 +617,8 @@ ehci: usb@12110000 {
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clocks = <&clock CLK_USB2>;
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clock-names = "usbhost";
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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phys = <&usb2_phy_gen 1>;
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};
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phys = <&usb2_phy_gen 1>;
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phy-names = "host";
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};
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ohci: usb@12120000 {
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@ -632,12 +628,8 @@ ohci: usb@12120000 {
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clocks = <&clock CLK_USB2>;
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clock-names = "usbhost";
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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phys = <&usb2_phy_gen 1>;
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};
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phys = <&usb2_phy_gen 1>;
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phy-names = "host";
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};
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usb2_phy_gen: phy@12130000 {
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@ -189,26 +189,16 @@ usbhost2: usb@12110000 {
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compatible = "samsung,exynos4210-ehci";
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reg = <0x12110000 0x100>;
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interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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phys = <&usb2_phy 1>;
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};
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phys = <&usb2_phy 1>;
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phy-names = "host";
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};
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usbhost1: usb@12120000 {
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compatible = "samsung,exynos4210-ohci";
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reg = <0x12120000 0x100>;
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interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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phys = <&usb2_phy 1>;
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};
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phys = <&usb2_phy 1>;
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phy-names = "host";
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};
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usb2_phy: phy@12130000 {
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