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ARM: dts: exynos: Use standard arrays of generic PHYs for EHCI/OHCI devices

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Move USB PHYs to a standard arrays for Exynos EHCI/OHCI devices. This
resolves the conflict between Exynos EHCI/OHCI sub-nodes and generic USB
device bindings. Once the Exynos EHCI/OHCI sub-nodes are removed, the
boards can finally provide sub-nodes for the USB devices using generic USB
device bindings.

Suggested-by: Måns Rullgård <mans@mansr.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Link: https://lore.kernel.org/r/20190726081453.9456-4-m.szyprowski@samsung.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Marek Szyprowski 2019-07-26 10:14:53 +02:00 committed by Greg Kroah-Hartman
parent 214b606e90
commit 314de2f6b5
8 changed files with 22 additions and 79 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

28
arch/arm/boot/dts/exynos4.dtsi
View file

@ -380,23 +380,8 @@ ehci: ehci@12580000 {
clocks = <&clock CLK_USB_HOST>; clocks = <&clock CLK_USB_HOST>;
clock-names = "usbhost"; clock-names = "usbhost";
status = "disabled"; status = "disabled";
#address-cells = <1>; phys = <&exynos_usbphy 1>, <&exynos_usbphy 2>, <&exynos_usbphy 3>;
#size-cells = <0>; phy-names = "host", "hsic0", "hsic1";
port@0 {
reg = <0>;
phys = <&exynos_usbphy 1>;
status = "disabled";
};
port@1 {
reg = <1>;
phys = <&exynos_usbphy 2>;
status = "disabled";
};
port@2 {
reg = <2>;
phys = <&exynos_usbphy 3>;
status = "disabled";
};
}; };
ohci: ohci@12590000 { ohci: ohci@12590000 {
@ -406,13 +391,8 @@ ohci: ohci@12590000 {
clocks = <&clock CLK_USB_HOST>; clocks = <&clock CLK_USB_HOST>;
clock-names = "usbhost"; clock-names = "usbhost";
status = "disabled"; status = "disabled";
#address-cells = <1>; phys = <&exynos_usbphy 1>;
#size-cells = <0>; phy-names = "host";
port@0 {
reg = <0>;
phys = <&exynos_usbphy 1>;
status = "disabled";
};
}; };
gpu: gpu@13000000 { gpu: gpu@13000000 {

8
arch/arm/boot/dts/exynos4210-universal_c210.dts
View file

@ -204,9 +204,8 @@ &cpu0 {
&ehci { &ehci {
status = "okay"; status = "okay";
port@0 { phys = <&exynos_usbphy 1>;
status = "okay"; phy-names = "host";
};
}; };
&exynos_usbphy { &exynos_usbphy {
@ -520,9 +519,6 @@ &mixer {
&ohci { &ohci {
status = "okay"; status = "okay";
port@0 {
status = "okay";
};
}; };
&pinctrl_1 { &pinctrl_1 {

9
arch/arm/boot/dts/exynos4412-itop-elite.dts
View file

@ -146,13 +146,8 @@ &ehci {
/* In order to reset USB ethernet */ /* In order to reset USB ethernet */
samsung,vbus-gpio = <&gpc0 1 GPIO_ACTIVE_HIGH>; samsung,vbus-gpio = <&gpc0 1 GPIO_ACTIVE_HIGH>;
port@0 { phys = <&exynos_usbphy 1>, <&exynos_usbphy 3>;
status = "okay"; phy-names = "host", "hsic1";
};
port@2 {
status = "okay";
};
}; };
&exynos_usbphy { &exynos_usbphy {

8
arch/arm/boot/dts/exynos4412-odroidu3.dts
View file

@ -105,12 +105,8 @@ &usb3503 {
}; };
&ehci { &ehci {
port@1 { phys = <&exynos_usbphy 2>, <&exynos_usbphy 3>;
status = "okay"; phy-names = "hsic0", "hsic1";
};
port@2 {
status = "okay";
};
}; };
&sound { &sound {

5
arch/arm/boot/dts/exynos4412-odroidx.dts
View file

@ -72,9 +72,8 @@ &buck8_reg {
}; };
&ehci { &ehci {
port@1 { phys = <&exynos_usbphy 2>;
status = "okay"; phy-names = "hsic0";
};
}; };
&mshc_0 { &mshc_0 {

9
arch/arm/boot/dts/exynos4412-origen.dts
View file

@ -88,13 +88,8 @@ &exynos_usbphy {
&ehci { &ehci {
samsung,vbus-gpio = <&gpx3 5 1>; samsung,vbus-gpio = <&gpx3 5 1>;
status = "okay"; status = "okay";
phys = <&exynos_usbphy 2>, <&exynos_usbphy 3>;
port@1 { phy-names = "hsic0", "hsic1";
status = "okay";
};
port@2 {
status = "okay";
};
}; };
&fimd { &fimd {

16
arch/arm/boot/dts/exynos5250.dtsi
View file

@ -617,12 +617,8 @@ ehci: usb@12110000 {
clocks = <&clock CLK_USB2>; clocks = <&clock CLK_USB2>;
clock-names = "usbhost"; clock-names = "usbhost";
#address-cells = <1>; phys = <&usb2_phy_gen 1>;
#size-cells = <0>; phy-names = "host";
port@0 {
reg = <0>;
phys = <&usb2_phy_gen 1>;
};
}; };
ohci: usb@12120000 { ohci: usb@12120000 {
@ -632,12 +628,8 @@ ohci: usb@12120000 {
clocks = <&clock CLK_USB2>; clocks = <&clock CLK_USB2>;
clock-names = "usbhost"; clock-names = "usbhost";
#address-cells = <1>; phys = <&usb2_phy_gen 1>;
#size-cells = <0>; phy-names = "host";
port@0 {
reg = <0>;
phys = <&usb2_phy_gen 1>;
};
}; };
usb2_phy_gen: phy@12130000 { usb2_phy_gen: phy@12130000 {

18
arch/arm/boot/dts/exynos54xx.dtsi
View file

@ -189,26 +189,16 @@ usbhost2: usb@12110000 {
compatible = "samsung,exynos4210-ehci"; compatible = "samsung,exynos4210-ehci";
reg = <0x12110000 0x100>; reg = <0x12110000 0x100>;
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
phys = <&usb2_phy 1>;
#address-cells = <1>; phy-names = "host";
#size-cells = <0>;
port@0 {
reg = <0>;
phys = <&usb2_phy 1>;
};
}; };
usbhost1: usb@12120000 { usbhost1: usb@12120000 {
compatible = "samsung,exynos4210-ohci"; compatible = "samsung,exynos4210-ohci";
reg = <0x12120000 0x100>; reg = <0x12120000 0x100>;
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
phys = <&usb2_phy 1>;
#address-cells = <1>; phy-names = "host";
#size-cells = <0>;
port@0 {
reg = <0>;
phys = <&usb2_phy 1>;
};
}; };
usb2_phy: phy@12130000 { usb2_phy: phy@12130000 {