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clk: ingenic: Read bypass register only when there is one
Rework the clock code so that the bypass register is only read when there is actually a bypass functionality. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20210530164923.18134-4-paul@crapouillou.net Tested-by: 周琰杰 (Zhou Yanjie)<zhouyanjie@wanyeetech.com> # on CU1830-neo/X1830 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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249592bf6d
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315a8423b2
1 changed files with 11 additions and 8 deletions
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@ -99,13 +99,14 @@ ingenic_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
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od_enc = ctl >> pll_info->od_shift;
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od_enc &= GENMASK(pll_info->od_bits - 1, 0);
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ctl = readl(cgu->base + pll_info->bypass_reg);
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if (!pll_info->no_bypass_bit) {
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ctl = readl(cgu->base + pll_info->bypass_reg);
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bypass = !pll_info->no_bypass_bit &&
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!!(ctl & BIT(pll_info->bypass_bit));
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bypass = !!(ctl & BIT(pll_info->bypass_bit));
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if (bypass)
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return parent_rate;
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if (bypass)
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return parent_rate;
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}
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for (od = 0; od < pll_info->od_max; od++) {
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if (pll_info->od_encoding[od] == od_enc)
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@ -225,11 +226,13 @@ static int ingenic_pll_enable(struct clk_hw *hw)
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u32 ctl;
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spin_lock_irqsave(&cgu->lock, flags);
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ctl = readl(cgu->base + pll_info->bypass_reg);
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if (!pll_info->no_bypass_bit) {
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ctl = readl(cgu->base + pll_info->bypass_reg);
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ctl &= ~BIT(pll_info->bypass_bit);
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ctl &= ~BIT(pll_info->bypass_bit);
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writel(ctl, cgu->base + pll_info->bypass_reg);
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writel(ctl, cgu->base + pll_info->bypass_reg);
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}
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ctl = readl(cgu->base + pll_info->reg);
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