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ASoC: cs42l43: Use fls to calculate the pre-divider for the PLL
Use fls to calculate the pre-divider and input frequency for the PLL, this is marginally faster than the previous loop. Suggested-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com> Link: https://msgid.link/r/20240125103117.2622095-7-ckeepax@opensource.cirrus.com Signed-off-by: Mark Brown <broonie@kernel.org>
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1 changed files with 3 additions and 4 deletions
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@ -1338,10 +1338,9 @@ static int cs42l43_enable_pll(struct cs42l43_codec *priv)
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dev_dbg(priv->dev, "Enabling PLL at %uHz\n", freq);
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dev_dbg(priv->dev, "Enabling PLL at %uHz\n", freq);
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while (freq > cs42l43_pll_configs[ARRAY_SIZE(cs42l43_pll_configs) - 1].freq) {
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div = fls(freq) -
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div++;
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fls(cs42l43_pll_configs[ARRAY_SIZE(cs42l43_pll_configs) - 1].freq);
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freq /= 2;
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freq >>= div;
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}
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if (div <= CS42L43_PLL_REFCLK_DIV_MASK) {
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if (div <= CS42L43_PLL_REFCLK_DIV_MASK) {
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int i;
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int i;
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