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Merge branch 'sunxi/dt' into next/dt

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This avoids a boot regression

* sunxi/dt:
  Revert "ARM: dts: sunxi: unify APB1 clock"
  Revert "ARM: dts: sunxi: Use sun4i-a10-apb1-clk for sun6i/sun8i apb2 clocks."

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2014-11-27 16:05:30 +01:00
commit 321081f5f5
6 changed files with 60 additions and 12 deletions
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12
arch/arm/boot/dts/sun4i-a10.dtsi
View file

@ -174,11 +174,19 @@ apb0_gates: clk@01c20068 {
"apb0_ir1", "apb0_keypad";
};
apb1: clk@01c20058 {
apb1_mux: apb1_mux@01c20058 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-apb1-mux-clk";
reg = <0x01c20058 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
clock-output-names = "apb1_mux";
};
apb1: apb1@01c20058 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-apb1-clk";
reg = <0x01c20058 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
clocks = <&apb1_mux>;
clock-output-names = "apb1";
};

12
arch/arm/boot/dts/sun5i-a10s.dtsi
View file

@ -162,11 +162,19 @@ apb0_gates: clk@01c20068 {
"apb0_ir", "apb0_keypad";
};
apb1: clk@01c20058 {
apb1_mux: apb1_mux@01c20058 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-apb1-mux-clk";
reg = <0x01c20058 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
clock-output-names = "apb1_mux";
};
apb1: apb1@01c20058 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-apb1-clk";
reg = <0x01c20058 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
clocks = <&apb1_mux>;
clock-output-names = "apb1";
};

12
arch/arm/boot/dts/sun5i-a13.dtsi
View file

@ -161,11 +161,19 @@ apb0_gates: clk@01c20068 {
clock-output-names = "apb0_codec", "apb0_pio", "apb0_ir";
};
apb1: clk@01c20058 {
apb1_mux: apb1_mux@01c20058 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-apb1-mux-clk";
reg = <0x01c20058 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
clock-output-names = "apb1_mux";
};
apb1: apb1@01c20058 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-apb1-clk";
reg = <0x01c20058 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
clocks = <&apb1_mux>;
clock-output-names = "apb1";
};

12
arch/arm/boot/dts/sun6i-a31.dtsi
View file

@ -217,11 +217,19 @@ apb1_gates: clk@01c20068 {
"apb1_daudio1";
};
apb2: clk@01c20058 {
apb2_mux: apb2_mux@01c20058 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-apb1-clk";
compatible = "allwinner,sun4i-a10-apb1-mux-clk";
reg = <0x01c20058 0x4>;
clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
clock-output-names = "apb2_mux";
};
apb2: apb2@01c20058 {
#clock-cells = <0>;
compatible = "allwinner,sun6i-a31-apb2-div-clk";
reg = <0x01c20058 0x4>;
clocks = <&apb2_mux>;
clock-output-names = "apb2";
};

12
arch/arm/boot/dts/sun7i-a20.dtsi
View file

@ -222,11 +222,19 @@ apb0_gates: clk@01c20068 {
"apb0_iis2", "apb0_keypad";
};
apb1: clk@01c20058 {
apb1_mux: apb1_mux@01c20058 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-apb1-mux-clk";
reg = <0x01c20058 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
clock-output-names = "apb1_mux";
};
apb1: apb1@01c20058 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-apb1-clk";
reg = <0x01c20058 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
clocks = <&apb1_mux>;
clock-output-names = "apb1";
};

12
arch/arm/boot/dts/sun8i-a23.dtsi
View file

@ -189,11 +189,19 @@ apb1_gates: clk@01c20068 {
"apb1_daudio0", "apb1_daudio1";
};
apb2: clk@01c20058 {
apb2_mux: apb2_mux_clk@01c20058 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-apb1-clk";
compatible = "allwinner,sun4i-a10-apb1-mux-clk";
reg = <0x01c20058 0x4>;
clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
clock-output-names = "apb2_mux";
};
apb2: apb2_clk@01c20058 {
#clock-cells = <0>;
compatible = "allwinner,sun6i-a31-apb2-div-clk";
reg = <0x01c20058 0x4>;
clocks = <&apb2_mux>;
clock-output-names = "apb2";
};